KR100304194B1 - Digital-analog converter for high-integrated circuit - Google Patents

Abstract

PURPOSE: A digital-analog converter for high-integrated circuit is provided to minimize an area of a digital-analog converter by reducing the number of resistance and the number of switch. CONSTITUTION: A digital-analog converter(201) includes a primary conversion stage(305) and a secondary conversion stage(405). The digital-analog converter(201) converts analog values corresponding to digital values of N-bits on the basis of reference voltages(VREFT,VREFB). The digital-analog converter(201) coverts the N-bits to analog values by dividing the N bits into two parts, namely bits of X number and bits of Y number. Upper bits of X number are provided to the primary conversion stage(305). Lower bits of Y number are provided to the secondary conversion stage(405). The primary conversion stage(305) converts the upper bits to a primary voltage range. An upper and a lower voltage(V1,V2) are provided to the secondary conversion stage(405). The secondary conversion stage(405) generates analog values corresponding to the primary voltage range and the lower bits. The primary conversion stage(305) is formed with a voltage generation circuit(300) and the first decoder(100). The secondary conversion stage(405) is formed with a voltage distribution circuit(400), a selection circuit(500), and the second decoder(200).

Description

Digital-analog converting circuit for reducing number of devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital-analog converters, and more particularly to digital-to-analog converters for high integration.

Digital-to-analog conversion circuits are demanding higher levels of resolution that characterize the converter as the system becomes more efficient.

1 is a circuit diagram showing the configuration of a digital-analog conversion circuit according to the prior art.

Referring to FIG. 1, the digital-to-analog converter includes a decoder 10, a voltage distribution circuit 20, and a selection circuit 30. The decoder 10 receives an N-bit digital signal from the outside and decodes it to output 2 ^N selection signals and non-selection signals, and the selection signal is a signal for selecting one of the distribution voltages of the voltage distribution circuit. to be. The voltage divider circuit 20 includes a plurality of resistors R1 to Rn connected in series between the first and second input terminals to which the upper reference voltage VREFT and the lower reference voltage VREFB are applied. The reference voltages are divided according to the resistance ratio. The selection circuit 30 selects one of several distribution voltages in response to the selection signal and the non-selection signals, which are connected to the switches {sw0 to sw (n-1)} connected to the connection points of the respective resistors. Is determined due to. The op amp connected to the output terminal of the selection circuit amplifies the level of the selected divided voltage and outputs an analog signal corresponding to the N-bit digital input signal. The digital-analog circuit having the above configuration reacts sensitively by the precision of passive elements such as resistors and switches in terms of resolution, and the resolution is an indicator of the characteristics of the transducer. Is improved.

However, the digital-to-analog converter described above has a problem in that the resistance increases exponentially as the resolution is increased and the number of bits of the input digital signal is increased. In addition, the resistance column of the voltage divider circuit is determined by the number of bits of the input digital signal to be 2 ^{N. In} the case of 4 bits, only 2 or ⁴ resistors can operate, but in the case of a 20 bit input digital signal, ^As many as ²⁰ resistors are needed. In addition, as the number of resistors increases exponentially, the number of switches corresponding to their respective connection points increases, and the area of the decoder generating signals for driving these switches also increases. As described above, as the number and area of the resistors, the switches, and the decoders increase, the noise component due to the switching increases, resulting in a deterioration of the characteristics of the digital-analog conversion circuit.

It is an object of the present invention to reduce the number of resistors and switches in a digital-to-analog conversion circuit to minimize the area and to increase the resolution.

1 is a circuit diagram showing the configuration of a digital-analog conversion circuit according to the prior art:

2 is a circuit diagram showing a configuration of a digital-analog conversion circuit according to an embodiment of the present invention:

3 is a circuit diagram showing in detail a digital-analog conversion circuit configuration according to an embodiment of the present invention:

4A is an operation timing diagram of switches in response to a drive signal of a first decoder:

4B is an operation timing diagram of switches in response to a selection signal of a second decoder:

5 shows an output of an analog signal corresponding to digital signals:

* Explanation of symbols on the main parts of the drawings

100: first decoder 200: second decoder

300: voltage generator 400: voltage divider

500: selection

[Configuration]

According to one aspect for achieving the above object, a digital-to-analog conversion circuit for converting an N-bit digital value into a corresponding analog value decodes a first portion of the N bits to obtain a plurality of first decoder signals. A first decoder for providing audio data; A voltage generator circuit operating in response to the first decoder signals and generating a preliminary voltage range corresponding to a first portion of the N bits based on an upper reference voltage and a lower reference voltage; A voltage divider circuit for dividing the reserve voltage range into a plurality of divided voltages, the plurality of divided voltages defining a plurality of sub-ranges that fall within the reserve voltage range; A second decoder for decoding a second portion of the N bits to provide a plurality of second decoder signals; Operate in response to the plurality of second decoder signals, and select one of the plurality of sub-ranges based on the plurality of second decoder signals to generate an analog value corresponding to the N-bit digital value. And a selection circuit.

In this embodiment, the voltage generation circuit comprises: a plurality of switches operating in response to the plurality of first decoder signals; And a plurality of resistors electrically connected to the plurality of switches to generate the preliminary voltage range based on the upper reference voltage and the lower reference voltage.

In this embodiment, the plurality of switches comprises a switch of a first group and a switch of a second group, the switches of the first group including the plurality of resistors based on the first decoder signals. The resistors of the first group generate a first voltage and the resistors of the second group produce a second voltage.

In this embodiment, the second group of switches comprises a plurality of switch pairs, one switch pair being selected from the switch pairs based on the plurality of first decoder signals, the selected switch pair being the The first and second voltages are selected to generate the preliminary voltage range.

In this embodiment, the total number of bits of the first portion of the N bits and the total number of bits of the second portion of the N bits are the same.

In this embodiment, the total number of bits of the first portion of the N bits and the total number of bits of the second portion of the N bits do not match.

In this embodiment, the plurality of resistors includes (2 ^N -1) resistors having the same value.

EXAMPLE

2 is a block diagram of a digital-analog conversion circuit according to an embodiment of the present invention. The digital-to-analog conversion circuit 201 includes a first conversion stage 305 and a second conversion stage 405. The digital-to-analog conversion circuit 201 converts the corresponding analog value into an N-bit digital value based on the reference voltages VREFT and VREFB. In particular, the N bits are converted to an analog value by dividing the N bits into two parts, X bits and Y bits. X upper bits of the N bits are provided to the first transform stage 305, and Y lower bits of the N bits are provided to the second transform stage 405.

The first conversion stage 305 converts the upper bits of the N bits into a primary voltage range. The preliminary voltage range is defined as an upper voltage V1 and a lower voltage V2. The upper and lower voltages V1 and V2 of the preliminary voltage range are provided to the second conversion stage 405.

The second conversion stage 405 generates a corresponding analog value based on the preliminary voltage range provided by the first conversion stage 305 and the Y lower bits. Specifically, the second conversion stage 405 determines a clearer analog value corresponding to the N bits using the lower voltage V1 and the upper voltage V2 of the preliminary voltage range. In other words, the first conversion stage 305 determines a coarse voltage range that includes the corresponding analog value, and the second conversion stage 405 further refines the preliminary voltage range to refine the corresponding analog value. Create As a result, fewer resistors and switches will be used for the digital-to-analog conversion.

The first transform stage 305 includes a first decoder 100 that decodes the X upper bits into a plurality of first decoder signals. The first decoder signals control the generation of the preliminary voltage range by the voltage generation circuit 300. For example, in the case of 4-bit digital data, the first decoder 100 generates eight decoder signals based on the upper two bits of the four bits. The voltage generator 300 divides the voltage range of the reference voltages VREFT and VREFB into four sub-ranges, each sub-range being the full range of the reference voltages VREFT and VREFB. Define 1/4 of. The voltage generator circuit 300 generates the preliminary voltage range, and the upper voltage V1 and the lower voltage V2 define a selected sub-range.

The second conversion stage 405 includes a voltage division circuit 400, which divides the preliminary voltage range from the first conversion stage 305 into a plurality of division voltages. The second decoder 200 decodes the lower Y bits of the N bits to provide a plurality of second decoder signals. The selection circuit 500 selects one of the plurality of distribution voltages based on the plurality of second decoder signals to generate the corresponding analog value. Specifically, the voltage division circuit 400 subdivides the preliminary voltage range from the first conversion stage 305 to provide the division voltage to the selection circuit 500. The second decoder 200 generates the second decoder signals based on the lower Y bits. The second decoder signals select one of the distribution voltages to provide the corresponding analog value. In other words, second decoder signals generated by the second decoder 200 are used to subdivide the preliminary voltage range provided by the first conversion stage 305.

3 is a preferred embodiment of a digital-to-analog conversion circuit for 4-bit digital-to-analog conversion according to the present invention. The voltage generation circuit 300 includes a plurality of switches and a plurality of resistors that generate the preliminary voltage range based on the reference voltages VREFT and VREFB. Specifically, the switches are responsive to decoder signals generated by the first decoder 100. The decoder signals generated by the first decoder 100 control the states of each of the switches in the voltage generation circuit 300 of FIG. 3. In particular, the switch pairs wt0 / swb0-to wt3 / swb3 are provided by a series of first decoder signals provided from the first decoder 100. Similarly, the switches sw0 to sw3 are controlled by a series of second decoder signals provided from the first decoder 100.

The first and second decoder signals generated by the first decoder 100 interlock to select the preliminary voltage range. For example, in the case of a 4-bit digital value, the upper two bits are provided to the first decoder 100, with the result that the first and second decoder signals are generated by the first decoder 100. The second decoder signals are used to divide the resistors RM1, RM2, RM3 into two separate groups. The 1 decoder signals control the states of the switch pairs wt0 / swb0 to wt3 / swb3. For example, one of the second decoder signals controls the switch pair swt3 / swb3. In addition, the state of the switch pair swt3 / swb3 is controlled in association with the state of the switch sw3.

The voltage divider circuit 400 includes a series of resistors RL1 to RL4 that divide the preliminary voltage range to define a series of sub-range voltages. Each of the sub-range voltages is included in the preliminary voltage range generated by the voltage divider circuit 300.

The selection circuit 500 includes switches sw11 to sw14. The second decoder 200 generates decoder signals based on the lower Y bits to control the states of each of the switches swt11 to sw14. Thus, the second decoder 200 closes the switch corresponding to the appropriate sub-range voltage. The corresponding sub-range voltage is connected to node N3 to produce the corresponding analog voltage Vout.

4A and 4B are timing diagrams for describing an operation of the digital-analog conversion circuit of FIG. 3. Specifically, FIG. 4A illustrates a state of each of the switches included in the voltage generation circuit 300 based on the upper two bits of the N bits. Logic high in FIG. 4A indicates that the corresponding switch is in a closed state. In contrast, a logic low indicates that the corresponding switch is in an open state. 4A illustrates the association of switch pairs with first switches in the second switches. For example, when D3 = 0 and D2 = 0, the switch pairs wt0 / swb0 are closed and the swoosh sw0 is open. The remaining switches sw1 to sw3 are closed. As a result, the upper voltage V1 of the preliminary voltage range is provided as a result of the voltage drop across the coupling of the resistors RM1, RM2, RM3. Similarly, voltage VREFB provides the lower voltage V2 of the preliminary voltage range via switch swb0. As a result, the switches of the voltage generating circuit 300 are used to generate a reserve voltage range.

4B shows the state of all switches in the selection circuit 500 based on the lower bits of the N bits. For example, when D0 = 0 and D1 = 0, the switch sw11 is closed while the switches sw12 to sw14 are open. As a result, the voltage generated at the input of the switch sw11 is connected to the node N3 to provide the corresponding analog voltage VAout.

5 is a graph of digital values to analog output to be converted in the digital-to-analog conversion circuit of FIG. 1 or FIG. As described above, by dividing the 4-bit digital value into the upper two bits and the lower two bits, the voltage generation circuit 300 uses 3 (2-1) resistors. Similarly, voltage divider circuit 400 uses 4 (2 ² ) resistors. As a result, the present invention can reduce the number of resistors used to provide a digital-analog change compared to the prior art. In this embodiment, although the digital-to-analog conversion circuit of the present invention has been described using an even bit digital value, it is obvious that the present invention can also be applied to converting an odd bit digital value. For example, a digital-to-analog conversion circuit can be constructed by dividing a 5-bit digital value into upper two bits and lower three bits.

According to the present invention, the input digital signal is divided into upper and lower bits and applied to reduce the number of resistors and the number of switches connected thereto. In addition, the circuit configuration of the decoder for driving the switches is simplified, thereby reducing the total area.

Claims (7)

A digital-to-analog conversion circuit for converting an N-bit digital value into a corresponding analog value, comprising: a first decoder (100) for decoding a first portion of the N bits to provide a plurality of first decoder signals; A voltage generation circuit operating in response to the first decoder signals and generating a preliminary voltage range corresponding to a first portion of the N bits based on an upper reference voltage VREFT and a lower reference voltage VREFB; 300); A voltage division circuit (400) for dividing the preliminary voltage range into a plurality of division voltages, the plurality of division voltages defining a plurality of sub-ranges falling within the preliminary voltage range; A second decoder (200) for decoding a second portion of the N bits to provide a plurality of second decoder signals; Operate in response to the plurality of second decoder signals, and select one of the plurality of sub-ranges based on the plurality of second decoder signals to generate an analog value corresponding to the N-bit digital value. And a selection circuit (500). 2. The apparatus of claim 1, wherein the voltage generation circuit (300) comprises: a plurality of switches operating in response to the plurality of first decoder signals; A plurality of resistors electrically connected to the plurality of switches, the plurality of resistors generating the preliminary voltage range based on the upper reference voltage VREFT and the lower reference voltage VREFB. Circuit. 3. The apparatus of claim 2, wherein the plurality of switches comprises switches of a first group and switches of a second group, wherein the switches of the first group comprise the plurality of resistors based on the first decoder signals. The resistors of the group and the resistors of the second group, wherein the resistors of the first group generate a first voltage V1 and the resistors of the second group generate a second voltage V2. Digital-to-analog conversion circuit. 4. The switch of claim 3, wherein the second group of switches comprises a plurality of switch pairs, one switch pair being selected from the switch pairs based on the plurality of first decoder signals, wherein the selected switch pair is And selecting the first and second voltages (V1, V2) to generate the preliminary voltage range. 2. The digital-analog conversion circuit of claim 1, wherein the total number of bits of the first portion of the N bits and the total number of bits of the second portion of the N bits are the same. 2. The digital-analog conversion circuit of claim 1, wherein the total number of bits of the first portion of the N bits and the total number of bits of the second portion of the N bits do not coincide. 3. The digital-to-analog conversion circuit of claim 2, wherein the plurality of resistors comprise (2 ^N -1) resistors having the same value.

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