KR19990026108A - Central Processing Unit with Malfunction Protection - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit having a malfunction prevention function adapted to prevent a malfunction of a CPU caused by a change of a program counter value due to noise or the like. The present invention relates to a system processing information (about a system program command). A program counter and a program memory block configured to store and output a program memory, and a program counter to count the information output state of the program memory and output a signal related to the information output state, and to program instructions in the program counter and program memory block. There is an instruction comparison circuit and execution block composed of instruction registers, instruction decoders, instruction execution blocks, etc. that receive execution data and process instructions, and program counter values are not used in the program memory area or hardware. A reset to control a reset operation by receiving a program counter supervisor block for detecting a change in an address of a non-area area, a reset pin input signal, an instruction comparison enable signal of a comparison circuit, and a reset generation control signal of the program counter supervisor block; It is configured to include a control circuit block.

Description

Central Processing Unit with Malfunction Protection

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit, and more particularly, to a central processing unit having a malfunction preventing function adapted to prevent a malfunction of a CPU caused by a change in a program counter value due to noise or the like.

Hereinafter, a description will be given of a central processing unit of the prior art with reference to the accompanying drawings.

Fig. 1 is a block diagram of a central processing unit of the prior art, and Fig. 2 is an operation timing diagram of the central processing unit of the prior art.

The prior art central processing unit (CPU) first includes a program memory unit 12 for storing and outputting information (relative to a command of a system program) relating to the overall system operation, and counting the information output state of the program memory unit and outputting the information. A program memory block (1) comprising a program counter (13) for outputting a signal relating to a state, an instruction register and a command decoder for receiving data about a program instruction from the program memory block (1) and processing an execution instruction; It is largely comprised of an instruction processing block and an execution block 2 composed of an instruction execution block and the like, and a reset control circuit block 3 that receives a reset pin input signal and controls a reset operation.

The instruction processing block and the execution block 1 may include a first instruction register 4 for fetching an instruction or data stored in a program memory unit into a CPU, and the first instruction. Second and third instruction registers IR_1 (IR_2) 5 and 6 for shift-outputting information output by being fetched from the register 4, and the second and third instruction registers IR_1 and IR_2 5; A comparison output unit 7 which compares the shift output information of (6) with each other and outputs an instruction comparison enable signal, and receives the instruction comparison enable signal of the comparison output unit 7 and receives the third instruction register IR_2; Shift output information, i.e., an instruction decoder 8 for decoding an instruction, an execution block 9 for executing an instruction according to the decoded instruction, a decoding signal of the instruction decoder 8 and a reset signal OR operation of the edge detection signal And force OR arithmetic unit 10 that receives a reset signal is configured to include an edge detection circuit 11 to the edge detection operation of the reset signal.

At this time, the output signal of the OR operator 10 is input to the comparison output unit 7 and the program counter 13.

The reset control circuit block 3 receives the reset pin input signal and the command comparison enable signal of the comparison output unit 7 to control the reset operation.

The instruction register as described above is a block in which instructions to be executed in the CPU are stored. In the fetching step, the system controller accesses and stores the instructions at the memory address indicated by the program counter 13.

The program counter is a block that contains a memory address that contains the next program instruction to be executed by the computer in the CPU. The CPU retrieves instructions from the storage device indicated by the program counter 13 and retrieves them one by one. It executes a command and adds the contents of the counter one by one each time the command is retrieved.

The prior art central processing unit fetches instructions from the program memory unit 12 twice, compares them, finds a case of inconsistency, and prevents CPU malfunction.

The central processing unit of the prior art has only a function of preventing a malfunction of the CPU by finding a case where the function of preventing a CPU malfunction occurring in the instruction execution process is compared by fetching the instruction twice and comparing them.

If the program counter value is changed to an address of an unused area of the program memory area or an area in which no hardware exists, the CPU cannot be detected.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art central processing unit, and has a central processing unit having a malfunction preventing function adapted to prevent a malfunction of a CPU caused by a change in a program counter value due to noise or the like. The purpose is to provide.

1 is a configuration block diagram of a central processing unit of the prior art

2 is an operation timing diagram of a central processing unit of the prior art.

3 is a block diagram of a central processing unit according to the present invention;

4 is a detailed configuration diagram of a program counter check block according to the present invention.

5 is a map of a program memory according to the present invention;

* Explanation of symbols for main parts of the drawings

30. Program counter watch block

31. Program counter and program memory block

32. Reset Control Circuit Block

33. Instruction Comparison Circuit and Execution Block

The central processing unit with a malfunction preventing function of the present invention, which is adapted to prevent a malfunction of a CPU caused by a change of a program counter value due to noise or the like, stores and outputs information (about a command of a system program) relating to the entire system operation. A program counter and a program memory block comprising a program memory, a program counter for counting the information output state of the program memory and outputting a signal relating to the information output state, and data relating to program instructions in the program counter and the program memory block. Instruction comparison circuit and execution block composed of instruction registers for receiving and processing execution instructions, instruction decoder, instruction execution block, etc., and areas in which program counter values are not used among program memory areas or areas where no hardware exists. A reset control circuit block for controlling a reset operation by receiving a program counter monitoring block for detecting a change in an address, a reset pin input signal, an instruction comparison enable signal of a comparison circuit, and a reset generation control signal of the program counter monitoring block. Characterized in that comprises a.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the central processing unit having a malfunction preventing function of the present invention.

Fig. 3 is a block diagram of the central processing unit according to the present invention, and Fig. 4 is a detailed block diagram of the program counter monitoring block according to the present invention. 5 is a map of a program memory according to the present invention.

The configuration of the central processing unit having the malfunction preventing function of the present invention, which is adapted to prevent the malfunction of the CPU caused by the change of the program counter value due to noise or the like, is as follows.

A program memory 34 for storing and outputting information (about a command of a system program) relating to the overall system operation; a program counter for counting the information output state of the program memory 34 and outputting a signal relating to the information output state thereof; A program counter and program memory block 31 comprising: 35, and instruction registers 38, 39, and 40 for receiving data about program instructions from the program counter and program memory block 31 and processing execution instructions. ), An instruction comparison circuit and execution block 33 including a command decoder 42, an instruction execution block 43, and the like, a reset control circuit block 32 for receiving a reset pin input signal and controlling a reset operation, and a program counter. If the value is changed to an address of an unused or non-hardware area of the program memory area, it is detected. Is largely made up of counter surveillance program blocks (30).

The instruction comparison circuit and the execution block 33 may include a first instruction register 38 for fetching an instruction or data stored in the program memory 34 into the CPU, and the first instruction register 38. Second and third instruction registers IR_1 (IR_2) 39 and 40 for shift-outputting information output by being fetched from one instruction register 38 and the second and third instruction registers IR_1 and IR_2 ( 39 and 40, the comparison output unit 41 for comparing the shift output information of 40 and outputting an instruction comparison enable signal, and receiving the instruction comparison enable signal of the comparison output unit 41 and receiving the third instruction register ( Shift output information output from the IR_2) 40, that is, the instruction decoder 42 for decoding the instruction, the instruction execution block 43 for executing the instruction according to the decoded instruction, and the decoding of the instruction decoder 42. Edge detection of the signal and the reset signal And a call-OR operation to the output OR operation part 45 that receives a reset signal is configured to include an edge detection circuit 44 to the edge detection operation of the reset signal.

At this time, the output signal of the OR operation unit 45 is input to the comparison output unit 41 and the program counter 35.

The detailed configuration of the program counter monitoring block 30 is the same as in FIG.

First, a non-existent hardware address detection circuit 47 that receives an address input from the program counter 35 and detects when the address is a hardware address that does not exist in the system, and a ROM address not used in the system. An unused ROM address register 48 for storing and outputting information relating to the information; a minimum address and a maximum address of an unused area output from the unused ROM address register 48; and an address in the program counter 35. OR operation of the comparison circuit 49 for receiving and comparing an input, the non-existent hardware address detection signal of the non-existent hardware address detection circuit 47 and the comparison signal of the comparison circuit 49 to output an abnormal address detection signal. When the OR calculating unit 50 and the abnormal address detection signal of the OR calculating unit 50 are inputted It is configured to include a selection circuit 51 that outputs the internal reset hardware generation control signal and a program counter value correction control signal for causing a jump to a specific address in accordance with the selected reference value of the selection register 52 is written by my choice.

The reset control circuit block 32 receives the reset pin input signal, the command comparison enable signal of the comparison output unit 41, and the reset generation control signal of the program counter monitoring block 30 to control the reset operation.

As shown in FIG. 5, the space of the program memory 34 is C000 to FFFF, and the area not used is D100 to DFFF and hardware. An area in which s does not exist is described as 0000 to Bfff.

When an error of an address is input to an area where no hardware exists, a non-existent address matching signal is generated by the non-existent hardware address detecting circuit 47, and the abnormal address matching signal is enabled through the OR operation unit 50 to select the circuit. It is inputted by 51.

When an error of an address is input into an unused area, a comparison is made between the minimum and maximum address values of an unused area written in the unused ROM address register 48 and an unused address detection signal is generated through the OR operation unit 50. The abnormal address detection signal is enabled and is input to the selection circuit 51.

As described above, the abnormal address detection signal inputted to the selection circuit 51 generates an internal hardware reset or a program counter value correction control signal that causes the user to jump to a specific address according to a value written to the selection register 52. The CPU will operate normally.

The central processing unit of the present invention having the malfunction preventing function, which is adapted to prevent the malfunction of the CPU caused by the change of the program counter value due to noise or the like, has the following effects.

The program counter monitoring block has a program counter value correction control signal that detects when a program counter value has an unused address or an address value that does not exist in hardware and causes an internal hardware reset or jump to a specific address. It can improve the reliability of the system by enabling normal operation.

Claims (7)

A program memory configured to store and output information about a command of a system program, a program counter and a program memory block including a program counter to output a signal related to an information output state of the program memory; An instruction comparison circuit and an execution block including instruction registers, an instruction decoder, an instruction execution block, and the like, which receive data about a program instruction in the program counter and a program memory block, and execute an instruction; A program counter monitoring block that detects when the program counter value is an address of an unused area or a hardware-free area of the program memory area; And a reset control circuit block configured to receive a reset pin input signal, an instruction comparison enable signal of the comparison circuit, and a reset generation control signal of the program counter monitoring block to control a reset operation. Processing unit. The method of claim 1, wherein the instruction comparison circuit and the execution block comprise: a first instruction register for fetching an instruction or data stored in a program memory into a CPU; Second and third instruction registers IR_1 and IR_2 for shifting out information output by being fetched from the first instruction register; A comparison output unit configured to compare the shift output information of the second and third command registers IR_1 (IR_2) 39 and 40 to output an instruction comparison enable signal; An instruction decoder which receives the instruction comparison enable signal of the comparison output unit and decodes the shift output information output from the third instruction register IR_2, that is, an instruction; An instruction execution block for executing an instruction according to the decoded instruction; An OR operation unit for performing an OR operation on the decoding signal of the command decoder and the edge detection signal of the reset signal; And a edge detection circuit configured to receive a reset signal and perform edge detection of the reset signal. The CPU of claim 2, wherein an output signal of the OR operation unit is input to the comparison output unit and a program counter. The non-existent hardware address detecting circuit of claim 1, wherein the program counter monitoring block receives an address input from a program counter and detects a corresponding address when the address is a hardware address that does not exist in the system; An unused ROM address register for storing and outputting information about ROM addresses not used in the system; A comparison circuit which receives and compares the minimum address, the maximum address of the unused area and the address input from the program counter, output from the unused ROM address register; An OR operation unit for ORing the non-existent hardware address detection signal of the non-existent hardware address detection circuit and the comparison signal of the comparison circuit to output an abnormal address detection signal; A selection circuit for outputting an internal hardware reset generation control signal and a program counter value correction control signal for jumping to a specific address according to a selection reference value of a selection register written by a user when an abnormal address detection signal of the OR operation unit is input; The central processing unit having a malfunction preventing function, characterized in that configured. The selection circuit of claim 4, wherein when an error of an address is input to an area in which no hardware exists, a non-existent address matching signal is generated in a non-existent hardware address detection circuit, and an abnormal address detection signal is enabled through an OR operation unit. Central processing unit having a malfunction prevention function, characterized in that is input to. The non-used address matching signal is generated when an error of an address is input to an unused area compared with the minimum and maximum address values of an unused area written to the unused ROM address register. And the address detection signal is enabled and input to the selection circuit. 7. The abnormal address detection signal input to the selection circuit generates a program counter value correction control signal for causing the user to jump to an internal hardware reset or a specific address according to a value written to the selection register. Central processing unit having a malfunction prevention function characterized in that the CPU to perform a normal operation.