KR19990025198A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR19990025198A
KR19990025198A KR1019970046737A KR19970046737A KR19990025198A KR 19990025198 A KR19990025198 A KR 19990025198A KR 1019970046737 A KR1019970046737 A KR 1019970046737A KR 19970046737 A KR19970046737 A KR 19970046737A KR 19990025198 A KR19990025198 A KR 19990025198A
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South Korea
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forming
film
conductive layer
blanket
hsg film
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KR1019970046737A
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Korean (ko)
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홍승완
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윤종용
삼성전자 주식회사
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Priority to KR1019970046737A priority Critical patent/KR19990025198A/en
Publication of KR19990025198A publication Critical patent/KR19990025198A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

스토리지 전극의 형성방법에 대해 개시된다. 본 발명의 방법은, 반도체기판상에 트랜지스터를 형성하는 단계와, 상기 트렌지스터의 소스전극과 연결되는 비트라인을 형성하는 단계와, 상기 비트라인이 형성된 결과물 전면에 층간절연막을 형성하는 단계와, 상기 층간절연막에 콘택 홀을 형성하여 그 내부에 상기 비트라인과 연결되는 제1도전층을 형성하는 단계와, 상기 제1도전층 형성 후 결과물 전면에 소정두께의 제2도전층, 제1블랭킷 HSG막 및 비반사층을 차례로 형성하는 단계와, 상기 비반사층을 패터닝하는 단계와, 상기 패터닝된 비반사층을 식각마스크로 적용하여 상기 제1블랭킷 HSG막 및 제2도전층을 차례로 패터닝하는 단계와, 상기 제1블랭킷 HSG막 및 제2도전층의 패터닝 후 결과물 전면에 소정두께의 제2블랭킷 HSG막을 형성하는 단계와, 상기 제2도전층을 몸체로 하여 그 윗면에는 제1블랭킷 HSG막이, 그 측면에는 제2블랭킷 HSG막이 형성된 스토리지 전극을 완성하도록 일부분의 제2블랭킷 HSG막 및 비반사층을 제거하는 단계를 구비하여 이루어진 것을 특징으로 한다. 이에 따라, 본 발명에 따른 반도체장치의 제조방법에 의하면, 그 측면 및 윗면에 블랭킷 HSG막을 형성한 도전층을 스토리지 전극으로 사용함으로써 전극의 표면적이 증대되어 캐패시터의 정전용량을 향상시킬 수 있다.A method of forming a storage electrode is disclosed. The method includes forming a transistor on a semiconductor substrate, forming a bit line connected to a source electrode of the transistor, forming an interlayer insulating film on the entire surface of the resultant product on which the bit line is formed; Forming a contact hole in the interlayer insulating film to form a first conductive layer connected to the bit line in the interlayer insulating film; and forming a second conductive layer and a first blanket HSG film having a predetermined thickness on the entire surface of the resultant after forming the first conductive layer. And sequentially forming a non-reflective layer, patterning the non-reflective layer, and patterning the first blanket HSG film and the second conductive layer in sequence by applying the patterned non-reflective layer as an etch mask; Forming a second blanket HSG film having a predetermined thickness on the entire surface of the resultant after patterning the first blanket HSG film and the second conductive layer; and forming a first blanket HSG film on the upper surface of the first Kit for the HSG film, the side characterized in that made in a step of removing the second blanket HSG film and a non-reflection layer of a portion to complete the storage electrode film second blanket HSG formed. Accordingly, according to the method for manufacturing a semiconductor device according to the present invention, the surface area of the electrode can be increased by using a conductive layer having a blanket HSG film formed on the side and top thereof as a storage electrode, thereby improving the capacitance of the capacitor.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 정전용량을 증대시킬 수 있는 반도체장치의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of increasing capacitance.

최근의 메모리소자는 그 집적도가 향상됨에 따라, 소자의 기억장치로 사용되는 캐패시터의 정전용량(cell capacitance)의 유지가 힘들어졌다. 즉, 어떤 정보를 기억할 수 있는 단위 기억소자의 갯수(비트(bit) 수)는 획기적으로 증대한 반면에, 그 소자들의 면적증가는 한정되어 있어, 한정된 면적에 아주 많은 기억소자를 구성해야 하는 어려움이 생긴 것이다. 이에 따라, 적은 면적에서도 높은 정전용량을 가지는 기억소자를 구성하기 위하여 Ta2O5, (Ba,Sr)TiO3등의 고유전물질을 유전체막으로 이용하거나, 스토리지 노드의 높이를 획기적으로 증가시켜서 기억소자의 면적을 높이는 등의 실험들이 이루어졌다. 그러나, 상기 고유전물질을 유전체막으로 사용할 경우에는 반도체장치를 제작하는 공정이 복잡해지며, 그 막질의 절연특성이 좋지않은 문제점이 있다. 또한, 스토리지 노드의 높이를 증가시켜 면적을 높이는 것은 후속되는 반도체 제조공정 예컨대 평탄화와 관계되는 공정에서 문제점을 유발하게 되어 반도체장치의 제작에 어려움을 가져오게 된다.In recent years, as the integration of memory devices has been improved, it is difficult to maintain cell capacitance of capacitors used as memory devices. In other words, the number of unit memory devices (bits) that can store some information has increased dramatically, while the area increase of the devices is limited, which makes it difficult to configure a large number of memory devices in a limited area. This is what happened. Accordingly, in order to form a memory device having a high capacitance even in a small area, high dielectric materials such as Ta 2 O 5 and (Ba, Sr) TiO 3 may be used as the dielectric film, or the height of the storage node may be increased dramatically. Experiments were conducted to increase the area of memory devices. However, when the high dielectric material is used as the dielectric film, the process of fabricating a semiconductor device is complicated, and the insulating property of the film quality is poor. In addition, increasing the area by increasing the height of the storage node causes a problem in a subsequent semiconductor manufacturing process, for example, a process related to planarization, which causes difficulty in manufacturing a semiconductor device.

본 발명이 이루고자 하는 기술적 과제는, 블랭킷 HSG(blanket Hemi Spherical Grain)를 스토리지 전극으로 사용함으로써 종래기술의 문제점을 해결함과 동시에 캐패시터의 정전용량을 증대시킬 수 있는 반도체장치의 제조방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for manufacturing a semiconductor device capable of increasing the capacitance of a capacitor while at the same time solving the problems of the prior art by using a blanket Hemi Spherical Grain (HSG) as a storage electrode. .

도 1 내지 도 7은 본 발명에 따른 반도체장치의 제조방법을 설명하기 위한 공정순서도이다.1 to 7 are process flowcharts for explaining a method for manufacturing a semiconductor device according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

100...반도체기판 1,2...게이트전극100 ... semiconductor substrate 1,2 gate electrodes

3...소스전극 4...드레인전극3.Source electrode 4 ... Drain electrode

5,10...절연막 6...스페이서5,10 ... insulator 6 ... spacer

12,14...제1층간절연막, 제2층간절연막12,14 Interlayer dielectric film, first interlayer dielectric film

16...제1도전층 18...제2도전층16 ... 1st conductive layer 18 ... 2nd conductive layer

20,24...제1블랭킷 HSG막, 제2블랭킷 HSG막20,24 ... First blanket HSG film, Second blanket HSG film

22...비반사층22 ... Non-reflective layer

상기 과제를 이루기 위하여 본 발명에 의한 방법은, 반도체기판상에 트랜지스터를 형성하는 단계와, 상기 트렌지스터의 소스전극과 연결되는 비트라인을 형성하는 단계와, 상기 비트라인이 형성된 결과물 전면에 층간절연막을 형성하는 단계와, 상기 층간절연막에 콘택 홀을 형성하여 그 내부에 상기 비트라인과 연결되는 제1도전층을 형성하는 단계와, 상기 제1도전층 형성 후 결과물 전면에 소정두께의 제2도전층, 제1블랭킷 HSG막 및 비반사층을 차례로 형성하는 단계와, 상기 비반사층을 패터닝하는 단계와, 상기 패터닝된 비반사층을 식각마스크로 적용하여 상기 제1블랭킷 HSG막 및 제2도전층을 차례로 패터닝하는 단계와, 상기 제1블랭킷 HSG막 및 제2도전층의 패터닝 후 결과물 전면에 소정두께의 제2블랭킷 HSG막을 형성하는 단계와, 상기 제2도전층을 몸체로 하여 그 윗면에는 제1블랭킷 HSG막이, 그 측면에는 제2블랭킷 HSG막이 형성된 스토리지 전극을 완성하도록 일부분의 제2블랭킷 HSG막 및 비반사층을 제거하는 단계를 구비하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the method includes forming a transistor on a semiconductor substrate, forming a bit line connected to a source electrode of the transistor, and forming an interlayer insulating layer on the entire surface of the resultant product on which the bit line is formed. Forming a contact hole in the interlayer insulating layer, forming a first conductive layer connected to the bit line in the interlayer insulating layer, and forming a second conductive layer having a predetermined thickness on the entire surface of the resultant after forming the first conductive layer. And sequentially forming a first blanket HSG film and an antireflective layer, patterning the antireflective layer, and applying the patterned nonreflective layer as an etch mask to sequentially pattern the first blanket HSG film and the second conductive layer. And forming a second blanket HSG film having a predetermined thickness on the entire surface of the resultant after patterning the first blanket HSG film and the second conductive layer, and the second conductive layer. A body to the upper surface thereof is characterized by having been made in the step of 1 blanket HSG film, the side to remove the second blanket HSG film and a non-reflection layer of a portion to complete the storage electrode film second blanket HSG formed.

이하, 첨부한 도면을 참조하여 본 발명을 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described the present invention.

도 1 내지 도 7은 본 발명에 따른 반도체장치의 제조방법을 설명하기 위한 공정순서도로, COB(Capacitor Over Bit-line) 구조의 스토리지 전극의 표면적을 증대시키기 위하여 전극의 도전물질로 블랭킷 HSG를 이용한다.1 to 7 are flowcharts for explaining a method of manufacturing a semiconductor device according to the present invention. In order to increase the surface area of a storage electrode having a capacitor over bit-line (COB) structure, a blanket HSG is used as a conductive material of the electrode. .

도 1을 참조하면, 먼저 반도체기판(100)상에 소자형성영역과 분리영역을 정의하기 위하여 트렌치 소자분리방법을 통한 분리영역(101)을 형성한 후, 결과물 전면에 소정의 반도체 제조공정을 거쳐 게이트전극(1,2), 소스전극(3) 및 드레인전극(4)으로 구성된 트랜지스터를 형성한다. 이어서, 상기 트랜지스터를 보호하기 위한 제1절연막(5) 및 스페이서(6)를 형성한 후 상기 소스전극(3)과 연결되는 비트라인(BL)을 형성하고, 결과물 전면에 제1층간절연막(12) 및 제2층간절연막(14)을 차례로 형성한다. 다음으로, 상기 비트라인(BL)과 제1도전층(16)을 통해 연결되는 제2도전층(18) 예컨대 불순물이 도핑된 다결정실리콘을 소정두께 형성하고, 상기 제2도전층(18)위에 제1블랭킷 HSG막(20)을 형성한다. 여기서, 상기 제2도전층(18) 및 제1블랭킷 HSG막(20)은 스토리지 전극으로 사용되고, 미설명부호 10은 절연막을 나타낸다.Referring to FIG. 1, first, in order to define a device formation region and a separation region on a semiconductor substrate 100, a separation region 101 is formed through a trench isolation method, and then a predetermined semiconductor manufacturing process is performed on the entire surface of the resultant substrate. A transistor composed of the gate electrodes 1 and 2, the source electrode 3 and the drain electrode 4 is formed. Subsequently, after forming the first insulating film 5 and the spacer 6 to protect the transistor, a bit line BL connected to the source electrode 3 is formed, and the first interlayer insulating film 12 is formed on the entire surface of the resultant. ) And the second interlayer insulating film 14 are formed in this order. Next, the second conductive layer 18 connected to the bit line BL and the first conductive layer 16, for example, a polysilicon doped with impurities, is formed to a predetermined thickness, and formed on the second conductive layer 18. The first blanket HSG film 20 is formed. Here, the second conductive layer 18 and the first blanket HSG film 20 are used as storage electrodes, and reference numeral 10 denotes an insulating film.

다음으로 도 2를 참조하면, 상기 제1블랭킷 HSG막(20)위에 스토리지 전극의 패터닝시 빛의 난반사를 방지하기 위하여 비반사층(Anti Reflective Coating layer : ARC층)(22)을 소정두께 형성한다. 이때의 비반사층(22)은 빛의 난반사를 방지할 뿐만 아니라 후속공정에서 형성되는 제2블랭킷 HSG막의 식각 마스크로도 이용된다.Next, referring to FIG. 2, an anti-reflective coating layer (ARC layer) 22 is formed on the first blanket HSG film 20 to prevent diffuse reflection of light when the storage electrode is patterned. In this case, the anti-reflective layer 22 may be used as an etching mask of the second blanket HSG film formed in a subsequent process as well as preventing diffuse reflection of light.

다음으로 도 3을 참조하면, 상기 비반사층(22)위에 포토레지스트 도포, 마스크 노광 및 현상 등의 공정을 거쳐 소정 크기의 포토레지스트 패턴(도시하지 않음)을 형성한 후, 이 패턴을 식각마스크로 적용하여 상기 비반사층(22)을 패터닝한다.Next, referring to FIG. 3, a photoresist pattern (not shown) having a predetermined size is formed on the non-reflective layer 22 through a process such as photoresist coating, mask exposure, and development, and then the pattern is used as an etching mask. Apply to pattern the anti-reflective layer 22.

다음으로 도 4를 참조하면, 먼저 상기 포토레지스트 패턴을 제거한 후, 상기 패터닝된 비반사층(22)을 식각마스크로 적용하여 상기 제1블랭킷 HSG막(20) 및 제2도전층(18)을 패터닝한다.Next, referring to FIG. 4, first, after removing the photoresist pattern, the patterned non-reflective layer 22 is applied as an etch mask to pattern the first blanket HSG film 20 and the second conductive layer 18. do.

다음으로 도 5를 참조하면, 상기 도 4의 공정 후 결과물 전면에 제2블랭킷 HSG막(24)을 소정두께 형성한다.Next, referring to FIG. 5, a second thickness of the blanket HSG film 24 is formed on the entire surface of the resultant after the process of FIG. 4.

다음으로 도 6을 참조하면, 각각의 스토리지 전극을 분리하기 위해 일부분의 제2블랭킷 HSG막을 제거한 모습을 나타낸다.Next, referring to FIG. 6, a portion of the second blanket HSG film is removed to separate each storage electrode.

다음으로 도 7을 참조하면, 상기 비반사층을 제거하여 도시된 바와 같이 불순물이 도핑된 다결정실리콘으로 이루어진 제2도전층(18)을 몸체로 하여 그 측면 및 윗면까지 제2블랭킷 HSG막(24) 및 제1블랭킷 HSG막(20)으로 인해 표면적이 향상된 스토리지 전극을 완성한다.Next, referring to FIG. 7, the second blanket HSG film 24 is formed by removing the non-reflective layer and forming a second conductive layer 18 made of polycrystalline silicon doped with impurities as its body. And a storage electrode having an improved surface area due to the first blanket HSG film 20.

이상 설명된 바와 같이 본 발명에 따른 반도체장치의 제조방법에 의하면, 그 측면 및 윗면에 블랭킷 HSG막을 형성한 도전층을 스토리지 전극으로 사용함으로써 전극의 표면적이 증대되어 캐패시터의 정전용량을 향상시킬 수 있다.As described above, according to the method of manufacturing a semiconductor device according to the present invention, by using a conductive layer having a blanket HSG film formed on its side and top thereof as a storage electrode, the surface area of the electrode can be increased to improve the capacitance of the capacitor. .

Claims (1)

반도체기판상에 트랜지스터를 형성하는 단계;Forming a transistor on the semiconductor substrate; 상기 트렌지스터의 소스전극과 연결되는 비트라인을 형성하는 단계;Forming a bit line connected to the source electrode of the transistor; 상기 비트라인이 형성된 결과물 전면에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on an entire surface of the resultant product on which the bit lines are formed; 상기 층간절연막에 콘택 홀을 형성하여 그 내부에 상기 비트라인과 연결되는 제1도전층을 형성하는 단계;Forming a contact hole in the interlayer insulating layer to form a first conductive layer connected to the bit line therein; 상기 제1도전층 형성 후 결과물 전면에 소정두께의 제2도전층, 제1블랭킷 HSG막 및 비반사층을 차례로 형성하는 단계;Forming a second conductive layer having a predetermined thickness, a first blanket HSG film, and an anti-reflective layer on the entire surface of the resultant after the first conductive layer is formed; 상기 비반사층을 패터닝하는 단계;Patterning the antireflective layer; 상기 패터닝된 비반사층을 식각마스크로 적용하여 상기 제1블랭킷 HSG막 및 제2도전층을 차례로 패터닝하는 단계;Applying the patterned anti-reflective layer as an etch mask to sequentially pattern the first blanket HSG film and the second conductive layer; 상기 제1블랭킷 HSG막 및 제2도전층의 패터닝 후 결과물 전면에 소정두께의 제2블랭킷 HSG막을 형성하는 단계; 및Forming a second blanket HSG film having a predetermined thickness on the entire surface of the resultant after patterning the first blanket HSG film and the second conductive layer; And 상기 제2도전층을 몸체로 하여 그 윗면에는 제1블랭킷 HSG막이, 그 측면에는 제2블랭킷 HSG막이 형성된 스토리지 전극을 완성하도록 일부분의 제2블랭킷 HSG막 및 비반사층을 제거하는 단계를 구비하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.And removing a portion of the second blanket HSG film and the anti-reflective layer to complete the storage electrode having the first conductive HSG film on the upper surface and the second blanket HSG film on the side thereof. A method of manufacturing a semiconductor device, characterized in that.
KR1019970046737A 1997-09-11 1997-09-11 Manufacturing Method of Semiconductor Device KR19990025198A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100575855B1 (en) * 1999-10-26 2006-05-03 주식회사 하이닉스반도체 A method of fabricating a capacitor in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100575855B1 (en) * 1999-10-26 2006-05-03 주식회사 하이닉스반도체 A method of fabricating a capacitor in semiconductor device

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