KR19990017112A - Timing signal generator and method for device testing - Google Patents

Abstract

The present invention precisely controls the edge of a timing signal supplied to a device under test (DUT), thereby generating a timing signal suitable for testing a high-speed device at high speed. The present invention relates to a generator, and the present invention compares the magnitude of the falling edge and the rising edge of the timing signal generated as a reference and generates a selection signal for logical combination of the falling edge and the rising edge according to the result, By combining the delayed falling edge and rising edge according to the selection signal and generating the result as a timing signal, the timing signal suitable for high-speed device test is provided, and the timing is controlled by controlling the rising and falling edges of the timing signal. By generating signals, precise timing signals can be generated. Will.

Description

Apparatus and method for generating timing signals for device testing

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the generation of timing signals for testing various devices. More particularly, the present invention relates to high-speed control by precisely controlling edges of timing signals supplied to a device under test (DUT). A timing signal generator and method for testing a device for generating a timing signal suitable for testing a device at high speed.

In general, many timing signals are required to test the functions of various devices (Test Burn-In System, Memory, Waveform Generator, etc.).

For example, a timing signal required for writing / reading data directly to a memory cell, a timing signal for comparing data written to the memory in one cycle by a comparator, a timing signal for storing bad data, and the like. It is.

The conventional timing signal generator that generates such a timing signal generates a desired timing signal by controlling the timing signal in units of 1 ms.

However, the conventional timing signal generator as described above has a disadvantage in that a timing signal for precisely controlling a high speed (15 pico second) device is not generated because the timing signal is generated by controlling the generated timing signal in units of 1 ms.

Accordingly, the present invention has been proposed to solve various problems generated from the conventional timing signal generator as described above.

An object of the present invention is to provide an apparatus and a method for generating a timing signal for a device test that precisely controls an edge of a timing signal supplied to a device under test (DUT) to generate an accurate timing signal. There is this.

It is another object of the present invention to provide a timing signal generator and method for testing a device that generate timing signals suitable for testing a high speed device at high speed.

Technical means for achieving the objects of the present invention,

Comparison means for comparing a falling edge of the timing signal generated as a reference with a rising edge of the timing signal and generating a selection signal for logically combining the falling edge and the rising edge according to the result;

Falling edge delay means for delaying the falling edge of the timing signal by a predetermined time and outputting the delayed edge;

Rising edge delay means for delaying and rising the rising edge of the timing signal by a predetermined time;

And a timing signal control and generating means for selectively logically combining the falling edge and the rising edge generated by the falling edge / rising edge delay means according to the selection signal generated by the comparing means, and generating the result as a timing signal.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

1 is a signal timing diagram required for a general device test;

2 is a block diagram of a timing signal generator for testing a device according to the present invention;

3 is a detailed circuit diagram of a timing signal control and generation unit of FIG. 2;

4 is a detailed circuit diagram of a timing signal changer of FIG. 3;

5 is an input / output timing diagram of each part of the timing signal control and generation unit of FIG. 3;

* Explanation of symbols for the main parts of the drawings

10: comparison unit, 20: falling edge delay unit, 30: rising edge delay unit, 40: timing signal control and generation unit

2 is a block diagram of a timing signal generator for device testing according to the present invention.

Here, reference numeral 10 is for comparing the falling edge (T _- down) of the timing signal generated as a reference with the rising edge (T _- up) of the timing signal and logically combining the falling edge and the rising edge according to the result. Comparing unit for generating a selection signal, reference numeral 20 is a falling edge delay unit for delaying and outputting the falling edge of the timing signal by a predetermined time, reference numeral 30 is output by delaying the rising edge of the timing signal by a predetermined time Is a rising edge delay unit.

Further, reference numeral 40 denotes a logical combination of falling edges and rising edges generated by the falling edge / rising edge delay units 20 and 30 respectively according to the selection signal SEL generated by the comparing unit 10. And a timing signal control and generator that generates the result as a timing signal.

In the above, the timing signal control and generation unit 40, as shown in Figure 3, the first buffer 41 for buffering the polarity of the timing signal, and the first edge of the logic of the falling edge and the rising edge of the timing signal A logical sum element 42, a logical AND element 43 for ANDing the falling edge and the rising edge of the timing signal, a second buffer 44 for buffering the level of the input timing signal, and the second buffer 44 The first logical sum element 42 and the logical product element 43 in accordance with the second logical sum element 45 for logical sum of the output signal and paging signal PAGING, and the output signal of the second logical sum element 45. A timing signal changing unit 46 for selecting one of the outputs of the output signal and changing the output signal to a predetermined level, and buffering the delay mask values of the input timing signals, respectively; According to the output values of the third and fourth buffers 47 and 48, the output values of the second logic element 45 are determined. A timing signal level adjusting unit 49 for adjusting and outputting the third logic logic element 51 for logically combining the output signal of the timing signal level adjusting unit 49 and the output signal of the timing signal changing unit 46; An exclusive logical sum device 52 for exclusively ORing the polarities of the output signal of the third logical sum element 51 and the timing signal output from the first buffer 41 and generating the result as a timing signal, and the exclusive logic sum element And a fifth buffer 53 for buffering and outputting the timing signal output from the 52.

In addition, as illustrated in FIG. 4, the timing signal changing unit 46 includes an inverter 46a for inverting the selection signal output from the comparing unit 10, the selection signal, and the second logical and the A first NAND gate 46b for NAND ring the enable signal output from 45), a second NAND ring for the output signal of the inverter 46a, and the enable signal output from the second logic element 45; A first logical element 46d that logically multiplies the NAND gate 46c, the output signal of the first NAND gate 46b, and the delayed falling edge, the output signal of the second NAND gate 46c, and the delayed rising To a logic logic element 46f that logically sums the signals output from the second logical AND elements 46e and the logical AND elements 46d and 46e, which are ANDs the edges, and outputs the result as a timing signal. It is composed.

The operation of the timing signal generator for testing a device according to the present invention having such a configuration will be described in detail with reference to FIGS. 1 to 5 as follows.

First, a timing signal required for the device test is as shown in FIG. 1, wherein (A) indicates a RAS (Rom Address Strobe), CAS (Column Address Strobe), WE (Write Enable), and OE ( Control signal such as Output Enable), and a high speed / high precision signal is required to test the device. Further, (B) is a signal generated when the request signal is low (L) in the device test mode, and (C) is a signal generated when the request signal is high (H) in the device test mode, respectively.

As such, in order to accurately generate the timing signals required in the device test modes, it is necessary to precisely control the falling edge and the rising edge of the timing signal as shown in FIG.

To this end, the present invention provides a timing signal generator as shown in FIG.

That is, as shown in Figure 2, the comparator 10 compares the magnitude of the falling edge (T _- down) and the rising edge (T _- up) of the timing signal generated as a reference to the timing signal of the rear stage according to the result The control and generation unit 40 generates a selection signal SEL for selecting a logic combination element for adjusting the rising and falling edges.

That is, when the falling edge and the rising edge signal of the timing signal as shown in (B) and (C) of FIG. 5 are respectively input, the comparing unit 10 compares the magnitudes of the two edges, and the magnitude of the rising edge is the falling edge. Since the falling edge and the rising edge must be logically multiplied in order to generate the timing signal required for the test as shown in FIG. 5D, the low signal L is generated by the selection signal SEL. The timing signal control and generator 40 is provided.

In addition, when the falling edge and the rising edge signal of the timing signal as shown in (E) and (F) of FIG. 5 are respectively input, the comparing unit 10 compares the magnitudes of the two edges to the size of the falling edge. Since it is larger than the magnitude, in order to make the timing signal required for the test as shown in FIG. 5 (H), the falling edge and the rising edge must be logically combined to generate a high signal H as the selection signal SEL to generate the timing signal. Provided to the control and generation unit 40.

In addition, the falling edge delay unit 20 serves to delay for a predetermined time in order to control the falling edge (T ₋ down) of the timing signal, and likewise, the rising edge delay unit 30 also has the rising edge of the timing signal. In order to control (T _- up), it plays a role of delaying the rising edge signal input for an arbitrary time.

In this way, the falling edge and the rising edge respectively delayed for a predetermined time are transmitted to the timing signal control and generation unit 40, respectively, and are logically combined and processed according to the selection signal generated in the comparison unit 10.

Here, the operation of the timing signal control and generation unit 40 will be described in detail.

As shown in FIG. 3, the timing signal control and generation unit 40 buffers the polarity (T_polarity) of the timing signal with the first buffer 41, and the first logic element 42 delays the timing signal. The falling edge T_down and the delayed rising edge T_up are ORed together, and the result value is transferred to the timing signal changing unit 46. The AND product 43 also logically multiplies the falling edge and the rising edge of the timing signal. The resultant value is transmitted to the timing signal changer 46.

In addition, the second buffer 44 buffers the timing signal level value T_level, and the second logical sum element 45 logically sums the output signal of the second buffer 44 and the paging signal PAGING and the result value. Is provided to the timing signal changing unit 46 as an enable signal EN.

Then, the timing signal changing unit 46 controls the output of the first logical sum element 42 and the output of the logical product element 43 according to the selection signal provided from the comparator 10 to obtain a desired timing signal. .

That is, as shown in FIG. 4, the timing signal changing unit 46 inverts the selection signal SEL to the inverter 46a, and the first NAND gate 46b and the selection signal SEL. NAND ring the enable signal EN obtained from the second logic element 45, and NAND ring the output signal of the inverter 46a and the enable signal EN to the second NAND gate 46c. Done. Subsequently, the falling edge delayed by the falling edge delay unit 20 and the output signal of the first NAND gate 46b are logically multiplied by the first logical multiplier element 46d, and the second logical multiplier 46e The rising edge delayed by the rising edge delay unit 30 is multiplied by the output signal of the second NAND gate 46c. In addition, the logic sum element 46f performs an OR on the signals output from the first and second AND products 46d and 46e, respectively, and outputs the result as a timing signal Y1 for testing the device.

In other words, when the selection signal SEL output from the comparator 10 is the high signal H, that is, the magnitude of the falling edge of the timing signal is equal to the rising edge of the timing signal. If it is larger than the magnitude, the falling edge output from the falling edge delay unit 20 and the rising edge output from the rising edge delay unit 30 are ORed together to output the result as a controlled timing signal.

Further, when the selection signal SEL output from the comparator 10 is the low signal L, that is, when the rising edge of the timing signal is larger than the falling edge of the timing signal, the falling edge delay is delayed. The rising edge output from the rising edge output unit 30 and the rising edge output from the rising edge delay unit 30 are ANDed to output the result as a controlled timing signal.

On the other hand, the third and fourth buffers 47 and 48 buffer the delay mask values T_MaskB and T_MaskA of the input timing signals, respectively, to adjust the timing signal levels for use in refreshing, reading, and writing the signals. The timing signal level adjusting unit 49 outputs a signal for adjusting the timing signal level based on a plurality of input signals. Accordingly, the third logical sum element 51 logically sums the signal output from the timing signal level controller 49 and the timing signal generated by the timing signal changer 46, and the exclusive logic sum element 52 The polarity of the timing signal generated by the exclusive OR of the signal output from the third logical sum element 51 and the timing signal polarity signal buffered in the first buffer 41 is adjusted. The polarity-adjusted timing signal is buffered by the fifth buffer 53 and output as a timing signal for testing the device.

In addition, since the timing signal buffered and output from the fifth buffer 53 is a timing signal precisely controlled to 150 Hz, the timing signal can be used as a test timing signal even for a high-speed device.

As described above, the device test timing signal generator according to the present invention has the effect of generating a precise timing signal by controlling the falling edge and the rising edge of the timing signal.

In addition, since a precise timing signal controlled to 150 kHz can be generated, it can be used as a timing signal even when testing a high-speed device.

Claims (5)

Comparison means for comparing a magnitude of the falling edge of the timing signal generated with the reference and the magnitude of the rising edge of the timing signal and generating a selection signal for logically combining the falling edge and the rising edge according to the result; Falling edge delay means for delaying the falling edge of the timing signal by a predetermined time and outputting the delayed edge; Rising edge delay means for delaying and rising the rising edge of the timing signal by a predetermined time; And a timing signal control and generation means for selectively logically combining the falling edge and the rising edge generated by the falling edge / rising edge delay means according to the selection signal generated by the comparing means, and generating the result as a timing signal. A timing signal generator for testing a device, characterized in that configured. The method of claim 1, The comparing means outputs a high signal H as the selection signal when the falling edge is larger than the rising edge as a result of comparing the magnitude of the falling edge of the timing signal with the magnitude of the rising edge of the timing signal. And a low signal (L) as the selection signal when an edge is larger than the falling edge. The method of claim 1, The timing signal control and generation means includes: a first buffer for buffering the polarity of the timing signal, a first logic element for ORing the falling edge and the rising edge of the timing signal, and the falling edge and rising edge of the timing signal; A logical multiplication device for multiplying, a second buffer for buffering the level of an input timing signal, a second logical sum device for performing an OR of the output signal of the second buffer and a paging signal, and an output signal of the second logical sum device A timing signal changing unit which selects one of the outputs of the first logical sum element and the logical multiplication element and changes it to a predetermined level, and outputs a third and fourth buffers which respectively buffer delay mask values of the input timing signal. And a timing signal level adjusting unit for adjusting and outputting an output value of the second logical sum device according to the output values of the third and fourth buffers. And a third logical sum device for ORing the output signal of the first logic signal and the output signal of the timing signal changer, the output signal of the third logic sum device and the timing signal polarity output from the first buffer, and generating a result as a timing signal. And a fifth buffer configured to buffer and output a timing signal output from the exclusive logical sum element. The method of claim 1 or 3, The timing signal changing unit may include an inverter for phase inverting a selection signal output from the comparison means, a first NAND gate for NAND ringing the selection signal and an enable signal output from the second logic unit, and an output of the inverter. A second NAND gate for NAND-ringing a signal and an enable signal output from the second logical sum device, a first logical element for ANDing the output signal of the first NAND gate, and a delayed rising edge, and the second NAND gate; And a logic logical element for performing an OR operation on the output signal of the second logical AND element, which is ANDed by the delayed rising edge, and a signal output from the first and second logical AND elements, respectively, and outputting the result as a timing signal. Timing signal generator for device testing. By comparing the magnitude of the falling edge and the rising edge of the reference timing signal, a high signal is generated when the size of the falling edge is greater than the size of the rising edge, and a low signal is generated when the size of the rising edge is greater than the size of the falling edge. A select signal output step A falling / rising edge delay step of delaying and outputting the falling and rising edges of the timing signal by a predetermined time; According to the selection signal generated in the selection signal output step, if the selection signal is a high signal, the falling edge and the rising edge generated in the falling edge / rising edge delay step are respectively logically ORed; And a timing signal output step of outputting a result value as a timing signal for testing the device.