KR100228815B1 - Timing signal generator for device test and the method - Google Patents

Abstract

The present invention precisely controls the edge of a timing signal supplied to a device under test (DUT), thereby generating a timing signal suitable for testing a high-speed device at high speed. The present invention relates to a generator, and the present invention compares the magnitude of the falling edge of the timing signal and the rising edge of the timing signal generated as a reference, and generates a selection signal for logical combination of the falling edge and the rising edge according to the result, By combining the delayed falling edge and rising edge according to the selection signal and generating the result as a timing signal, it provides a timing signal suitable for high-speed device test, and also controls the rising edge and falling edge of the timing signal to control the timing. By generating signals, precise timing signals can be generated. Will.

Description

Timing signal generator and method for device testing

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the generation of timing signals for testing various devices. More particularly, the present invention relates to high-speed control by precisely controlling edges of timing signals supplied to a device under test (DUT). A timing signal generator and method for testing a device for generating a timing signal suitable for testing a device at high speed.

In general, many timing signals are required to test the functions of various devices (Test Burn-In System, Memory, Waveform Generator, etc.).

For example, a timing signal required for writing / reading data directly to a memory cell, a timing signal for comparing data written to the memory in one cycle by a comparator, a timing signal for storing bad data, and the like. It is.

A conventional timing signal generator for generating such a timing signal generates a desired timing signal by controlling the timing signal in units of 1 ns.

However, the conventional timing signal generator as described above has a disadvantage in that the timing signal for precisely controlling a high speed (15 pico second) device is not generated because it is generated by controlling the generated timing signal in units of 1 ns.

Accordingly, the present invention has been proposed to solve various problems arising from the conventional timing signal generator as described above, and the present invention is to precisely adjust the edge of the timing signal supplied to the device under test (DUT). It is an object of the present invention to provide a timing signal generator and method for testing a device that can be controlled to generate an accurate timing signal.

It is another object of the present invention to provide a timing signal generator and method for testing a device that generate timing signals suitable for testing a high speed device at a high speed.

Technical means for achieving the objects of the present invention, a selection signal for comparing the falling edge of the timing signal generated with the reference and the rising edge of the timing signal and logical combination of the falling edge and the rising edge according to the result. Comparing means for generating; Falling edge delay means for delaying the falling edge of the timing signal by a predetermined time and outputting the delayed edge; Rising edge delay means for delaying and rising the rising edge of the timing signal by a predetermined time; And a timing signal control and generation means for selectively logically combining the falling edge and the rising edge generated by the falling edge / rising edge delay means according to the selection signal generated by the comparing means to generate a timing signal.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

1 is a signal timing diagram required for general device testing.

2 is a block diagram of a timing signal generator for testing a device according to the present invention.

FIG. 3 is a detailed circuit diagram of a timing signal control and generator of FIG.

4 is a detailed circuit diagram of a timing signal changer of FIG.

5 is an input / output timing diagram of respective parts of the timing signal control and generation unit of FIG.

* Explanation of symbols for main parts of the drawings

10: comparison unit 20: falling edge delay unit

30: rising edge delay unit 40: timing signal control and generation unit

2 is a block diagram of a timing signal generator for device testing according to the present invention.

Here, reference numeral 10 compares the falling edge T_down of the timing signal generated as a reference with the rising edge T_up of the timing signal and generates a selection signal for logical combination of the falling edge and the rising edge according to the result. Reference numeral 20 denotes a falling edge delay unit for delaying and outputting the falling edge of the timing signal by a predetermined time, and reference numeral 30 denotes a rising edge delay for delaying and outputting the rising edge of the timing signal by a predetermined time. It is wealth.

Further, reference numeral 40 denotes a logical combination of falling edges and rising edges generated by the falling edge / rising edge delay units 20 and 30 respectively according to the selection signal SEL generated by the comparing unit 10. And a timing signal control and generator that generates the result as a timing signal.

In the above, the timing signal control and generation unit 40, as shown in Figure 3, the first buffer 41 for buffering the polarity of the timing signal, and the logic for the OR of the falling edge and the rising edge of the timing signal A logical logic element 42, a logical AND element 43 for ANDing the falling edge and the rising edge of the timing signal, a second buffer 44 for buffering the level of the input timing signal, and the second buffer ( The first logical sum element 42 and the logical product element 43 in accordance with the second logical sum element 45 for logical sum of the output signal of the 44 and the paging signal PAGING, and the output signal of the second logical sum element 45. A timing signal changing unit 46 which selects one of the outputs of the output signal, changes the output signal to a predetermined level, and outputs a third and fourth buffers 47 and 48 which buffer the delay mask values of the input timing signals. And the output of the second logical element 45 according to the output values of the third and fourth buffers 47 and 48. A timing signal level adjusting unit 49 for adjusting and outputting the control signal; and a third logical sum element 51 for ORing the output signal of the timing signal level adjusting unit 49 and the output signal of the timing signal changing unit 46; An exclusive logical sum element 52 and an exclusive logical sum of the polarity of the output signal of the third logical sum element 51 and the timing signal output from the first buffer 41 and generating a result as a timing signal; The fifth buffer 53 is configured to buffer and output a timing signal output from the element 52.

In addition, as shown in FIG. 4, the timing signal changing unit 46 includes an inverter 46a for phase inverting the selection signal output from the comparison unit 10, the selection signal and the second logic element. A first NAND gate 46b for NAND ringing the enable signal output from 45, an NAND ring for the output signal of the inverter 46a and the enable signal output from the second logic element 45; 2nd NAND gate 46c, a first logical element 46d that logically multiplies the output signal of the first NAND gate 46b, and the delayed falling edge, and the output signal of the second NAND gate 46c and the delayed signal. Logic sum element 46f for logically combining the second logical multiplication element 46e for logically multiplying the rising edge and the signals output from the first and second logical multiplication elements 46d and 46e, and outputting the result as a timing signal. It consists of).

The operation of the timing signal generator for testing a device according to the present invention having such a configuration will be described in detail with reference to FIGS. 1 to 5 as follows.

First, the timing signal required for the device test is shown in FIG. 1 of the accompanying drawings, wherein (A) indicates the device's row address strobe (RAS), column address strobe (CAS), write enable (WE), and OE ( Control signal such as Output Enable), and a high speed / high precision signal is required to test the device. Further, (B) is a signal generated when the request signal is low (L) in the device test mode, and (C) is a signal generated when the request signal is high (H) in the device test mode, respectively.

As described above, in order to accurately generate the required timing signals in the device test mode, it is necessary to precisely control the falling edge and the rising edge of the timing signal as shown in FIG.

To this end, the present invention provides a timing signal generator as shown in FIG.

That is, as shown in FIG. 2, the comparator 10 compares the magnitudes of the falling edge T_down and the rising edge T_up of the timing signal generated as a reference, and controls and generates a timing signal at a later stage according to the result. The unit 40 generates a selection signal SEL for selecting a logic combination element for adjusting the rising and falling edges.

That is, when the falling edge and the rising edge signal of the timing signal such as the fifth (b) and the fifth (c) are respectively input, the comparing unit 10 compares the magnitudes of the two edges to obtain the rising edge. Since it is larger than the size of the falling edge, in order to generate the timing signal required for the test as shown in FIG. 5 (d), the falling edge and the rising edge must be logically multiplied to generate the low signal L as the selection signal SEL. The timing signal control and generator 40 is provided.

In addition, when the falling edge and the rising edge signals of the timing signals such as the fifth (e) and the fifth (f) are respectively input, the comparing unit 10 increases the magnitude of the falling edge when comparing the sizes of the two edges. Since it is larger than the size of the edge, in order to make the timing signal required for the test as shown in FIG. 5 (h), the falling edge and the rising edge must be ORed together to generate the high signal H as the selection signal SEL to generate the timing signal. Provided to the signal control and generator 40.

In addition, the falling edge delay unit 20 serves to delay for a predetermined time in order to control the falling edge (T-down) of the timing signal, and likewise, the rising edge delay unit 30 also has the rising edge of the timing signal. To control (T_up) serves to delay the rising edge signal input for a certain time.

In this way, the falling edge and the rising edge respectively delayed for a predetermined time are transmitted to the timing signal control and generation unit 40, respectively, and are logically combined and processed according to the selection signal generated in the comparison unit 10.

Here, the operation of the timing signal control and generation unit 40 will be described in detail.

As shown in FIG. 3, the timing signal control and generation unit 40 buffers the polarity (T_polarity) of the timing signal with the first buffer 41, and the first logic element 42 is configured to control the timing signal. The delayed falling edge T_down and the delayed rising edge T_up are ORed together to transfer the result to the timing signal changing unit 46, and the AND product 43 also logics the falling edge and the rising edge of the timing signal. The result is multiplied and transmitted to the timing signal changer 46.

In addition, the second buffer 44 buffers the timing signal level value T_level, and the second logical sum element 45 logically sums the output signal of the second buffer 44 and the paging signal PAGING and the result value. Is provided to the timing signal changing unit 46 as an enable signal EN.

Then, the timing signal changing unit 46 controls the output of the first logical sum element 42 and the output of the logical product element 43 according to the selection signal provided from the comparator 10 to obtain a desired timing signal. .

That is, the timing signal changing unit 46 inverts the selection signal SEL to the inverter 46a as shown in FIG. 4, and the selection signal SEL to the first NAND gate 46b. And an enable signal EN obtained from the second logic element 45, and a NAND output signal of the inverter 46a and the enable signal EN to the second NAND gate 46c. Ring. Subsequently, the falling edge delayed by the falling edge delay unit 20 and the output signal of the first NAND gate 46b are logically multiplied by the first logical multiplier element 46d, and the second logical multiplier 46e The rising edge delayed by the rising edge delay unit 30 is multiplied by the output signal of the second NAND gate 46c. In addition, the logic sum element 46f performs an OR on the signals output from the first and second AND products 46d and 46d, respectively, and outputs the result as a timing signal Y1 for testing the device.

In other words, when the selection signal SEL output from the comparator 10 is the high signal H, that is, the magnitude of the falling edge of the timing signal is equal to the rising edge of the timing signal. If it is larger than the magnitude, the falling edge output from the falling edge delay unit 20 and the rising edge output from the rising edge delay unit 30 are ORed together to output the result as a controlled timing signal.

Further, when the selection signal SEL output from the comparator 10 is the low signal L, that is, when the rising edge of the timing signal is larger than the falling edge of the timing signal, the falling edge delay is delayed. The falling edge output from the unit 20 and the rising edge output from the rising edge delay unit 30 are ANDed to output the result as a controlled timing signal.

On the other hand, the third and fourth buffers 47 and 48 buffer the delay mask values T_MaskB and T_MaskA of the input timing signals, respectively, to adjust the timing signal levels for use in refreshing, reading, and writing the signals. The timing signal level adjusting unit 49 outputs a signal for adjusting the timing signal level based on a plurality of input signals. Accordingly, the third logical sum element 51 performs a logical sum of the signal output from the timing signal level controller 49 and the timing signal generated by the timing signal changer 46, and the exclusive logic sum element 52 The polarity of the timing signal generated by the exclusive OR of the signal output from the third logical sum element 51 and the timing signal polarity signal buffered in the first buffer 41 is adjusted. The polarity-adjusted timing signal is buffered by the fifth buffer 53 and output as a timing signal for testing the device.

In addition, since the timing signal buffered and output from the fifth buffer 53 is a timing signal precisely controlled to 150 ps, the timing signal can be used as a test timing signal even for a high-speed device.

As described above, the device test timing signal generator according to the present invention has the effect of generating a precise timing signal by controlling the falling edge and the rising edge of the timing signal.

In addition, precise timing signals controlled up to 150ps can be generated, which can be used as timing signals even when testing high-speed devices.

Claims (5)

Comparison means for comparing a magnitude of the falling edge of the timing signal generated with the reference and the magnitude of the rising edge of the timing signal and generating a selection signal for logically combining the falling edge and the rising edge according to the result; Falling edge delay means for delaying the falling edge of the timing signal by a predetermined time and outputting the delayed edge; Rising edge delay means for delaying and rising the rising edge of the timing signal by a predetermined time; And a timing signal control and generation means for selectively logically combining the falling edge and the rising edge generated by the falling edge / rising edge delay means according to the selection signal generated by the comparing means, and generating the result as a timing signal. A timing signal generator for testing a device, characterized in that configured. The high signal H as the selection signal according to claim 1, wherein the comparison means compares the magnitude of the falling edge of the timing signal with the magnitude of the rising edge of the timing signal. And outputting a low signal (L) as the selection signal when the rising edge is greater than the falling edge. 2. The apparatus of claim 1, wherein the timing signal control and generation means comprises: a first buffer for buffering the polarity of the timing signal, a first logical sum element for ORing the falling edge and the rising edge of the timing signal, and the falling of the timing signal; A logical AND element for ANDing an edge and a rising edge, a second buffer for buffering a level of an input timing signal, a second logical OR element for ORing the output signal and the paging signal PAGING of the second buffer, A timing signal changer configured to select one of the outputs of the first logical logic element and the logical multiplication element according to the output signal of the logical logic element, change the output signal to a predetermined level, and buffer the delay mask value of the input timing signal, respectively; A third and fourth buffers, a timing signal level controller which adjusts and outputs an output value of the second logical element according to the output values of the third and fourth buffers; Exclusively OR the third logical sum element that ORs the output signal of the ming signal level adjusting part and the output signal of the timing signal changer, and outputs the output signal of the third logic sum element and the timing signal polarity output from the first buffer, and the result value. And a fifth buffer configured to buffer and output a timing signal outputted from the exclusive logical sum device, and an exclusive logical sum device generated as a timing signal. 4. The apparatus of claim 1 or 3, wherein the timing signal changing unit comprises: an inverter for phase inverting a selection signal output from the comparison means, and an NAND ring of an enable signal output from the selection signal and the second logic element. A first logic to logically multiply a first NAND gate, a second NAND gate for NAND-ringing an output signal of the inverter and an enable signal output from the second logic element, and an output signal of the first NAND gate and a delayed falling edge. A logical multiplication of a product element, a second logical element multiplying the output signal of the second NAND gate and the delayed rising edge, and a signal output from each of the first and second logical multiplication elements is performed, and the result is a timing signal. A timing signal generator for testing a device, characterized in that it comprises an output logic logic element. By comparing the magnitudes of the falling edge and the rising edge of the reference timing signal, a high signal is generated when the size of the falling edge is larger than the size of the rising edge, and a low signal when the size of the rising edge is larger than the size of the falling edge. According to an output step, a falling / rising edge delay step of delaying the falling edge and the rising edge of the timing signal by a predetermined time and outputting the selected signal, the selection signal is generated according to the selection signal generated in the selection signal output step. A timing signal output step of ORing the falling edge and the rising edge generated in the falling edge / rising edge delay step if it is a high signal, and if the selection signal is a low signal, logically multiplying and outputting the result as a timing signal for testing the device; Timing signal generation method for a device test, characterized in that consisting of.

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