KR19990016022A - Microphase data correction device and method - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

Piel device in communication system.

I. The technical problem to be solved by the invention

Apparatus and method for correcting the phase difference of a PEL apparatus.

All. Summary of Solution of the Invention

The microphase difference correction processing apparatus includes one master PEL unit generating a clock signal for supplying the system by a clock signal applied from the outside, and a clock signal for supplying the system according to the clock signal applied from the master PEL unit. A phase detection unit for comparing the generated first and second slave PIEL units, the master PIEL unit and the first and second PIEL units, and outputting a comparison result; and the first and second slave PIELs according to the signals of the phase detection unit. And a phase control unit for outputting a phase control signal to the el unit.

la. Important uses of the invention

Apparatus and method for correcting small phase differences in a communication system.

Description

Microphase data correction device and method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital phase synchronizers and methods, and more particularly, to an apparatus and method for correcting microphase difference data in digital phase synchronizers.

In general, as communication networks are digitized, each hierarchy or exchange constituting the communication network synchronizes the entire communication network with one reference frequency to maximize the loss of data that may occur in the levels or exchanges constituting the communication network. What was needed was a way to reduce it. Therefore, the tripled Digital Processing Phase Locked Loop (DP-PLL) method was used. However, in the case of the triplexed digital FEL, the loop output clock is generated when the system noise is generated due to interference between the outputs of each FEL or when the clock supplied from the master FEL to the system is applied to the slave FEL. At the moment of changing the system, the normal duty ratio could not be maintained, which affected the whole exchange system.

Accordingly, an object of the present invention is to provide a device capable of correcting data by detecting a microphase difference when processing digital data.

In order to achieve the above object, the present invention provides a microphase difference data correction processing apparatus comprising: a master PIEL unit for generating a clock signal for supplying the system by a clock signal applied from the outside; and a clock applied from the master PIEL unit. A phase detection unit for comparing the signals of the first and second slave FELEL parts to generate a clock signal for supplying the system according to the signal, and outputting a comparison result by comparing the signals of the master FELEL part and the first and second FELEL parts; And a phase control unit for outputting phase control signals to the first and second slave PIEL units according to the signal of the phase detection unit.

Another object of the present invention is to provide a method capable of correcting data by detecting a microphase difference when processing digital data.

In order to achieve the above object, the present invention provides a method for processing a microphase difference data correction method, which includes checking whether a master Piel is selected and three Piel parts are in normal mode, and the phase control when the Piel part is in the normal mode. A process of checking whether the minimum time warns, a phase speed test process of checking a phase of the master PIEL part and the speeds of the phases of the two PIELs when the phase control minimum time warns, and the two PIELs A phase control signal for checking whether a result of a negative phase speed test is maintained for a set time; and if the two slave Piel parts are later than the phase of the master Piel part, a phase control signal for speeding up the phase speed to the two slave Piel parts Characterized in that it is made of a micro-phase difference data correction method characterized by outputting do.

1 is a block diagram of a tripled digital PLL device according to the present invention;

2 is a block diagram of a phase detector for detecting a microphase according to an embodiment of the present invention.

3 is a timing diagram according to the circuit of FIG.

4 is a control flowchart for correcting microphase difference data according to an embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a tripled digital PLL device according to the present invention.

The tripled digital PLL device is composed of one master Piel part 100 and two slave Piel parts 110 and 120. In this case, the master PEL part and the slave PEL part are not fixed, and each of the PEL parts 100, 110, and 120 may be the master PEL part according to the master selection signal. The master PEL unit 100 detects and outputs a phase difference between an external clock signal applied from the outside and a divided signal applied from the divider 105. Hereinafter, the phase difference signal, which the phase detection unit 101 detects and outputs the phase difference between the external clock signal and the signal applied from the divider 105, is called a phase detection signal. The phase detection signal of the phase detector 101 is input to the first processor 102, and the first processor 102 analyzes the input phase detection signal and outputs a control signal to the D / A converter 103. The digital-to-analog converter 103 modulates the digital signal into an analog signal according to the control signal received from the first processor 102 and outputs the digital signal to an OVCXO (Ovenized Voltage Controlled X-tal Oscillator) 104. . The oscillator 104 oscillates and outputs at a frequency for supplying the system, and feeds back a portion of the oscillation frequency to the frequency divider 105. The frequency divider 105 divides the frequency received from the oscillator and outputs the frequency to the phase detectors 111 and 121 of the phase detector 101 and the slave PLL circuits 110 and 120.

The phase detectors of the slave PEL parts 110 and 120 output signals of the frequency to be supplied to the system using the clock signal input from the divider 105 of the master PEL part 100 as an external clock signal.

2 is a block diagram illustrating a phase detector for detecting a microphase according to an embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to FIG. 2.

First, the clock signal output from the master PEL unit 100 of FIG. 1 is clock 0, the clock signal output from the slave PEL unit 110 is CLOCK 1, and the clock signal output from the slave PEL unit 120 is CLOCK 2. . The three clock signals are combined by two signals. First, the signals of CLOCK 0 and CLOCK 1 are input to the module _1, the module _2 inputs the CLOCK 0 and CLOCK 2, and the module _3 inputs the CLOCK 1 and CLOCK 2. Module_1, module_2 and module_3 are each composed of two de-flip flops.

The first flip-flop F / F1 of the module_1 connects the CLOCK 0 to the input terminal D1 and the CLOCK 1 to the clock applying terminal CK1, and the second flip-flop F / F2 connects the CLOCK 1 It is connected to the input terminal (D2) and the CLOCK 0 is connected to the clock clock terminal (CK2). The third flip-flop F / F3 of the module_2 connects CLOCK 0 to the input terminal D1, the CLOCK 2 to the clock applying terminal CK1, and the fourth flip-flop F / F4 connects the CLOCK 2 to The input terminal D2 is connected, and the CLOCK 0 is connected to the clock applying terminal CK2. The fifth flip-flop F / F5 of the module_3 connects CLICK 1 to the input terminal D1 and the clock 2 to the clock applying stage CK1, and the sixth flip-flop F / F6 inputs the CLOCK 2 to the input terminal. Connect to (D2) and the CLOCK 1 is connected to the clock applying stage (CK2). In addition, the outputs of the respective flip-flops F / F1 to F / F6 are input to the phase controller 150. The phase controller 150 inputs two outputs applied from the module_1 to Pa and Pa 'stages, inputs two outputs from the module_2 to Pb and Pb' stages, and outputs two outputs applied from the module_3. Input to Pc and Pc '. The phase controller 150 controls the output according to a master PLL select (MS) signal applied from the outside. Hereinafter, the master PLL part selection signal applied from the outside is called a master selection signal. The phase controller 150 applies a signal of each output terminal V _{O0 to} the PEL unit 100, a signal of V _{O1 to} the PEL unit 110, and a signal of V _{O2 to} the PEL unit 120. Table 1 shows the phase control signal output according to the master selection signal.

M.S signal Output phase control signal Phase control signal not output 100 V ₁ → 110 V ₂ → 120 V ₀ 110 V ₀ → 100 V ₂ → 120 V ₁ 120 V ₀ → 100 V ₁ → 110 V ₂

3 is a timing diagram according to the circuit of FIG. 2.

Hereinafter, the operation of the phase detection circuit will be described with reference to FIGS. 2 to 3.

Hereinafter, the module_1 will be described as an example. When the signals of CLOCK 0 and CLOCK 1 are input, the flip-flop F / F1 maintains a low level in step 10 and the flip-flop F / F2 maintains a high level in 20 steps. do. In addition, the second flip flop F / F2 transitions from the high level to the low level in step 30, and the first flip flop F / F1 transitions from the low level to the high level in step 40. The first flip-flop F / F1 of the module_1 maintains the same output from the 40th to the 50th stage, and then transitions to the low level again in the 50th stage. In addition, the second flip-flop F / F2 maintains a low level from 30 to 60 steps, and transitions to a high level at 60 steps. The same result can be obtained in modules _2 to _3.

Then, the speed of each clock signal according to the output is shown in Table 2 below.

module Q1 Q2 FAST SLOW Module_1 H L CLOCK 0 CLOCK 1 L H CLOCK 1 CLOCK 0 Module_2 H L CLOCK 0 CLOCK 2 L H CLOCK 2 CLOCK 0 Module_3 H L CLOCK 1 CLOCK 2 L H CLOCK 2 CLOCK 1

Hereinafter, Table 2 is referred to as a phase comparison table, and a signal output from each module is referred to as a phase comparison signal.

The phase controller 150 inspects the output of each module by using the phase comparison table and outputs a frequency control signal to the microprocessors of each PEL board according to the inspection result.

4 is a control flowchart of correcting microphase difference data according to an embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to FIGS. 1 to 4.

The phase controller 150 checks whether the master PLL unit is selected in step 200. The phase controller 150 proceeds to step 202 when the master PLL unit is selected as a result of the test and ends when the master PLL unit is not selected. In step 202, the phase controller 150 checks whether the PLL board is in a normal state. In this case, the steady state refers to checking whether the PLL board has passed the transient phenomenon in the initial state. The phase controller 150 proceeds to step 204 in the normal mode as a result of the inspection and ends in the normal mode. The phase controller 150 checks whether the minimum phase control time has elapsed in step 204. In this case, the elapse of the phase control minimum time refers to a minimum setting time for the PLL board to operate normally. The phase controller 150 proceeds to step 206 when the minimum phase control time has elapsed, and proceeds to step 218 when the minimum phase control time has elapsed, and increases and terminates the time counter TCNT. In the following description, it is assumed that the master PLL unit is denoted by reference numeral 100 of FIG. 1. In step 206, the phase controller 150 determines whether the phase of the master PLL and the phase of the slave PLL are the same. The phase controller 150 ends when the phase of the master PLL 100 and the phases of the slaves 110 and 120 are the same as the result of the test, and proceeds to step 206 when the phases of the phase controller 150 are not the same.

Here, the process of checking whether the phases are the same may be checked when the state of the phase comparison table of Table 2 is maintained as one state for a predetermined time or more. However, if such a test takes a long time, step 206 may be omitted. In step 208, the phase controller 150 compares the signals applied to the Pa and Pa 'stages with the Pb and Pb stages and checks whether a clock signal of the master PLL is faster than a signal of each slave PLL. If the clock signal of the slave board is fast, the process proceeds to step 214. If the signal of the slave board is slow, the process proceeds to step 210. As an example, when the slave board 110 is slow and the slave board 120 is fast as a result of the phase comparison table shown in Table 2, the phase control signal is different from each slave board according to the master selection signal of Table 1. Will print Here, the phase control signal refers to a signal for controlling the frequency of the clock supplied to the system from the phase controller 150 to each slave PLL. Therefore, if the phase controller 150 maintains the same state for a predetermined time in step 210, the phase controller 150 proceeds to step 212 and outputs an analog to an analog conversion word (DACW) value of a clock signal output from the slave PLL and supplied to the system. A phase control signal for reducing is output. On the other hand, if the same state is maintained for the set time in step 214, the opposite signal of step 212 is output to the slave PLL. The phase control signal of steps 212 and 216 is output, and the phase controller 150 proceeds to step 206.

As described above, the phase difference can be corrected by comparing the signal output from the master PLL with the signal output from the slave PLL so as to continuously correct the phase.

Claims (8)

In the micro-phase difference data correction device, A master PEL part generating a clock signal for supplying the system by a clock signal applied from the outside; First and second slave PIEL parts for generating a clock signal for supplying the system according to the clock signal applied from the master PI EL part; A phase detection unit for comparing the signals of the master PIEL unit and the first and second PIEL units and outputting a comparison result; And a phase control unit for outputting a phase control signal to the first and second slave PEL parts according to the signal of the phase detection unit. The method of claim 1, wherein the phase detection unit, A first module for inspecting a speed of a clock signal applied from the master PEL unit and a clock signal applied from the first slave PEL unit and outputting the speed to a phase controller; A second module for inspecting a speed of a clock signal applied from the master PEL unit and a clock signal applied from the second slave PEL unit and outputting the speed to the phase controller; And a third module which checks the speeds of the clock signals applied from the first slave PIEL unit and the clock signals applied from the second slave PIEL and outputs them to the phase controller. The method of claim 2, The phase controller determines a master PIEL unit and a slave PIEL unit of each of the PLEL units according to a master selection signal, And outputting a phase control signal to the determined slave PLL unit. The method of claim 2, wherein the first, second and third modules, It consists of two de flip flops In the first module, the clock signal applied from the master PEL part is applied to the input terminal of the first flip flop and the clock applying end of the second flip flop, and the clock signal applied from the first slave FEL part is the clock of the first flip flop. Is applied to the input terminal of the application stage and the second flip-flop, In the second module, the clock signal applied from the master PEL part is applied to the input terminal of the third flip flop and the clock applying end of the fourth flip flop, and the clock signal applied from the second slave PEL part is the clock of the third flip flop. Is applied to the input terminal of the applying stage and the fourth flip-flop, In the third module, the clock signal applied from the first slave PLEL unit is applied to the input terminal of the fifth flip flop and the clock application terminal of the sixth flip flop, and the clock signal applied from the second slave PLEL is the fifth flip flop. Apparatus for correcting the micro-phase difference, characterized in that applied to the clock application stage and the input terminal of the sixth flip-flop. In the small phase difference data correction method, The process of checking whether master PIEL is selected and three PIEL parts are in normal mode, Checking whether the phase control minimum time warns when the PEL part is in the normal mode as a result of the inspection; A phase velocity inspection process for inspecting the phases of the master PIEL part and the velocity of the phases of the two PIELs when the phase control minimum time warns; Checking whether the phase velocity test results of the two PEL parts are maintained for a set time; And outputting a phase control signal for increasing the phase speed to the two slave PEL parts when the two slave PEL parts are later than the phase of the master PEL part. The method of claim 5, A process of checking whether the state is maintained for a set time when the speed of one slave PIEL part is faster than the speed of the master PIEL part and the speed of one slave PIEL part is slower than the speed of the master PIEL part as a result of the phase speed test. and, Outputting a phase control signal for speeding up the phase speed to the PEL part having a low phase speed, and outputting a phase control signal for slowing the phase speed to the PEL part with a high phase speed if the test result is maintained for a predetermined time. Microphase difference data correction method characterized in that it comprises. The method of claim 6, Checking whether the state is maintained for a set time when the phase velocity test results show that the phases of the two slave PELs are faster than the phase phases of the master PEL part; And outputting a phase control signal for slowing the phase velocity to the two slave PEL parts when the two slave PEL parts are faster than the phase of the master PEL part. . The method of claim 5, And checking whether the phases of the master PEL part and the slave PEL part are identical to each other.