KR19990013066A - Semiconductor device with crystal oscillator - Google Patents

Abstract

The semiconductor device of the present invention comprises a crystal oscillator connected between the first and second clock pins, for obtaining an oscillation signal having a predetermined frequency range; A drive circuit connected between the first and second clock pins and for driving the oscillation signal; The drive circuit consists of at least two drivers, each of which is selectively activated by corresponding activation signals.

Description

Semiconductor device with crystal oscillator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a crystal oscillator for obtaining an oscillation signal having a predetermined frequency range.

On-chip oscillators (ON-CHIP oscillator) has a smaller number of parts and simpler structure than the oscillator mounted on the outside of the semiconductor chip, and its use is increasing. Recently, a crystal oscillator which uses a stable oscillator is mainly used. In order to reduce the price in CMOS ICs, crystal oscillators using a resonator element and a plurality of passive elements are widely used. The advantage of the crystal oscillator is that the temperature and voltage, and the frequency dependence on the process are very low, and the circuit configuration for oscillation is very easy. If a chip is made and then one oscillator is used to cover several frequency bands, it is designed for the highest frequency.

1 is a block diagram showing a configuration of a semiconductor device having a crystal oscillator according to the prior art.

Referring to FIG. 1, the oscillator has a crystal oscillator (X-tal) connected between clock pins (X0) and (X1), one input terminal is connected to the clock pin (X0), and an activation signal (E) is input to the other input terminal. ) Is inputted to the NOR gate G1 and the buffer circuit 10 connected to the output terminal of the NOR gate G1. Here, the clock pin X1 is connected to the output terminal of the NOR gate G1, and the NOR gate G1 operates as a driver.

One of the most power consuming parts of most semiconductor chips is the oscillator part. This is because the driving portion of the oscillator does not make a full swing logically from a low level to a logically high level. In general, since the frequency band is not subdivided in the used oscillator, the size of the driver becomes larger than necessary when using an oscillator suitable for a desired frequency, and power consumption increases accordingly.

For example, assume that the oscillator of FIG. 1 is designed such that the frequency band can be used from 10MHZ to 40MHZ. In this case, if the oscillator is desired to be used at about 20 MHZ, the result is an unnecessary large driver G1, resulting in increased power consumption.

It is therefore an object of the present invention to provide a semiconductor device having an oscillator with low power consumption.

1 is a block diagram showing a configuration of a semiconductor device having an oscillator according to the prior art;

2 is a block diagram showing a configuration of a semiconductor device having an oscillator according to the present invention;

3 is a circuit diagram showing a circuit of a driver according to a preferred embodiment of the present invention;

* Explanation of symbols on the main parts of the drawings

10: buffer circuit 100: drive circuit

According to one aspect of the present invention for achieving the above object, in a semiconductor device having first and second clock pins, connected between the first and second clock pins, a predetermined frequency range is provided. A crystal oscillator for obtaining an oscillation signal having; Connected between the first and second clock pins and including means for driving the oscillation signal; The driving means is characterized in that it comprises at least two drivers, each of which is selectively activated by corresponding activation signals.

In the present embodiment, the remaining drivers except the selected ones of the drivers are deactivated in the floating state by the corresponding activation signal.

In this embodiment, the drivers are connected in parallel between the first and second clock pins.

In this embodiment, the semiconductor device is further connected in series with the drivers, characterized in that it further comprises a buffer means for amplifying the oscillation signal output through a selected one of the drivers.

In this embodiment, each of the drivers comprises: a power supply terminal to which a power supply voltage is applied; A ground terminal to which a ground potential is applied; An input terminal to which the activation signal is applied; An inverter for inverting the phase of the activation signal; Pull-up and pull-down transistors having drain, source and gate; Current paths of the pull-up and pull-down transistors are formed between the power supply terminal and the ground terminal; A first switching transistor having a current path formed between the power supply terminal and a gate of the pull-up transistor and a gate connected to the input terminal; A second switching transistor having a current path formed between the gate of the pull-down transistor and the ground terminal and a gate connected to the input terminal through the inverter; A first transfer gate having a first control terminal controlled to the activation signal and a second control terminal controlled to the activation signal applied through the inverter; A second transfer gate having a first control terminal controlled to said activation signal and a second control terminal controlled to said activation signal applied through said inverter; Gates of the pull up and pull down transistors are interconnected through the first and second transfer gates.

In this embodiment, the pull-up transistor and the first switch transistor are characterized in that it comprises PMOS transistors.

In this embodiment, the pull down transistor and the second switch transistor include NMOS transistors.

According to another aspect of the present invention, there is provided a crystal oscillator for obtaining an oscillation signal having a predetermined frequency range; Connected between the crystal oscillators and including means for driving the oscillation signal; The drive means comprise at least two drivers, each of which is selectively activated by corresponding activation signals.

In this embodiment, the remaining drivers except the selected ones of the drivers are deactivated to the floating state by the corresponding activation signal.

In this embodiment, the drivers are connected in parallel between the crystal oscillators.

In this embodiment, each of the drivers comprises: a power supply terminal to which a power supply voltage is applied; A ground terminal to which a ground potential is applied; An input terminal to which the activation signal is applied; An inverter for inverting the phase of the activation signal; Pull-up and pull-down transistors having drain, source and gate; Current paths of the pull-up and pull-down transistors are formed between the power supply terminal and the ground terminal; A first switching transistor having a current path formed between the power supply terminal and a gate of the pull-up transistor and a gate connected to the input terminal; A second switching transistor having a current path formed between the gate of the pull-down transistor and the ground terminal and a gate connected to the input terminal through the inverter; A first transfer gate having a first control terminal controlled to the activation signal and a second control terminal controlled to the activation signal applied through the inverter; A second transfer gate having a first control terminal controlled to said activation signal and a second control terminal controlled to said activation signal applied through said inverter; Gates of the pull up and pull down transistors are interconnected through the first and second transfer gates.

In this embodiment, the pull-up transistor and the first switch transistor include PMOS transistors.

In this embodiment, the pull down transistor and the second switch transistor include NMOS transistors.

By such an apparatus, only the driver corresponding to the desired frequency among the drivers having different driving capacities can be driven and the remaining drivers can be kept in a floating state.

Reference drawings according to embodiments of the present invention will be described in detail with reference to FIGS.

Referring to FIG. 2, a novel semiconductor device of the present invention is connected in parallel between clock pins (X0) and (X1), and a plurality of drivers controlled by activation signals (E1) and (E2), which are selectively activated. Oscillators having (DRV1) to (DRV2). Thus, in order to obtain the oscillation signal OSC having the frequency of 20 MHZ by using the oscillator which generates the oscillation signal OSC having the predetermined frequency band (for example, 20 MHZ to 40 MHZ), the drivers DRV1 It is possible to reduce the power consumed by the remaining drivers by activating only the corresponding ones of RV-DRV2.

2 is a block diagram showing a configuration of a semiconductor device according to the present invention.

2, a semiconductor device having an oscillator according to the present invention includes a driving circuit 100 connected between clock pins X0 and X1 and a buffer circuit 10 connected to the driving circuit. . The driving circuit 100 is constituted by at least two drivers DRV1 to DRV2 connected in parallel, and each of the drivers DRV1 to DRV2 corresponds to corresponding activation signals E1 and E2. It is selectively activated by) and is for driving the oscillation signal OSC having a predetermined frequency band generated from the crystal oscillator X-tal. Here, the remaining drivers (eg, DRV2) except for the selected ones (eg, DRV1) among the drivers DRV1 to DRV2 are in a floating state so as not to affect the operation of the selected driver DRV1. maintain.

As such, a circuit diagram showing a circuit of a driver according to a preferred embodiment of the present invention for maintaining an unselected driver in a floating state is shown in FIG. 3. It is apparent that the circuit of the driver shown in FIG. 3 shows only one of the drivers of FIG. 2 and the other drivers are also configured with the same circuit.

Referring to Fig. 3, the driver of the oscillator according to the present invention is one inverter IV1, two transfer gates T1 and T2, two PMOS transistors M1 and M3 and two NMOS. It consists of transistors M2 and M3. The current paths of the transistors M3 and M4 are formed between the power supply voltage and the ground potential. The transistor M1 has a current path formed between the power supply voltage and the gate of the transistor M3 and a gate connected to the input terminal 1 to which an activation signal E is applied.

The transistor M2 has a current path formed between the gate of the transistor M4 and the ground potential and a gate connected to the input terminal 1 through the inverter IV1. The transfer gate T1 has a first control terminal controlled to the activation signal E and a second control terminal controlled to the activation signal E applied through the inverter IV1. The second transfer gate T2 has a first control terminal controlled to the activation signal E and a second control terminal controlled to the activation signal E applied through the inverter IV1. In addition, the gates of the transistors M3 and M4 are interconnected through the first and second transfer gates T1 and T2.

As such, the driving circuit 100 of the oscillator is divided into a plurality of drivers DRV1 to DRV2 connected in parallel so that each is selectively activated by corresponding activation signals E1 and E2. Only the necessary drivers can be activated for the frequency band that the user wants to use. This not only enables one oscillator to support the granular frequency band, but also reduces the power consumption by keeping the unused drivers in a floating state.

As described above, the power consumed by the oscillator can be reduced by activating only the driver corresponding to the required frequency band.

Claims (13)

A semiconductor device having first and second clock pins, the semiconductor device comprising: A crystal oscillator connected between the first and second clock pins, for obtaining an oscillation signal having a predetermined frequency range; Connected between the first and second clock pins and including means for driving the oscillation signal; And said driving means comprises at least two drivers, each of which is selectively activated by corresponding activation signals. The method of claim 1, And the other drivers except the selected ones of the drivers are deactivated in a floating state by a corresponding activation signal. The method of claim 1, And said drivers are connected in parallel between said first and second clock pins. The method of claim 1, And said semiconductor device further comprises buffer means for amplifying said oscillation signal, which is connected in series with said drivers, and which is output through a selected one of said drivers. The method of claim 1, Each of the drivers, A power supply terminal to which a power supply voltage is applied; A ground terminal to which a ground potential is applied; An input terminal to which the activation signal is applied; An inverter for inverting the phase of the activation signal; Pull-up and pull-down transistors having drain, source and gate; Current paths of the pull-up and pull-down transistors are formed between the power supply terminal and the ground terminal; A first switching transistor having a current path formed between the power supply terminal and a gate of the pull-up transistor and a gate connected to the input terminal; A second switching transistor having a current path formed between the gate of the pull-down transistor and the ground terminal and a gate connected to the input terminal through the inverter; A first transfer gate having a first control terminal controlled to the activation signal and a second control terminal controlled to the activation signal applied through the inverter; A second transfer gate having a first control terminal controlled to said activation signal and a second control terminal controlled to said activation signal applied through said inverter; And the gates of the pull up and pull down transistors are interconnected through the first and second transfer gates. The method of claim 5, And the pull-up transistor and the first switch transistor comprise PMOS transistors. The method of claim 5, And the pull down transistor and the second switch transistor comprise NMOS transistors. A crystal oscillator for obtaining an oscillation signal having a predetermined frequency range; Connected between the crystal oscillators and including means for driving the oscillation signal; Said driving means comprising at least two drivers, each of which is selectively activated by corresponding activation signals. The method of claim 8, An oscillator circuit in which the remaining drivers except the selected one of the drivers are deactivated to a floating state by a corresponding activation signal. The method of claim 8, The drivers are connected in parallel between the crystal oscillator. The method of claim 8, Each of the drivers, A power supply terminal to which a power supply voltage is applied; A ground terminal to which a ground potential is applied; An input terminal to which the activation signal is applied; An inverter for inverting the phase of the activation signal; Pull-up and pull-down transistors having drain, source and gate; Current paths of the pull-up and pull-down transistors are formed between the power supply terminal and the ground terminal; A first switching transistor having a current path formed between the power supply terminal and a gate of the pull-up transistor and a gate connected to the input terminal; A second switching transistor having a current path formed between the gate of the pull-down transistor and the ground terminal and a gate connected to the input terminal through the inverter; A first transfer gate having a first control terminal controlled to the activation signal and a second control terminal controlled to the activation signal applied through the inverter; A second transfer gate having a first control terminal controlled to said activation signal and a second control terminal controlled to said activation signal applied through said inverter; The oscillation circuit of the pull up and pull down transistors is interconnected through the first and second transfer gates. The method of claim 11, The pull-up transistor and the first switch transistor include PMOS transistors. The method of claim 11, The pull down transistor and the second switch transistor comprise NMOS transistors.