KR19990011893A - Isolation Area Formation Method - Google Patents

Abstract

The present invention relates to a method for forming an isolation region, and more particularly, to an isolation region formation method in which a trench of an STI structure can be filled without a void by using a general oxide film. The isolation region forming method may include sequentially forming first and second insulating layers on a semiconductor substrate, etching the second and first insulating layers and the semiconductor substrate in a predetermined depth to form a trench, and forming a trench in the trench. Forming sidewall spacers on side surfaces of the second and first insulating films and the semiconductor substrate; forming a third insulating film on the entire surface of the semiconductor substrate including the trench; and planarizing the three insulating films to form an upper surface of the second insulating film. Exposing the light and selectively removing the second insulating film.

Description

Isolation Area Formation Method

The present invention relates to a method for forming an isolation region, and more particularly, to a method for forming an isolation region in which a trench of an STI structure can be filled without a void using a general oxide film.

As semiconductor devices are increasingly integrated, methods of reducing the size of a device isolation region and a device formation region, that is, an active region, have been proposed. A LOCOS (LOCal Oxidation of Silicon) process was used as a technique for forming a device isolation region. The isolation region forming process using the LOCOS process has been widely used because of its advantages that the process is simple and excellent in reproducibility. However, as the device is increasingly integrated, the area of the active region is reduced due to the occurrence of bird beaks in the edge of the isolation oxide that extends into the active region, which is a characteristic of the isolation oxide formed by the LOCOS process. It is not suitable for use in DRAMs of more than 64MB. Therefore, in the conventional method of forming an isolation region using LOCOS, an advanced LOCOS process is proposed such as preventing the formation of bud beak or removing the bud beak to reduce the isolation region and increase the active region. Or in the manufacturing process of 256MB DRAM. However, in the process of forming the isolation region using the advanced advanced process, the area of the isolation region is large in the GIGA class or more DRAM which requires the area of the cell region to be 0.2 μm ² or less and the field oxide film formed by the LOCOS process. As the silicon substrate is formed at the interface with the silicon substrate, the concentration of the silicon substrate is lowered due to the combination with the field oxide film, and as a result, a leakage current is generated, resulting in poor isolation characteristics. As a method of forming an isolation region, a method of forming an isolation region using a trench which can easily control the thickness of the isolation region and increase the isolation effect has been proposed.

This conventional isolation region formation method will be described with reference to the accompanying drawings.

1A to 1F are cross-sectional views of a conventional isolation region forming process.

First, as shown in FIG. 1A, an oxide film 2 is formed on a semiconductor substrate 1.

As shown in FIG. 1B, a nitride film 3 is formed on the oxide film 2.

As shown in Fig. 1C, the isolation region is defined to selectively pattern the nitride film 3 and the oxide film 2 in the isolation region (photolithography process + etching process). Subsequently, the semiconductor substrate 1 is etched to a certain depth to form a trench 4.

As shown in FIG. 1D, an oxide isolation film 5 for isolation of the device is deposited on the entire surface of the semiconductor substrate 1 including the trench 4. At this time, due to the step coverage of the trench 4, the trench 4 is not completely filled and the void 6 is formed. The higher the integration of the semiconductor device, the higher the probability of occurrence of such voids 6. As the aspect ratio (ASPECT RATIO) of the trench 4 increases, the isolation layer 5 is not completely filled in the trench 4. The likelihood of generating VOID is increasing. In particular, such a problem is more serious when the inclination of the trench 4 is formed steeply.

As shown in FIG. 1E, the device isolation oxide film 5 and the nitride film 3 are polished by using chemical mechanical polishing (CMP), and the device isolation oxide film 5 is formed in the trench (CMP). 4) It is formed in the isolation film 5a, and the nitride film 3 is also polished so that only a predetermined thickness remains.

As shown in Fig. 1F, the nitride film 3 is completely removed.

As semiconductor devices are highly integrated in the conventional isolation region formation method, the aspect ratio of the trench is high and the slope of the trench is steep, so that the occurrence of voids during the process of forming the isolation layer by filling the oxide film in the trench increases the reliability of the isolation layer. There was a problem letting.

The present invention has been made to solve the problems of the conventional method for forming an isolation region as described above, so that the isolation layer is formed after forming sidewall spacers in the trench to form the isolation layer, thereby providing an isolation region formation method capable of filling the trench without voids. Its purpose is to.

1A to 1F are cross-sectional views of a conventional isolation region forming process.

Figure 2a to 2h is a cross-sectional view of the isolation region forming process of the present invention

Explanation of symbols for main parts of the drawings

11 semiconductor substrate 12 first insulating film

13 second insulating film 14 trench

15a: sidewall spacer 16a: separator

In the method of forming an isolation region according to the present invention, the steps of sequentially forming a first and a second insulating film on a semiconductor substrate, forming a trench by etching a predetermined depth of the second, first insulating film and the semiconductor substrate of the isolation region, Forming sidewall spacers on side surfaces of the second and first insulating films and the semiconductor substrate in the trench; forming a third insulating film on the entire surface of the semiconductor substrate including the trench; planarizing the third insulating film to Exposing an upper side, and selectively removing the second insulating film.

Such a method for forming an isolation region of the present invention will be described with reference to the accompanying drawings.

2A to 2H are cross-sectional views of the isolation region forming process of the present invention.

First, as shown in FIG. 2A, the first insulating film 12 is formed on the semiconductor substrate 11. At this time, an oxide film is formed.

As shown in FIG. 2B, a second insulating film 13 is formed on the first insulating film 12. In this case, the second insulating layer 13 is formed of a material having a different etching selectivity from the first insulating layer 12, and preferably formed of a nitride layer.

As shown in FIG. 2C, the isolation region is defined to selectively pattern the second insulating film 13 and the first insulating film 12 in the isolation region (photolithography process + etching process). Subsequently, the semiconductor substrate 11 in the isolation region is etched to a predetermined depth to form a trench 14. In this case, the isolation region is a region for forming an isolation layer for isolation between semiconductor devices.

As shown in FIG. 2D, a third insulating film 15 is formed along the surface of the semiconductor substrate 11 and the surfaces of the first and second insulating films 12 and 13 in the trench 14. In this case, the third insulating layer 15 is formed of one of an oxide and a nitride by using a low pressure chemical vapor deposition (LPCVD) method, and when formed of an oxide, high temperature low pressure dielectric (HLD) Form into a film. It may also be formed of a USG (Undoped Silicate Glass) film. Before the third insulating film 15 is formed on the entire surface including the trench 14, the surface of the semiconductor substrate 11 in the trench 14 is oxidized and deposited (not shown). The reason for this is to recover the etching damage of the semiconductor substrate 11 generated during the etching process for forming the trench 14 and to suppress the occurrence of leakage current.

As shown in FIG. 2E, the sidewall spacers 15a are etched back on the sidewalls of the second and first insulating layers 13 and 12 and the semiconductor substrate 11 in the trench 14. ). In this case, in order to prevent the etch damage of the semiconductor substrate 11, during the etch back process of the sidewall spacer 15a, the semiconductor substrate 11 under the trench 14 may be under etched so as not to be exposed. . At this time, it can be seen that the inclination of the trench 14 is gentle due to the formation of the sidewall spacers 15a as described above.

As shown in FIG. 2F, a fourth insulating film 16 is formed on the entire surface of the second insulating film 13 including the trench 14 and the sidewall spacers 15a.

As shown in FIG. 2G, the fourth insulating film 16 and the second insulating film 13 are polished by chemical mechanical mirror polishing to form the insulating film 16a in the trench 14. In addition, the second insulating layer 13 leaves only a predetermined thickness.

As shown in Fig. 2H, the second insulating film 13 is completely removed.

In the method for forming an isolation region according to the present invention, an insulating film having a sidewall spacer shape is formed in the trench of the STI structure so that the inclination in the trench is smoothed. There is an effect that can provide a method for forming an isolation region.

Claims (2)

Sequentially forming first and second insulating films on the semiconductor substrate; Etching the second and first insulating layers and the semiconductor substrate in the isolation region to form a trench; Forming sidewall spacers on side surfaces of the second and first insulating films and the semiconductor substrate in the trench; Forming a third insulating film on the entire surface of the semiconductor substrate including the trench; Planarizing the third insulating film to expose an upper surface of the second insulating film; And selectively removing the second insulating film. The method of claim 1, wherein the sidewall spacer is formed of one of an oxide and a nitride.