KR19990006072A - Manufacturing method of MOS field effect transistor - Google Patents
Manufacturing method of MOS field effect transistor Download PDFInfo
- Publication number
- KR19990006072A KR19990006072A KR1019970030294A KR19970030294A KR19990006072A KR 19990006072 A KR19990006072 A KR 19990006072A KR 1019970030294 A KR1019970030294 A KR 1019970030294A KR 19970030294 A KR19970030294 A KR 19970030294A KR 19990006072 A KR19990006072 A KR 19990006072A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- film
- oxide film
- planarization
- pattern
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title description 12
- 230000005669 field effect Effects 0.000 title description 2
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 14
- 150000004767 nitrides Chemical class 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 238000002955 isolation Methods 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 230000001133 acceleration Effects 0.000 abstract description 3
- 230000005684 electric field Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- -1 Boro Phosphor Chemical compound 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical group 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
본 발명은 MOS FET 의 제조방법에 관한 것으로서, 트랜치를 형성하고, 트랜치 상하의 노출된 반도체기판에 걸쳐지는 경사면을 채널로 이용하여 드레인에 인가되는 바이어스와 빌트인 필드의 합력을 감소시키고, 전하의 계속적인 가속도 방지하며, 경사면의 각도, 경사면 상하 부분의 길이 단차의 높이 등을 조절하여 MOS FET의 특성을 조절하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a MOS FET, in which a trench is formed, the slope of the exposed semiconductor substrate above and below the trench is used as a channel to reduce the force of the bias and the built-in field applied to the drain, and the charge is continuously Acceleration is also prevented, and the characteristics of the MOS FET are controlled by adjusting the angle of the inclined surface, the height of the length step of the upper and lower portions of the inclined surface, and the like, thereby improving process yield and reliability of device operation.
Description
본 발명은 모스 전계효과 트랜지스터(Metal Oxide Semi conductor Field Effect Transistor; 이하 MOS FET라 칭함)의 제조방법에 관한 것으로서, 특히 기판에 형성된 단차에 의해 좁은 면적에서 채널길이가 증가된 MOS FET 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a metal oxide semi-conductor field effect transistor (hereinafter referred to as a MOS FET), and more particularly to a method of manufacturing a MOS FET in which a channel length is increased in a small area by a step formed in a substrate. will be.
반도체소자가 고집적화되어 감에 따라 MOS FET의 게이트 전극도 폭이 줄어들고 있으나, 게이트전극의 폭이 N배 줄어들면 게이트전극의 전기 저항이 N배 증가되어 반도체소자의 동작 속도를 떨어뜨리는 문제점이 있다. 따라서 게이트 전극의 저항을 감소시키기 위하여 가장 안정적인 MOS FET 특성을 나타내는 폴리실리콘층/산화막 계면의 특성을 이용하여 폴리실리콘층과 실리사이드의 적층 구조인 폴리사이드를 저저항 게이트로 사용하기도 한다.As the semiconductor devices become more integrated, the gate electrodes of the MOS FETs also decrease in width, but when the width of the gate electrodes decreases by N times, the electrical resistance of the gate electrodes increases by N times, which reduces the operating speed of the semiconductor devices. Therefore, in order to reduce the resistance of the gate electrode, the polysilicon, which is a laminated structure of the polysilicon layer and the silicide, may be used as a low resistance gate by using the polysilicon layer / oxide layer interface property that exhibits the most stable MOS FET characteristics.
일반적으로 p 또는 n 형 반도체기판에 n 또는 p형 불순물로 형성되는 pn접합은 불순물을 반도체기판에 이온주입한 후, 열처리로 활성화시켜 확산영역을 형성한다. 따라서 채널의 폭이 감소된 반도체소자에서는 확산영역으로부터의 측면 확산에 의한 숏채널 효과(short channel effect)를 방지하기 위하여 접합깊이를 얕게 형성하여야 하며, 드레인으로의 전계 집중에 의한 접합 파괴를 방지하게 위하여 소오스/드레인 영역을 저농도 불순물 영역을 갖는 LDD 구조로 형성하는 등의 방법이 있다.In general, a pn junction formed of n or p type impurities on a p or n type semiconductor substrate is ion implanted into the semiconductor substrate and then activated by heat treatment to form a diffusion region. Therefore, in a semiconductor device having a reduced channel width, the junction depth should be shallow to prevent short channel effects due to side diffusion from the diffusion region, and to prevent junction breakage due to electric field concentration to the drain. For this purpose, there are methods such as forming a source / drain region into an LDD structure having a low concentration impurity region.
도 1 및 도 2 는 종래 기술에 따른 MOS FET를 설명하기 위한 도면들로서, 서로 연관시켜 설명한다.1 and 2 are diagrams for explaining a MOS FET according to the prior art, which will be described in association with each other.
도 1에 도시되어 있는 바와 같이, 반도체기판(10)상에 게이트산화막(12)과 게이트전극(14), 절연막 스페이서(16) 및 소오스/드레인 영역(18)이 형성되어 있는데, 도 2에 도시되어 있는 바와 같이, 게이트 및 드레인에 전압이 인가되면, 바이어스에 의한 필드와 빌트인 필드가 같은 방향으로 인가되어 드레인 앞부분에서 열전하가 생성된다.As shown in FIG. 1, a gate oxide film 12, a gate electrode 14, an insulating film spacer 16, and a source / drain region 18 are formed on the semiconductor substrate 10. As can be seen, when a voltage is applied to the gate and the drain, the field due to the bias and the built-in field are applied in the same direction to generate heat charge in front of the drain.
즉 소오스로 부터 채널을 타고 가속되던 전하가 드레인 앞부분의 강력한 전기장 인가 지역에서 실리콘 본드를 파괴할 정도의 큰 에너지를 가지게 되어 격자와 충돌해 전자-정공쌍을 형성하고, 형성된 전자-정공쌍중 Si/SiO2계면의 에너지 장벽을 통과할 정도의 큰 에너지를 갖는 것들이 게이트 산화막으로 침투하여 산화막내에 트랩된다. 이러한 상태가 누적되면 게이트 산화막내에 상당한 량의 전하를 갖는 층이 형성되고, 이층에서 발생하는 전기장에 의해 트랜지스터의 고유 특성인 문턱전압(Vt)이 변화되고, 그외의 다른 제반 특성들도 변화되어 소자의 오동작을 유발한다.In other words, the charge accelerated through the channel from the source has a large enough energy to destroy the silicon bond in the strong electric field applied area in front of the drain, colliding with the lattice to form an electron-hole pair, and forming a Si-hole pair in Si. Those with a large energy enough to cross the energy barrier at the / SiO 2 interface penetrate into the gate oxide film and are trapped in the oxide film. When such a state accumulates, a layer having a considerable amount of charge is formed in the gate oxide film, and the electric field generated in the second layer changes the threshold voltage (Vt), which is inherent in the transistor, and other various properties. Cause malfunction.
여기서 서브마이크론 크기의 MOS FET 제조시에는 열전하 축퇴(hot carrier degradation) 가 매우 심각한 문제가 되는데, 이는 드레인 앞부분의 고전계지역에서의 열전하의 생성에 기인한 게이트산화막내 전하(charge)의 트랩에 의한 불량발생을 방지하기 위하여 첫째, 게이트산화막 제조시 Si/SiO2의 계면에 트랩 생성을 최소로 하는 방법인데, 이는 실리콘 웨이퍼 자체의 질적인 문제와 장비의 한계로 인해 개선이 어렵다.In the manufacture of submicron-sized MOS FETs, hot carrier degradation becomes a very serious problem, which is caused by trapping of charge in the gate oxide due to the generation of heat charge in the high field region in front of the drain. In order to prevent the occurrence of defects caused by the first, the method of minimizing trap generation at the interface of Si / SiO 2 during the gate oxide film manufacturing, which is difficult to improve due to the quality problems of the silicon wafer itself and equipment limitations.
두번째 방법으로는 드레인 형성시 드레인 접합에 유도되는 비트인 필드를 약화시키기 위해 다단계 이온주입을 실시하는 방법으로서, 엘.디.디(lightly doped drain; 이하 LDD라 칭함)구조가 대표적인 예인데, 이 또한 장비의 한계로 인하여 더 이상의 향상이 어려운 문제점이 있다.In the second method, a multi-stage ion implantation is performed to weaken the bit-in field induced at the drain junction when the drain is formed. A typical example is the lightly doped drain (LDD) structure. In addition, there is a problem that further improvement is difficult due to the limitation of the equipment.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 상기의 여러가지 시도에도 불구하고, 열전하 축퇴의 문제가 계속적으로 제기되고 있는 근본적인 원인은 소오스와 드레인간의 직선 구조에서 기인하는데, 소자가 미세화되면서 더욱 소오스와 드레인간의 거리가 감소되어 채널에 인가되는 전기장이 급격하게 증가되고, 소오스로부터 가속된 전자가 그대로 드레인 앞의 고전계 지역에 주입되는 것이 원인이라는 점에 착안하여 채널을 단차가 지게 형성하여 채널에 인가되는 전기장의 세기 및 방향 그리고 게이트 산화막의 정전용량을 조절하여 소자의 동작 특성을 향상시킬 수 있는 MOS FET의 제조방법을 제공함에 있다.The present invention is to solve the above problems, the object of the present invention despite the various attempts of the above, the root cause of the continuous problem of heat charge degeneration is due to the linear structure between the source and drain, As the device becomes smaller, the distance between the source and the drain is further reduced, and the electric field applied to the channel is drastically increased, and the channel is stepped in consideration of the fact that the electrons accelerated from the source are injected into the high field region before the drain. The present invention provides a method of manufacturing a MOS FET that can be formed to improve the operating characteristics of the device by adjusting the strength and direction of the electric field applied to the channel and the capacitance of the gate oxide film.
도 1은 종래 기술에 따른 MOS FET 의 단면도.1 is a cross-sectional view of a MOS FET according to the prior art.
도 2는 도 1 MOS FET 의 전계 분포 그래프.2 is a field distribution graph of the MOS FET of FIG. 1;
도 3a 내지 도 3d는 본 발명의 일실시예에 따른 MOS FET의 제조 공정도.3A to 3D are diagrams illustrating a manufacturing process of a MOS FET according to an embodiment of the present invention.
도 4는 도3d의 MOS FET의 전계 분포 그래프.4 is a field distribution graph of the MOS FET of FIG. 3D;
도 5는 본 발명의 다른 실시예에 따른 MOS FET의 제조 공정중 일부의 단면도.5 is a cross-sectional view of a portion of a manufacturing process of a MOS FET in accordance with another embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 반도체기판, 12 : 게이트산화막, 14 : 게이트전극, 16 : 절연 스페이서, 18 : 소오스/드레인 영역, 20 : 패드산화막, 22 : 질화막, 26 : 트랜치, 28 : 소자분리 산화막, 30 : 다결정 실리콘층, 32 : 평탄화막, 34 : 감광막 패턴, 40 : 열산화막10: semiconductor substrate, 12: gate oxide film, 14: gate electrode, 16: insulating spacer, 18: source / drain region, 20: pad oxide film, 22: nitride film, 26: trench, 28: device isolation oxide film, 30: polycrystalline silicon Layer, 32: planarization film, 34: photosensitive film pattern, 40: thermal oxide film
상기와 같은 목적을 달성하기 위한 본 발명에 따른 MOS FET의 특징은, 제 1도전형의 반도체기판의 일정 부분을 노출시키는 패드산화막 패턴과 질화막 패턴을 형성하는 공정과,Features of the MOS FET according to the present invention for achieving the above object is a step of forming a pad oxide film pattern and a nitride film pattern for exposing a portion of the semiconductor substrate of the first conductive type;
상기 질화막 패턴에 의해 노출되어있는 반도체기판을 식각하여 경사진 측벽을 갖는 트랜치를 형성하는 공정과,Etching the semiconductor substrate exposed by the nitride film pattern to form a trench having an inclined sidewall;
상기 질화막 패턴과 패드산화막을 제거하고, 상기 트랜치의 저부 및 상측의 반도체기판에서 소자분리 영역으로 예정되어 있는 부분에 소자분리 산화막을 형성하는 공정과,Removing the nitride film pattern and the pad oxide film, and forming a device isolation oxide film on a portion of the bottom and upper semiconductor substrate of the trench, the device isolation region being formed as a device isolation region;
상기 구조의 전표면에 게이트 산화막과 다결정 실리콘층을 순차적으로 형성하는 공정과,Sequentially forming a gate oxide film and a polycrystalline silicon layer on the entire surface of the structure;
상기 구조의 전표면에 평탄화막을 형성하는 공정과,Forming a planarization film on the entire surface of the structure;
상기 평탄화된 편탄화막상에 감광막 패턴을 형성하되, 상기 단차 상하의 양측 부분과 중첩되도록 형성하는 공정과,Forming a photoresist pattern on the planarized knitted carbonization layer, and forming a photoresist pattern to overlap both sides of the stepped top and bottom;
상기 평탄화막의 상부를 CMP방법으로 평탄화시키는 공정과,Planarizing an upper portion of the planarization film by a CMP method;
상기 감광막 패텅에 의해 노출되어있는 평탄화막과 다결정 실리콘층 및 게이트산화막을 순차적으로 식각하여 단차의 상하부 및 측벽에 걸쳐지는 채널을 갖는 게이트전극을 형성하는 공정과,Sequentially etching the planarization film, the polycrystalline silicon layer, and the gate oxide film exposed by the photosensitive film package to form a gate electrode having a channel spanning the top, bottom, and sidewalls of the step;
상기 평탄화막의 남은 부분을 제거하는 공정과,Removing the remaining portion of the planarization film;
상기 게이트전극 양측의 반도체기판에 제 2도전형의 불순물로 소오스/드레인 영역을 형성하는 공정을 구비함에 있다.And forming a source / drain region of the second conductive type impurity on the semiconductor substrates on both sides of the gate electrode.
본 발명의 다른 특징은,Another feature of the invention,
제 1도전형의 반도체기판의 일정 부분을 노출시키는 패드산화막 패턴과 질화막 패턴을 형성하는 공정과,Forming a pad oxide film pattern and a nitride film pattern exposing a portion of the first conductive semiconductor substrate;
상기 질화막 패턴에 의해 노출되어있는 반도체기판을 열산화시켜 열산화막을 형성하는 공정과,Thermally oxidizing the semiconductor substrate exposed by the nitride film pattern to form a thermal oxide film;
상기 열산화막을 제거하여 경사진 측벽을 갖는 트랜치를형성하는 공정과,Removing the thermal oxide film to form a trench having an inclined sidewall;
상기 질화막 패턴과 패드산화막을 제거하고, 상기 트랜치의 저부 및 상측의 반도체기판에서 소자분리 영역으로 예정되어있는 부분에 소자분리 산화막을 형성하는 공정과,Removing the nitride layer pattern and the pad oxide layer, and forming a device isolation oxide layer on a portion of the bottom and upper semiconductor substrate of the trench, the device isolation region being formed as a device isolation region;
상기 구조의 전표면에 게이트 산화막과 다결정 실리콘층을 순차적으로 형성하는 공정과,Sequentially forming a gate oxide film and a polycrystalline silicon layer on the entire surface of the structure;
상기 구조의 전표면에 평탄화막을 형성하는 공정과,Forming a planarization film on the entire surface of the structure;
상기 평탄화막의 상부를 CMP 방법으로 평탄화시키는 공정과,Planarizing an upper portion of the planarization film by a CMP method;
상기 평탄화된 평탄화막상에 감광막 패턴을 형성하되, 상기 단차 상하의 양측부분과 중첩되도록 형성하는 공정과,Forming a photoresist pattern on the planarization planarization layer and overlapping both sides of the stepped top and bottom;
상기 감광막 패턴에 의해 노출되어있는 평탄화막과 다결정 실리콘층 및 게이트산화막을 순차적으로 식각하여 단차의 상하부 및 측벽에 걸쳐지는 채널을 갖는 게이트전극을 형성하는 공정과,Sequentially etching the planarization film, the polycrystalline silicon layer, and the gate oxide film exposed by the photosensitive film pattern to form a gate electrode having a channel covering the upper and lower portions and the sidewalls of the step;
상기 평탄화막의 남은 부분을 제거하는 공정과,Removing the remaining portion of the planarization film;
상기 게이트전극 양측의 반도체기판에 제 2도전형의 불순물로 소오스/드레인 영역을 형성하는 공정을 구비함에 있다.And forming a source / drain region of the second conductive type impurity on the semiconductor substrates on both sides of the gate electrode.
이하, 본 발명에 따른 MOS FET의 제조방법에 관하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a MOS FET according to the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3d는 본 발명의 일실시예에 따른 MOS FET의 제조공정도이다.3A to 3D are manufacturing process diagrams of a MOS FET according to an embodiment of the present invention.
먼저, 제 1도전형, 예를 들어 P형 실리콘 웨이퍼로된 반도체기판(10)상에 패드산화막(20)과 질화막(22)패턴을 형성하고, 반도체기판(10)을 소정 깊이 식각하여 트랜치(26)를 형성한다. 이때 상기 트랜치(26)의 경계면이 급격한 각으로 변화되지 않도록 경사진 측벽을 갖는다. (도 3a 참조).First, a pad oxide film 20 and a nitride film 22 pattern are formed on a semiconductor substrate 10 made of a first conductive type, for example, a P-type silicon wafer, and the semiconductor substrate 10 is etched to a predetermined depth to form a trench ( 26). At this time, the trench 26 has an inclined sidewall so that the boundary surface of the trench 26 does not change at a sharp angle. (See FIG. 3A).
그다음 상기 질화막 (22)패턴과 패드산화막(20)을 제거하고, 상기 트랜치(26)의 저부 및 상측의 반도체기판(10)에서 소자분리 영역으로 예정되어있는 부분에 소자분리 산화막(28)을 형성한 후, 상기 구조의 게이트 산화막(12)과 다결정 실리콘층(30)을 순차적으로 형성한 후, 상기 구조의 전표면에 흐름성이 우수한 재질, 예를 들어 비.피.에스.지(Boro Phosphor Silicate Glass; 이하 BPSG라 칭함)등으로된 평탄화막(32)을 형성하고, 이를 리플로우시켜 평탄화시킨다. 이때 평탄화막(32)의 두께는 단차의 정도를 고려하여 충분히 평탄화되도록 조절한다. (도 3b참조).Then, the nitride layer 22 pattern and the pad oxide layer 20 are removed, and the isolation layer 28 is formed on the bottom of the trench 26 and the semiconductor substrate 10 on the upper side of the semiconductor substrate 10. Thereafter, the gate oxide film 12 and the polycrystalline silicon layer 30 having the structure are sequentially formed, and then a material having excellent flowability on the entire surface of the structure, for example, B. Ph.phor (Boro Phosphor) A planarization film 32 made of Silicate Glass (hereinafter referred to as BPSG) or the like is formed and reflowed to planarize it. At this time, the thickness of the flattening film 32 is adjusted to be sufficiently flattened in consideration of the degree of the step. (See Figure 3b).
그후, 상기 평탄화막(32)의 표면을 화학-기계적 연마(chemical mechanical polisihg; 이하 CMP라 칭함)방법으로 연마하여 표면을 평탄화시킨후, 상기 평탄화막(32)상에 게이트 패턴닝용 감광막 패턴(34)을 형성한다. 이때 상기 감광막 패턴(34)은 단차의 양측 부분과 중첩되도록 형성하는데, 이는 단차 하부의 소오스 지역 게이트 산화막(12)의 길이 Ⅰ와 단차 상부의 드레인 지역 게이트산화막(12)의 길이 Ⅱ를 조절하면 트랜지스터의 여러가지 특성을 조절할 수 있으므로, 감광막 패턴(34)의 정확한 디판인이 요구되며, 평탄화막(32)이 완전하게 평탄화되어 있으므로 촛점심도등의 특성이 향상된다. (도 3c 참조).Thereafter, the surface of the planarization film 32 is polished by chemical mechanical polishing (hereinafter referred to as CMP) method to planarize the surface, and then the photoresist pattern 34 for gate patterning is formed on the planarization film 32. ). At this time, the photoresist pattern 34 is formed so as to overlap both sides of the step, which is controlled by adjusting the length I of the source region gate oxide film 12 below the step and the length II of the drain region gate oxide film 12 above the step. Since various characteristics of the photosensitive film pattern 34 can be adjusted, accurate depanning of the photosensitive film pattern 34 is required, and the flattening film 32 is completely flattened, thereby improving characteristics such as focus depth. (See FIG. 3C).
그다음 상기 감광막 패턴(34)을 마스크로하여 노출되어 있는 평탄화막(32)과 다결정 실리콘층(30) 및 게이트산화막(12)을 순차적으로 식각하여 다결정 실리콘층(30) 패턴으로된 게이트전극을 형성하고, 상기 평탄화막(32)의 남은 부분을 제거한후, LDD공정으로 반도체기판(10)에 제 2도전형, 예를 들어 N형의 저농도 및 고농도 불순물 영역으로된 소오스/드레인 영역(18)을 형성하고, 상기 다결정 실리콘층(30) 패턴의 측벽에는 절연막 스페이서(16)를 형성한다. (도 3d 참조).Next, the planarization layer 32, the polycrystalline silicon layer 30, and the gate oxide layer 12 that are exposed using the photoresist pattern 34 as a mask are sequentially etched to form a gate electrode having the polycrystalline silicon layer 30 pattern. After the remaining portion of the planarization film 32 is removed, the source / drain regions 18 having low and high concentration impurity regions of a second conductivity type, for example, N type, are formed on the semiconductor substrate 10 by an LDD process. The insulating layer spacer 16 is formed on sidewalls of the polycrystalline silicon layer 30 pattern. (See FIG. 3D).
상기와 같이 형성된 MOS FET 는 소오스와 드레인간의 거리가 단차에 의해 멀어져 그 사이의 전기장의 세기를 감소시키고, 드레인 바이어스와 빌트인 필에 의한 전기장의 방향을 어긋나게 형성하여 전기장의 합력을 감소시킴과 아울러 채널이 굽어져 있어 채널을 따라 주입되는 전하의 계속적인 가속을 방지하여 소자의 동작특성을 향상시킬 수 있으며, 부수적으로 단차 지역을 이용하므로 좁은 면적이 다수개의 MOS FET를 향상할 수 있어 소자의 고집적화에 유리하다.The MOS FET formed as described above reduces the strength of the electric field between the source and the drain by the step difference, and forms the displacement of the electric field due to the drain bias and the built-in fill, thereby reducing the force of the electric field and the channel. This curved structure prevents the continuous acceleration of charges injected along the channel, improving the operation characteristics of the device.In addition, by using the stepped area, a small area can improve the number of MOS FETs, resulting in high integration of the device. It is advantageous.
여기서 단차의 높이와 기울기, 소오스 드레인 앞의 게이트 산화막의 길이 이 3가지 요인에 의해 드레인 앞의 전기장의 직접적인 크기가 영향을 받는다.Here, the direct size of the electric field in front of the drain is influenced by three factors: the height and the slope of the step and the length of the gate oxide film in front of the source drain.
도 5는 본 발명의 다른 실시예에 따른 MOS FET의 제조 공정중 일부의 단면도로서, 패드산화막(20)과 질화막(22) 패턴을 이용하여 노출된 반도체기판(10)을 열산화시켜 산화막(40)을 형성하고, 이를 제거하여 트랜치(26)을 형성한 것으로서, 상기 산화막(40)의 버즈빅을 이용하여 트랜치(26)의 경계면이 자연스럽게 부드러운 프로라일을 가지며, 경사면도 완만하게 형성되어 모서리로 인한 불량, 예를 들어 전계집중에 의한 게이트 산화막의 파괴등을 방지할 수 있다.5 is a cross-sectional view of a part of a manufacturing process of a MOS FET according to another exemplary embodiment of the present invention. The exposed semiconductor substrate 10 is thermally oxidized using the pad oxide film 20 and the nitride film 22 pattern to form an oxide film 40. ), And the trench 26 is formed by removing the trench 26. The boundary surface of the trench 26 has a naturally smooth prorail using the buzz of the oxide film 40, and the slope is smoothly formed to the edge. It is possible to prevent defects caused by, for example, destruction of the gate oxide film due to electric field concentration.
그 다음 도 3a의 후속 공정을 진행하여 단차진 채널을 구비하고 경사면 및 경계 부분이 완만하게 변화되는 MOS FET를 형성한다.The subsequent process of FIG. 3A then proceeds to form a MOS FET with stepped channels and gentle changes in slopes and boundary portions.
이상에서 설명한 바와 같이, 본 발명에 따른 MOS FET제조방법은 트랜치를 형성하고, 트랜치 상하의 노출된 반도체기판에 걸쳐지는 경사면을 채널로 이용하여 드레인에 인가되는 바이어스와 빌트인 필드의 합력을 감소시키고, 전하의 계속적인 가속도 방지하며, 경사면의 각도, 경사면 상하 부분의 길이 단차의 높이 등을 조절하여 MOS FET 의 특성을 조절하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, the MOS FET manufacturing method according to the present invention forms a trench, reduces the force of the bias and the built-in field applied to the drain by using the inclined surface that extends over the exposed semiconductor substrate above and below the trench as a channel, It is possible to improve the process yield and device operation reliability by controlling the characteristics of the MOS FET by controlling the acceleration of the inclined plane and adjusting the angle of the inclined plane and the height of the length step of the inclined plane.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970030294A KR100408728B1 (en) | 1997-06-30 | 1997-06-30 | Method for manufacturing mos field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970030294A KR100408728B1 (en) | 1997-06-30 | 1997-06-30 | Method for manufacturing mos field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990006072A true KR19990006072A (en) | 1999-01-25 |
| KR100408728B1 KR100408728B1 (en) | 2004-03-26 |
Family
ID=37422835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970030294A KR100408728B1 (en) | 1997-06-30 | 1997-06-30 | Method for manufacturing mos field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100408728B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7239841B2 (en) | 2003-07-01 | 2007-07-03 | Samsung Electronics Co., Ltd. | Used toner collecting apparatus of a laser printer |
| US20190046888A1 (en) * | 2016-02-17 | 2019-02-14 | Kyneprox S.R.L. | Multi-dynamic platform |
-
1997
- 1997-06-30 KR KR1019970030294A patent/KR100408728B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7239841B2 (en) | 2003-07-01 | 2007-07-03 | Samsung Electronics Co., Ltd. | Used toner collecting apparatus of a laser printer |
| US20190046888A1 (en) * | 2016-02-17 | 2019-02-14 | Kyneprox S.R.L. | Multi-dynamic platform |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100408728B1 (en) | 2004-03-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100282452B1 (en) | Semiconductor device and method for fabricating the same | |
| KR100261170B1 (en) | Semiconductor device and method for fabricating the same | |
| US6551870B1 (en) | Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer | |
| US7091092B2 (en) | Process flow for a performance enhanced MOSFET with self-aligned, recessed channel | |
| US6524903B2 (en) | Method of manufacturing a semiconductor device having two peaks in an impurity concentration distribution | |
| US6355955B1 (en) | Transistor and a method for forming the transistor with elevated and/or relatively shallow source/drain regions to achieve enhanced gate electrode formation | |
| US7790551B2 (en) | Method for fabricating a transistor having a recess gate structure | |
| US7883971B2 (en) | Gate structure in a trench region of a semiconductor device and method for manufacturing the same | |
| EP1138058B1 (en) | Method of manufacturing a semiconductor device having a gate with a varying work function | |
| KR900008153B1 (en) | Semiconductor device and its manufacturing method | |
| KR100718248B1 (en) | Method of forming a recess structure, a recessed channel type transistor having the recess structure, and method of manufacturing the recessed channel type transistor | |
| KR100374550B1 (en) | Semiconductor device and fabricating method thereof | |
| KR100488099B1 (en) | A mos transistor having short channel and a manufacturing method thereof | |
| KR100408728B1 (en) | Method for manufacturing mos field effect transistor | |
| US6110786A (en) | Semiconductor device having elevated gate electrode and elevated active regions and method of manufacture thereof | |
| KR100282453B1 (en) | Method for manufacturing semiconductor device the same | |
| JP2002057118A (en) | Semiconductor device and its manufacturing method | |
| KR100617051B1 (en) | method for manufacturing of semiconductor device | |
| KR101180500B1 (en) | Method for manufacturing Transistor | |
| CN113437148B (en) | Semiconductor structure and forming method thereof | |
| KR100597462B1 (en) | Method for fabricating transistor of semiconductor device | |
| JP3714396B2 (en) | Manufacturing method of semiconductor device | |
| KR100269280B1 (en) | Manufacture method of ldd type mos transistor | |
| KR100863687B1 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| KR100674645B1 (en) | Method of manufacturing semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20121022 Year of fee payment: 10 |
|
| FPAY | Annual fee payment |
Payment date: 20131017 Year of fee payment: 11 |
|
| LAPS | Lapse due to unpaid annual fee |