KR19990005912A - Flash memory cell and manufacturing method thereof - Google Patents

Abstract

1. Technical field to which the invention described in the claims belongs

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory cell and a method of manufacturing the same, and more particularly, to a flash memory cell to which a same bias is applied to a well and a junction and a method of manufacturing the same.

2. Technical problem that the invention tries to solve

Since the well bias contact portion is located at the boundary of the cell array in the flash memory cell, the RC delay time is increased and the size of the device is increased, thereby solving the problem of not being able to achieve high integration of the semiconductor device.

3. Summary of the solution of the invention

In forming a contact hole for connecting wires to a junction in a flash memory cell, a well pick-up region may be selectively formed only at a junction to which the same bias is applied to the well so that the bias may be simultaneously applied to the well and the junction.

4. Important uses of the invention

The same bias is applied to all semiconductor devices where the same bias is applied to the wells and junctions.

Description

Flash memory cell and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory cell and a method of manufacturing the same, and more particularly, to a flash memory cell to which a same bias is applied to a well and a junction and a method of manufacturing the same.

A program, erase, and read operation of a flash memory cell having a conventional P-well structure will now be described with reference to FIG. 1.

The flash memory cell of the conventional P-well structure includes a floating gate 5, a control gate 7, a source 2, and a drain 3 in the P-well 1. The floating gate 5 and the control gate 7 are formed in a stacked structure, and a tunnel oxide film 4 is formed between the floating gate 5 and the P-well 1, and the floating gate 5 and the control gate ( A dielectric film 6 is formed between 7).

The program operation of the flash memory cell having the above-described configuration is performed by applying a voltage of 5 V to the drain 3 and 9 V to the control gate 7, and the source 2 and the P-well 1 to the ground state. Program using the electron injection method.

In the erase operation of the flash memory cell, a voltage of 5 V is applied to the source 2 and -9 V to the control gate 7, the drain 3 is floating, and the P-well 1 is grounded. It is erased using FN Tunnel method.

In the read operation of the flash memory cell, a voltage of 1 V is applied to the drain 3 and 5 V to the control gate 7, and the source 2 and the P-well 1 are grounded, respectively. Read out.

As described above, in the P-well structure flash memory cell, the P-well 1 is always grounded during program, erase, and read operations. If the P-well 1 can be biased, it is possible to make a cell having further improved erase characteristics. In order to be able to bias the P-well 1, a triple well formation technique has been developed.

The flash memory cell of the triple well structure shown in FIG. 2 forms the P-well 12 in the N-well 11, and the floating gate 16, the control gate 18, and the source in the P-well 12. 13 and the drain 14. The floating gate 16 and the control gate 18 are formed in a stacked structure, and a tunnel oxide film 15 is formed between the floating gate 16 and the P-well 12, and the floating gate 16 and the control gate ( A dielectric film 17 is formed between 18.

FIG. 3 illustrates a cell array in which a flash memory cell having a triple well structure having the above configuration is used as a unit cell. A plurality of well bias contact portions 22 are formed around the cell array region 21 illustrated in FIG. 3. 4 shows the layout of the cell array region 21 in which one source contact 26 is formed for every 16 cells in the direction of the word line 24. The reference numeral 23 is a field oxide film, the reference numeral 25 is a drain contact, and the reference numeral 26 is a source contact. The control gate 18 becomes a word line.

FIG. 5 is a cross-sectional view of the well bias contact portion 22 illustrated in FIG. 3 taken along a line A4-A4, wherein the pick-up region 27 formed in the P-well 12 is formed by the metal wiring 29. It is shown drawn outward. Reference numeral 28 is an interlayer insulating film.

FIG. 6 is a cross-sectional view of the source contact 26 shown in FIG. 4 taken along line A6-A6, in which the source 13 formed in the P-well 12 is drawn out to the outside by the metal wire 29. As shown in FIG. Shown.

The flash memory cell of the triple well structure described above has the same program and read operations as the flash memory cell of the P-well structure, except that the erase operation is different.

The erase operation of the flash memory cell of the triple well structure is applied with a voltage of 9V to the N-well 11, 8V to the P-well 12, 8V to the source 13, -9V to the control gate 18, The drain 14 erases the program in the floating state.

As described above, since the well bias voltage is applied through the plurality of well bias contact portions 22 formed around the cell array region 21 illustrated in FIG. 3, the RC delay time is not only long but also the plurality of well bias contacts. The disadvantage is that the size of the device is increased by the area occupied by the unit 22.

Accordingly, the present invention provides a flash memory cell capable of solving the above-described problems by forming a well bias contact portion in a junction in a cell array region in a flash memory cell in which a same bias is applied to a well and a junction. Its purpose is to provide its manufacturing method.

According to an aspect of the present invention, a silicon substrate is etched by forming a source contact hole and a drain contact hole in a flash memory cell having a triple well structure and an etching process using a photoresist pattern in which only the source contact hole is opened. Then, the method may include forming well pick-up regions by an impurity ion implantation process, and removing the photoresist pattern, and then forming metal wiring by a metal contact process.

The present invention for achieving the above object is a flash memory cell consisting of a floating gate, a control gate, a source and a drain on a semiconductor substrate having a triple well structure, the structure having a well pick-up region formed under the source contact portion It is done.

1 is a cross-sectional view of a flash memory cell of a P-well structure according to the prior art.

2 is a cross-sectional view of a flash memory cell of a triple well structure according to the prior art;

3 is a plan view of a cell array having the flash memory cell of FIG. 2 as a unit cell;

4 is a layout diagram of a cell array portion of FIG. 3;

5 is a cross-sectional view taken along the line A4-A4 of FIG. 3.

6 is a cross-sectional view taken along the line A6-A6 of FIG. 4.

7A to 7C are cross-sectional views illustrating a method of manufacturing a flash memory cell having a triple well structure according to an embodiment of the present invention.

Explanation of symbols for main parts of the drawings

1, 12, and 32: P-wells 2, 13, and 33: sources

3, 14, and 34: drains 4, 15, and 35: tunnel oxide film

5, 16, and 36: floating gates 6, 17, and 37: dielectric film

7, 18 and 38: control gates 11 and 31: N-well

21: cell array region 22: well bias contact portion

23: field oxide film 25: drain contact

26: source contact 27 and 47: well pick-up area

28 and 48: interlayer insulating film 29 and 49: metal wiring

45 and 46: contact hole 50: photoresist pattern

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

In the flash memory cell of the triple well structure, as mentioned in FIG. 2, the same bias is applied to the well and the source during the program, erase, and read operations.

7A to 7C are cross-sectional views of devices for describing a method of manufacturing a flash memory cell having a triple well structure according to an exemplary embodiment of the present invention.

Referring to FIG. 7A, a flash memory cell having a triple well structure includes a floating gate 36, a control gate 38, a source 33, and a drain in a P-well 32 formed in an N-well 31. It consists of 34. The floating gate 36 and the control gate 38 are formed in a stacked structure, and a tunnel oxide film 35 is formed between the floating gate 36 and the P-well 32, and the floating gate 36 and the control gate ( A dielectric film 37 is formed between 38.

An interlayer insulating layer 48 is formed on the entire structure including the flash memory cell, and a source contact hole 46 and a drain contact hole 45 are formed in the source 33 and the drain 34, respectively.

Referring to FIG. 7B, a portion where the same bias is applied to the well and the junction, that is, all portions except the source 33 portion of the flash memory cell are covered with the photoresist pattern 50, and the photoresist pattern 50 is etched. The silicon substrate in the source contact hole 46 is etched about 500 to 3,000 Å by an etching process using a mask so that the P-well 32 is sufficiently exposed. Thereafter, an impurity ion implantation process using any one of B and BF ₂ is performed to form a pick up region 47 in the P-well 32. Thereafter, the photoresist layer pattern 50 is removed and the metal wiring 49 is formed in the source contact hole 46 and the drain contact hole 45 as shown in FIG. 7C.

The cell array can be configured as shown in FIG. 4 using the flash memory cell of the triple well structure of the present invention as a unit cell, and the pick-up region 47 is formed in the source contact portion 26 different from the conventional cell array.

The pickup area 47 of the present invention is the same as the source contact 46 without being formed in the periphery of the cell array as compared with the pickup area 22 formed in the conventional well bias contact portion 22 shown in FIG. Formed in position. Accordingly, since the voltage is directly applied to the P-well 32 at the time of applying the voltage for the erase operation, and the well bias contact portion 22 shown in FIG. 3 is not required, the device can be highly integrated.

Although the present invention described above has been described with a flash memory cell having a triple well structure as an embodiment, the principles of the present invention described above can be applied to all semiconductor devices to which the same bias is applied to the well and the junction.

That is, the bias is applied to the well and the junction at the same time by additionally etching only the junction where the same bias is applied to the well when forming the contact hole for connecting the wiring to the junction in the flash memory cell, and forming a pickup region by an impurity ion implantation process. .

As described above, in the present invention, since the junction and the well are formed as one contact in the flash memory cell in which the same bias is applied to the well and the junction, the size and the RC delay time of the device may be reduced.

Claims (4)

Forming a source contact hole and a drain contact hole in a flash memory cell having a triple well structure, etching the silicon substrate by an etching process using a photoresist pattern in which only the source contact hole is opened, and then picking up the well by an impurity ion implantation process Forming a region, and forming a metal wiring by a metal contact process after removing the photoresist pattern. 2. The method of claim 1, wherein the etching process comprises etching the silicon substrate to a depth of 500 to 3000 microns so that the wells are sufficiently exposed. The method of claim 1, wherein the impurity ions are any one of B and BF ₂ . A flash memory cell comprising a floating gate, a control gate, a source, and a drain on a semiconductor substrate having a triple well structure, wherein the well pick-up region is formed under the source contact portion.