KR19990005880A - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
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- KR19990005880A KR19990005880A KR1019970030098A KR19970030098A KR19990005880A KR 19990005880 A KR19990005880 A KR 19990005880A KR 1019970030098 A KR1019970030098 A KR 1019970030098A KR 19970030098 A KR19970030098 A KR 19970030098A KR 19990005880 A KR19990005880 A KR 19990005880A
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- oxide film
- metal
- semiconductor device
- metal layer
- copper
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 35
- 239000002184 metal Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 title abstract 2
- 239000010949 copper Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 20
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 20
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052802 copper Inorganic materials 0.000 claims abstract description 17
- 238000000059 patterning Methods 0.000 claims abstract description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 3
- 238000002230 thermal chemical vapour deposition Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 description 31
- 239000000460 chlorine Substances 0.000 description 12
- 239000007789 gas Substances 0.000 description 9
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 7
- 229910052801 chlorine Inorganic materials 0.000 description 7
- 239000010409 thin film Substances 0.000 description 6
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 4
- 229910052731 fluorine Inorganic materials 0.000 description 4
- 239000011737 fluorine Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910016509 CuF 2 Inorganic materials 0.000 description 1
- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속배선 형성 방법에 관한 것으로, 구리(Cu)로 이루어진 금속층상에 금속산화막을 형성하고 금속산화막을 식각 마스크로 이용하여 금속층을 패터닝하므로써 소자의 전기적 특성이 향상될 수 있도록 한 반도체 소자의 금속배선 형성 방법에 관한 것이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, by forming a metal oxide film on a metal layer made of copper (Cu) and patterning the metal layer using the metal oxide film as an etching mask to improve the electrical properties of the device A metal wiring formation method of a semiconductor device.
Description
본 발명은 반도체 소자의 금속배선 형성 방법에 관한 것으로, 특히 구리(Cu)로 이루어진 금속층을 패터닝하는 과정에서 발생되는 소자의 전기적 특성 저하를 방지할 수 있도록 한 반도체 소자의 금속배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device in order to prevent a decrease in electrical characteristics of a device generated during patterning a metal layer made of copper (Cu). .
일반적으로 반도체 소자의 제조 공정에서 금속배선은 알루미늄(Al), 텅스텐(W) 등과 같은 금속으로 형성된다. 그러나 반도체 소자가 초고집적화됨에 따라 상기와 같은 금속을 이용하여 더 이상 금속배선을 형성하기 어려운 실정이다. 그래서 초고집적(ULSI) 반도체 소자의 제조 공정에서는 구리(Cu)를 이용하여 금속배선을 형성한다.In general, in the process of manufacturing a semiconductor device, the metal wiring is formed of a metal such as aluminum (Al), tungsten (W), or the like. However, as semiconductor devices are highly integrated, it is difficult to form metal wires using the above metals anymore. Therefore, in the manufacturing process of the ultra-high integrated (ULSI) semiconductor device, metal wiring is formed using copper (Cu).
구리(Cu)는 대개 염소(Cl)계의 가스를 이용한 플라즈마 식각 공정으로 패터닝한다. 그러나 식각 공정시 생성되는 식각 부산물의 증기압이 매우 낮기 때문에 이를 보상하기 위해서는 기판의 온도를 최소한 200 ℃ 이상으로 유지시켜야 한다. 따라서 종래에 사용되는 감광막은 150 ℃ 이상의 온도에서 물성이 저하되기 때문에 구리(Cu) 식각 공정시 감광막을 식각 마스크로 사용할 수 없는 문제점이 발생된다.Copper (Cu) is usually patterned by a plasma etching process using a chlorine (Cl) -based gas. However, since the vapor pressure of the etch by-products generated during the etching process is very low, the temperature of the substrate must be maintained at least 200 ° C. to compensate for this. Therefore, the conventional photosensitive film has a problem that the photosensitive film cannot be used as an etching mask during the copper (Cu) etching process since physical properties are lowered at a temperature of 150 ° C. or higher.
상기와 같은 문제점으로 인해 근래에는 WN, TaN, SiN 등과 같은 물질을 식각 마스크로 이용하는 기술을 개발하고 있다. 그러나 TiN, WN 등을 사용하는 경우 TiN, WN 등은 전도성을 갖기 때문에 금속배선 형성후 전기적 절연을 위한 절연막 형성 공정이 추가된다. 또한, SiN를 사용하는 경우 구리(Cu) 박막에 의한 스트레스(Stress)에 의해 전자 이동(Electro Migration), 스트레스 이동(Stress Migration) 등이 유발된다. 그리고 불소(F)계의 가스를 이용한 플라즈마 식각 공정시 구리(Cu) 박막 표면에 증기압이 매우 낮은 식각 부산물(CuF2)이 존재하게 되어 구리(Cu) 박막의 식각을 어렵게 한다.Due to the above problems, in recent years, a technology using a material such as WN, TaN, SiN, etc. as an etching mask has been developed. However, in the case of using TiN, WN, etc., since TiN, WN, and the like have conductivity, an insulating film forming process for electrical insulation is added after metal wiring is formed. In addition, when SiN is used, electron migration and stress migration are caused by stress caused by a copper thin film. In the plasma etching process using a fluorine (F) -based gas, etching by-products (CuF 2 ) having a very low vapor pressure exist on the surface of the copper (Cu) thin film, thereby making it difficult to etch the copper (Cu) thin film.
따라서 본 발명은 구리(Cu)로 이루어진 금속층상에 금속산화막을 형성하고 상기 금속산화막을 식각 마스크로 이용하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 금속배선 형성 방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of solving the above-mentioned disadvantages by forming a metal oxide film on a metal layer made of copper (Cu) and using the metal oxide film as an etching mask. .
상기한 목적을 달성하기 위한 본 발명은 절연막이 형성된 기판상에 구리를 증착하여 금속층을 형성한 후 상기 금속층상에 알루미늄 산화막을 증착하여 금속산화막을 형성하는 단계와, 상기 단계로부터 상기 금속산화막을 패터닝한 후 패터닝된 상기 금속산화막을 식각 마스크로 이용하여 상기 금속층을 식각하는 단계로 이루어지는 것을 특징으로 하고, 상기 알루미늄 산화막은 Thermal CVD 방법 및 MOCVD 방법중 어느 하나의 방법으로 형성하는 것을 특징으로 한다.The present invention for achieving the above object is formed by depositing copper on a substrate on which an insulating film is formed to form a metal layer and then depositing an aluminum oxide film on the metal layer to form a metal oxide film, patterning the metal oxide film from the step And then etching the metal layer using the patterned metal oxide film as an etching mask, wherein the aluminum oxide film is formed by any one of a thermal CVD method and a MOCVD method.
도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
도면의 주요부분에 대한 기호설명Symbol description for main parts of drawing
1 : 실리콘 기판 2 : 절연막1 silicon substrate 2 insulating film
3: 금속층 4 : 금속산화막3: metal layer 4: metal oxide film
5: 감광막 패턴5: photoresist pattern
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of devices for describing a method for forming metal wirings of a semiconductor device according to the present invention.
도 1a는 절연막(2)이 형성된 실리콘 기판(1)상에 구리(Cu)를 증착하여 금속층(3)을 형성한 후 상기 금속층(3)상에 금속산화막(4)을 형성하고 상기 금속산화막(4)상에 감광막 패턴(5)을 형성한 상태의 단면도로서, 상기 금속산화막(4)은 알루미늄 산화막으로 형성한다. 여기서 상기 알루미늄 산화막은 화학기상증착CVD) 또는 물리기상증착(PVD) 방법으로 형성할 수 있으며, 예를들어 Thermal CVD 방법으로 형성된 AlCl3, MOCVD 방법으로 형성된 (OC3H7)3등이 사용된다.FIG. 1A illustrates that a metal layer 3 is formed by depositing copper (Cu) on a silicon substrate 1 on which an insulating film 2 is formed, and then a metal oxide film 4 is formed on the metal layer 3. 4 is a cross-sectional view of the photosensitive film pattern 5 formed on the metal oxide film 4, which is formed of an aluminum oxide film. The aluminum oxide film may be formed by chemical vapor deposition CVD or physical vapor deposition (PVD). For example, AlCl 3 formed by Thermal CVD and (OC 3 H 7 ) 3 formed by MOCVD may be used. .
도 1b는 상기 감광막 패턴(5)을 마스크로 이용하여 노출된 부분의 상기 금속산화막(4)을 식각한 상태의 단면도로서, 상기 식각 공정은 2단계로 이루어진다. 제 1 단계 식각 공정은 200 내지 300 mT의 압력 및 220 내지 400 ℃의 온도 조건 그리고 염소(Cl)계의 가스(CCl4, BCl3, SiCl4) 및 질소(N2) 가스 분위기하에서 실시되며, 공급되는 전력은 250 내지 300 W가 되도록한다. 이때 상기 금속산화막(4) 전체 두께의 4/5 이상이 식각되도록 한다. 제 2 단계의 식각 공정은 50 내지 100 mT의 압력 및 아르곤(Ar) 가스 분위기하에서 실시되며, 공급되는 전력은 450 내지 700 W가 되도록한다. 이때 점차적으로 염소(Cl) 가스의 량을 감소시켜 구리(Cu) 박막과의 반응을 억제한다.FIG. 1B is a cross-sectional view of the exposed portion of the metal oxide film 4 using the photosensitive film pattern 5 as a mask, and the etching process is performed in two steps. The first step etching process is carried out under a pressure of 200 to 300 mT and a temperature of 220 to 400 ℃ and a chlorine (Cl) -based gas (CCl 4 , BCl 3 , SiCl 4 ) and nitrogen (N 2 ) gas atmosphere, The power supplied is 250 to 300 W. At this time, 4/5 or more of the total thickness of the metal oxide film 4 is etched. The etching process of the second step is carried out under a pressure of 50 to 100 mT and an argon (Ar) gas atmosphere, and the power supplied is 450 to 700 W. At this time, by gradually reducing the amount of chlorine (Cl) gas to suppress the reaction with the copper (Cu) thin film.
도 1c는 상기 도 1b의 상태에서 염소(Cl)계 또는 불소(F)계의 가스를 이용한 플라즈마 식각 공정으로 노출된 부분의 상기 금속층(3)을 식각한 상태의 단면도이다.FIG. 1C is a cross-sectional view of the metal layer 3 etched in a portion exposed by a plasma etching process using a chlorine (Cl) -based or fluorine (F) -based gas in the state of FIG. 1B.
본 발명은 금속산화막을 식각 마스크로 이용하여 구리(Cu)로 이루어진 금속층을 식각한다. 그리고 상기 금속산화막으로는 알루미늄 산화막을 사용한다. 알루미늄 산화막은 첫째, 불활성이며 2015 ℃에서 용해되는 고산화 저항성 물질이기 때문에 높은 절연 특성을 갖는다. 둘째, 염소(CL)계 또는 불소(F)계의 가스를 이용한 플라즈마 식각 공정시 구리(Cu) 박막에 비해 식각 속도가 매우 늦기 때문에 감광막을 사용하는 경우보다 높은 식각 선택비(10 : 1 이상)를 갖는다. 그리고 셋째, 식각 특성이 화학적 인자보다 이온 충돌 에너지(전력, 압력, 기판 바이어스)에 의존되기 때문에 식각 과정에서 염소(Cl)계 또는 불소(F)계의 가스에 의한 구리(Cu) 박막의 피해가 최소화된다.In the present invention, a metal layer made of copper (Cu) is etched using a metal oxide film as an etching mask. An aluminum oxide film is used as the metal oxide film. The aluminum oxide film is firstly inert and has high insulation properties because it is a high oxidation resistant material that dissolves at 2015 ° C. Second, in the plasma etching process using chlorine (CL) or fluorine (F) gas, the etching rate is very slow compared to the copper (Cu) thin film, so the etching selectivity higher than that of the photosensitive film (10: 1 or more) Has Third, since the etching characteristics depend on the ion bombardment energy (power, pressure, substrate bias) rather than chemical factors, the damage of the copper thin film by chlorine (Cl) or fluorine (F) based gas during the etching process is avoided. Is minimized.
상술한 바와 같이 본 발명은 구리(Cu)로 이루어진 금속층상에 금속산화막을 형성하고 상기 금속산화막을 식각 마스크로 이용하여 금속층을 식각한다. 이때 상기 금속산화막으로 알루미늄 산화막을 사용하므로써 금속배선의 전기적 절연도가 향상되며 금속층 패터닝 공정이 용이하게 이루어지고 식각 공정시 발생되는 금속층의 피해가 최소화된다. 따라서 소자의 전기적 특성 및 수율이 향상될 수 있는 탁월한 효과가 있다.As described above, the present invention forms a metal oxide film on a metal layer made of copper (Cu) and etches the metal layer using the metal oxide film as an etching mask. In this case, by using the aluminum oxide film as the metal oxide film, the electrical insulation of the metal wiring is improved, the metal layer patterning process is easily performed, and the damage of the metal layer generated during the etching process is minimized. Therefore, there is an excellent effect that can improve the electrical characteristics and yield of the device.
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| KR1019970030098A KR100250725B1 (en) | 1997-06-30 | 1997-06-30 | Process for fabricating metal interconnector of semiconductor device |
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| KR100655137B1 (en) * | 2000-06-30 | 2006-12-08 | 주식회사 하이닉스반도체 | Method for forming alumina layer by using MOCVD and method for FeRAM using the same |
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| KR100655137B1 (en) * | 2000-06-30 | 2006-12-08 | 주식회사 하이닉스반도체 | Method for forming alumina layer by using MOCVD and method for FeRAM using the same |
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