KR19990005501A - Method of forming a protective film of a semiconductor device - Google Patents
Method of forming a protective film of a semiconductor device Download PDFInfo
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- KR19990005501A KR19990005501A KR1019970029699A KR19970029699A KR19990005501A KR 19990005501 A KR19990005501 A KR 19990005501A KR 1019970029699 A KR1019970029699 A KR 1019970029699A KR 19970029699 A KR19970029699 A KR 19970029699A KR 19990005501 A KR19990005501 A KR 19990005501A
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- protective film
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술 분야1. TECHNICAL FIELD OF THE INVENTION
반도체 장치 제조 방법.Semiconductor device manufacturing method.
2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention
반도체 공정의 최종 공정인 보호막 형성 공정에서 소자의 고집적화에 따른 심한 단차로 인한 금속선의 부식을 방지하고자 함.In the protective film forming process, which is the final process of the semiconductor process, it is intended to prevent the corrosion of metal wires due to the severe step by high integration of the device.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
금속선 형성 후에 단차피복성이 우수한 (HSiO3/2)n를 형성하고, 다음에 질화막을 형성하는 보호막을 형성함.After the formation of the metal lines, (HSiO3 / 2) n having excellent step coverage is formed, and then a protective film for forming a nitride film is formed.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 장치 제조 공정 중 금속 배선 공정에 이용됨.Used in metal wiring process in semiconductor device manufacturing process.
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 마지막으로 증착되어 소자를 외부의 충격으로부터 보호하는 보호막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a protective film which is deposited to protect the device from external impact.
일반적으로 반도체 소자의 제조 공정에 있어서, 모든 소자의 제조 공정이 끝난 후 웨이퍼의 긁힘을 방지하고 알칼리 및 중금속의 오염을 방지하기 위해 플라즈마 화학 증착 방법으로 실리콘 산화막이나 질화막 및 인유리막을 이용하여 형성하는 보호막 형성 공정은 반도체 소자 제조 공정중 최종 공정으로서 제품의 신뢰성과 밀접한 관계를 갖는다.In general, in the manufacturing process of a semiconductor device, after the completion of the manufacturing process of all the devices to form a silicon oxide film, a nitride film and a phosphorus film by plasma chemical vapor deposition to prevent scratches of the wafer and to prevent contamination of alkali and heavy metals The protective film forming process is a final step in the semiconductor device manufacturing process and has a close relationship with the reliability of the product.
실리콘 산화막은 수분 및 Na+이온에 대한 저항력이 불량하지만 물질 상호간의 응력이 낮추기 위하여 사용된다. 또한 질화막은 조직이 치밀하고 경도가 높기 때문에 소자의 물리적 손상이나 불순물의 침입을 막기 위한 최종 보호막으로 사용된다.Silicon oxide film is poor in resistance to moisture and Na + ions, but is used to lower the stress between materials. In addition, since the nitride film has a dense structure and high hardness, the nitride film is used as a final protective film to prevent physical damage or intrusion of impurities.
도 1A 내지 도1C는 종래의 반도체 장치의 보호막 형성 방법을 나타내는 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a protective film of a conventional semiconductor device.
먼저, 도1A에 도시된 바와 같이, 실리콘 기판(11)상에 내부 금속 배선층을 감싸는 제1절연막(12)을 형성하고, 제2절연막으로 BPSG막(13)을 형성하여 평탄화 공정을 수행한다.First, as shown in FIG. 1A, a first insulating film 12 surrounding an inner metal wiring layer is formed on a silicon substrate 11, and a BPSG film 13 is formed as a second insulating film to perform a planarization process.
다음으로 도1B에 도시된 바와 같이, 전체 구조 상부에 장벽 금속층(14)과 금속층(15)을 적층한 후 식각 공정하여 금속선을 패터닝한다.Next, as shown in FIG. 1B, the barrier metal layer 14 and the metal layer 15 are stacked on the entire structure and then etched to pattern the metal wire.
마지막으로 도1C에 도시된 바와 같이, 플라즈마 화학 증착 방법으로 실리콘 산화막(SiO2, 16)과 실리콘 질화막(Si3N4, 17)을 차례로 형성한다.Finally, as shown in FIG. 1C, silicon oxide films (SiO 2 , 16) and silicon nitride films (Si 3 N 4 , 17) are sequentially formed by plasma chemical vapor deposition.
전술한 바와 같이 이루어지는 보호막 형성 방법은 소자의 고집적화에 따른 문제점이 대두되고 있다. 즉, 최종적으로 형성되는 금속 배선막의 단차가 심하게 되어, 에스펙트 비가 큰 부분에서는 금속막 위에 형성되는 막의 단락 현상이 일어나게 된다. 특히 저온으로 플라즈마 화학 증착 공정을 하는 보호막 형성 공정에서 단차피복성이 불량한 실리콘 산화막과 질화막의 형성시 각각의 막은 불량하게 증착되어 금속선이 대기중으로 노출되면서 수분이나 나트륨 이온에 의해 부식된다. 또한 소자의 신뢰성에 영향을 주어 소자의 수명이 단축되는 문제점을 야기시킨다.As described above, the protective film forming method has a problem due to the high integration of the device. That is, the level difference of the finally formed metal wiring film becomes severe, and the short circuit phenomenon of the film formed on a metal film occurs in the part with large aspect ratio. In particular, in the protective film forming process in which the plasma chemical vapor deposition process is performed at low temperature, when the silicon oxide film and the nitride film having poor step coverage are formed, each film is poorly deposited and is corroded by moisture or sodium ions as the metal wire is exposed to the atmosphere. In addition, the reliability of the device is affected, causing a problem of shortening the life of the device.
따라서, 전술한 바와 같이 이루어지는 보호막 형성 방법의 문제점을 해결할 수 있는, 즉 불량한 단차피복성의 문제를 극복하면서 보호막으로서도 충분한 역할을 하는 호막 형성 방법의 개발이 필요하게 되었다.Therefore, it is necessary to develop a foil film formation method which can solve the problem of the protective film forming method as described above, that is, serve as a protective film while overcoming the problem of poor step coverage.
전술한 바와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 심한 단차를 갖는 하부층에 형성되면서, 단차피복성이 우수하고, 또한 보호막으로서의 역할을 충분히 할 수 있는 반도체 장치의 보호막 형성 방법을 제공함을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention devised to solve the problems described above provides a method of forming a protective film for a semiconductor device, which is formed in a lower layer having a severe step and is excellent in step coverage and can function as a protective film. The purpose.
도 1A내지 도1C는 종래의 반도체 장치의 보호막 형성 방법을 나타내는 공정 단면도,1A to 1C are cross-sectional views illustrating a method of forming a protective film of a conventional semiconductor device;
도 2A 내지 도2C는 본 발명의 일실시예에 따른 반도체 장치의 보호막 형성 방법을 나타내는 공정 단면도.2A to 2C are cross-sectional views illustrating a method of forming a protective film of a semiconductor device according to an embodiment of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 실리콘 기판 22 : 제1절연막21 silicon substrate 22 first insulating film
23 : 제2절연막 24 : 장벽 금속23: second insulating film 24: barrier metal
25 : 금속층 26 : (HSiO3/2)n막25 metal layer 26 (HSiO3 / 2) n film
27 : 질화막27: nitride film
상기와 같은 목적을 달성하기 위하여 본 발명의 반도체 장치의 제조 방법은, 하부 전도막을 구비하는 하부층상에 상부 전도막을 형성하는 단계; 전체 구조 상부에 매립 특성이 우수한 제1보호막을 형성하는 단계; 및 전체 구조 상부에 질화막을 포함하는 제2보호막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a semiconductor device of the present invention includes: forming an upper conductive film on a lower layer having a lower conductive film; Forming a first passivation layer having excellent embedding characteristics on the entire structure; And forming a second protective film including a nitride film on the entire structure.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
먼저, 도2A에 도시된 바와 같이, 실리콘 기판(21)상에 내부 배선층을 감싸는 제1절연막(22)을 형성하고, 제2절연막으로 BPSG막(23)을 형성하여 평탄화 공정을 행한다.First, as shown in FIG. 2A, the first insulating film 22 surrounding the internal wiring layer is formed on the silicon substrate 21, and the BPSG film 23 is formed as the second insulating film to perform the planarization process.
다음으로 도2B에 도시된 바와 같이, 전체 구조 상부에 장벽 금속층(24)과 금속층(25)을 적층한 후 식각 공정하여 금속선을 패터닝한다.Next, as shown in FIG. 2B, the barrier metal layer 24 and the metal layer 25 are stacked on the entire structure, and the metal lines are patterned by etching.
마지막으로, 도2C에 도시된 바와 같이, 전체 구조 상부에 매립 특성이 우수한 평탄화막으로 (HSiO3/2)n막(26)을 도포하고, 그 상부에 최종 보호막으로 실리콘 질화막(Si3N4, 27)을 형성한다. 여기서 (HSiO3/2)n막(26)의 도포 조건은 소자의 단차 차이에 따라 차이가 나지만 약 3000Å 내지 4000Å의 두께로 하며, 도포 후에는 150/200/350℃의 온도로 각각 1분씩 베이크 공정을 실시한다. 베이크 공정은 표면 위에 대기중 수분이 흡착되는 것을 방지하기 위하여 질소 가스 분위기에서 공정한다.Finally, as shown in FIG. 2C, the (HSiO3 / 2) n film 26 is applied to the top of the entire structure as a planarization film having excellent embedding characteristics, and the silicon nitride film (Si 3 N 4 , 27). Here, the application conditions of the (HSiO3 / 2) n film 26 are different depending on the difference in the steps of the device, but the thickness is about 3000 kPa to 4000 kPa. Is carried out. The baking process is carried out in a nitrogen gas atmosphere to prevent adsorption of moisture in the atmosphere on the surface.
평탄화막으로 사용된 (HSiO3/2)n막(26)은 단차피복성이 우수하여 금속 배선막 간극의 매립이 충분하게 이루어지고 있다. 그러나 (HSiO3/2)n물질은 Si-H결합 구조를 가짐으로서 금속선의 부식을 유발한다. 이러한 것을 방지하기 위하여 400℃내지 420℃의 온도로 큐어링 공정을 실시한다.The (HSiO3 / 2) n film 26 used as the planarization film has excellent step coverage and is sufficiently filled with metal wiring film gaps. However, the (HSiO3 / 2) n material has a Si—H bond structure, causing corrosion of metal wires. In order to prevent this, the curing process is carried out at a temperature of 400 ℃ to 420 ℃.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the present invention without departing from the technical idea. It will be evident to those who have knowledge of.
상기와 같이 이루어지는 본 발명은, 반도체 장치의 보호막 형성 공정시, 저온의 플라즈마 화학 기상 증착 방법을 이용하는 보호막 형성시 (HSiO3/2)n과 질화막을 이용하여 기존의 불량한 단차피복성을 극복할 수 있고, 핀홀 및 크랙 등에 의한 하부 금속 배선층의 부식을 방지한다.The present invention made as described above can overcome the conventional poor step coverage by using (HSiO3 / 2) n and a nitride film when forming a protective film using a low-temperature plasma chemical vapor deposition method during a protective film forming process of a semiconductor device. And corrosion of the lower metal wiring layer due to pinholes and cracks.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970029699A KR100265360B1 (en) | 1997-06-30 | 1997-06-30 | Method for forming passivation layer in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970029699A KR100265360B1 (en) | 1997-06-30 | 1997-06-30 | Method for forming passivation layer in semiconductor device |
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| Publication Number | Publication Date |
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| KR19990005501A true KR19990005501A (en) | 1999-01-25 |
| KR100265360B1 KR100265360B1 (en) | 2000-10-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019970029699A KR100265360B1 (en) | 1997-06-30 | 1997-06-30 | Method for forming passivation layer in semiconductor device |
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| KR950034423A (en) * | 1994-05-10 | 1995-12-28 | 문정환 | Method of forming protective film for semiconductor device |
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