KR19990004590A - Method for manufacturing dual gate electrode of CMOS field effect transistor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gate electrode of a CMOS FET sharing an N-type and a P-type gate, wherein the N-type and P-type gates are patterned by doping impurities with one ion implantation and one diffusion process. Since the number of photo processes is small, the process is simple, and defects caused by contamination can be prevented, thereby improving process yield and reliability of device operation.

Description

Method for manufacturing dual gate electrode of CMOS field effect transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of manufacturing a dual gate electrode of a CMOS metal field semiconductor transistor (hereinafter referred to as a CMOS FET), in particular one ion implantation and one impurities The present invention relates to a method of manufacturing a dual gate electrode of a CMOS FET which can improve the process yield and the reliability of device operation by simplifying a process by doping a polycrystalline silicon layer which becomes a dual gate electrode by diffusion and preventing contamination.

In general, the most important function of the transistor constituting the semiconductor circuit is the current driving capability, and the channel width of the MOS FET is adjusted in consideration of this. The most widely used MOS FET uses a polysilicon layer doped with impurities as a gate electrode, and a diffusion region doped with impurities on a semiconductor substrate is used as a source / drain electrode.

In a conventional CMOS FET structure, a PMOS FET using an N + doped polycrystalline silicon gate electrode has a buried channel. Under such circumstances, a threshold voltage is different between an NMOS FET and a PMOS FET having a channel formed on a surface thereof. Therefore, various limiting factors affect the design and manufacture of the device.

In other words, the CMOS FET using the dual gate electrode according to the prior art forms a dual gate electrode by ion implanting N-type and P-type impurities twice, so that the process is complicated by performing two photographic processes. There is a high possibility of contamination, there is a problem that the process yield and the reliability of device operation is inferior.

The present invention is to solve the above problems, an object of the present invention is to form a dual gate electrode by only one photo process to simplify the process and lower the possibility of contamination can improve the process yield and device operation reliability The present invention provides a method for manufacturing a semiconductor device.

1A to 1D are diagrams illustrating a process of manufacturing a dual gate electrode of a CMOS field effect transistor according to an embodiment of the present invention.

2A to 2C are diagrams illustrating a process of manufacturing a dual gate electrode of a CMOS field effect transistor according to another exemplary embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

10: semiconductor substrate 12: device isolation oxide film

14 gate oxide film 16 polycrystalline silicon layer

16A: N + area 16B: P + area

18 photosensitive film pattern 20 insulating film

22A: N-type gate electrode 22B: P-type gate electrode

24: diffusion barrier

A feature of the semiconductor device manufacturing method according to the present invention for achieving the above object is the step of forming a device isolation oxide film on the portion of the semiconductor substrate is intended as the device isolation region, and on the remaining portion of the semiconductor substrate Forming a gate oxide film; forming a polycrystalline silicon layer on the entire surface of the structure; and injecting a first conductive impurity into a portion of the polycrystalline silicon layer Forming a conductive region, forming an insulating layer containing a second conductive impurity on the entire surface of the structure, and heat treating the insulating layer to diffuse the second conductive impurity onto the semiconductor substrate. Forming a conductive region, removing the insulating layer, and patterning the polycrystalline silicon layer to form first and second conductive gate electrodes. It consists in a step.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

1A to 1D are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

First, an element isolation thin film 12 is formed on a portion of the semiconductor substrate 10 that is intended as an isolation region, and a gate oxide layer 14 is formed on the remaining portion of the semiconductor substrate 10. An undoped polycrystalline silicon layer 16 serving as a gate electrode is formed on the entire surface of the film, and a photosensitive film pattern 18 is formed on a portion of the polycrystalline silicon layer 16 that will serve as a P-type gate electrode. (See FIG. 1A).

Then, an N-type impurity is ion-implanted on the exposed polycrystalline silicon layer 16, and the N + region 16A is formed by doping with a sufficient doping amount in consideration of the degree of neutralization due to the subsequent P-type impurity diffusion. (See FIG. 1B).

Thereafter, the photoresist pattern 18 is removed and an insulating layer containing P-type impurities, such as B, on the entire surface of the structure, for example B. Si. Glass (hereinafter referred to as BSG). The insulating film 20 is formed of B. P. S. paper (hereinafter referred to as BPSG), and the P-type impurities in the insulating film 20 are heat-treated to form a polycrystalline silicon layer. (16) Diffuses to form the P + region 16B. (See FIG. 1C).

Then, the insulating film 20 is removed, the impurities are activated, and the polycrystalline silicon layer 16 is patterned to form the N-type and P-type gate electrodes 22A, 22B. (See FIG. 1D).

2A to 2C are manufacturing process diagrams of a semiconductor device according to another embodiment of the present invention.

First, the processes up to FIG. 1B are sequentially performed, and the device isolation oxide film 12, the gate oxide film 14, the polycrystalline silicon layer 16, the photoresist pattern 18, and the N + region 16A are formed on the semiconductor substrate 10. ), And a diffusion barrier film 24 for preventing impurity diffusion on the entire surface of the structure is formed of a nitride film, an oxide film, or the like, and then the photosensitive film pattern 18 and the diffusion barrier film 254 on the portion intended as the P gate are formed. ) Is removed by a lift off method to form a diffusion barrier 24 pattern on the N + region 16A. (See Figure 2A).

Then, an insulating material containing P-type impurities, for example, BSG BPSG, is formed on the entire surface of the structure, and the P-type impurities are formed inside the polycrystalline silicon layer 16 by heat-treating the insulating film 20. Diffused to form a P + region 16B. (See FIG. 2B).

Thereafter, the insulating film 20 and the diffusion barrier film 24 are removed and the polycrystalline silicon layer 16 is patterned to form N-type and P-type gate electrodes 22A, 22B. (See FIG. 2C).

As described above, in the method of manufacturing a semiconductor device according to the present invention, the ion implantation process for forming the N-type and P-type gates in a CMOS FET sharing the N-type and P-type gates includes one ion implantation and one diffusion process. Since it is formed by doping with a patterning process, the number of photo process steps is small, the process is simple, there is an advantage that can improve the process yield and the reliability of the device operation by preventing the occurrence of defects due to contamination.

Claims (5)

Forming a device isolation oxide film on a portion of the semiconductor substrate, which is intended to be a device isolation region, forming a gate oxide film on the remaining portion of the semiconductor substrate, and forming a polycrystalline silicon layer on the entire surface of the structure. Forming a first conductive type region by implanting a first conductive type impurity into a portion of the polycrystalline silicon layer that is intended to be a gate electrode of a first conductive type, and forming a second conductive type impurity on the entire surface of the structure Forming an insulating layer comprising: forming a second conductive region by heat-treating the insulating layer to diffuse a second conductive impurity onto a semiconductor substrate, removing the insulating layer, and A method for manufacturing a dual gate electrode of a CMOS FET comprising the step of patterning a silicon layer to form first and second conductive gate electrodes. The method of manufacturing a dual gate electrode of a CMOS FET according to claim 1, wherein said first and second conductivity types are opposite conductivity types, respectively, being P and N type. The method of claim 1, wherein the insulating layer is BSG or BPSG. The method of manufacturing a dual gate electrode of a CMOS FET according to claim 1, further comprising forming a diffusion barrier pattern on the draft typical region after forming the first conductive region and subsequent steps thereof. The method of manufacturing a dual gate electrode of a CMOS FET according to claim 4, wherein the diffusion barrier is formed of a nitride film or an oxide film.