KR19990004426A - Contact formation method of semiconductor device - Google Patents
Contact formation method of semiconductor device Download PDFInfo
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- KR19990004426A KR19990004426A KR1019970028517A KR19970028517A KR19990004426A KR 19990004426 A KR19990004426 A KR 19990004426A KR 1019970028517 A KR1019970028517 A KR 1019970028517A KR 19970028517 A KR19970028517 A KR 19970028517A KR 19990004426 A KR19990004426 A KR 19990004426A
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- semiconductor device
- contact
- junction
- silicide
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- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 27
- 238000007796 conventional method Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 버팅 콘택(butting contact) 형성 방법에 관한 것임.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming butting contact of a semiconductor device.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
반도체 소자의 콘택 형성 공정중 상부 전도층에서 게이트 폴리실리콘(gate poly-Si)층을 거쳐 접합부로 버팅 콘택을 형성할 때, 필드 산화막(field oxide)에 필드 컷팅(field cutting) 현상이 발생하여 콘택의 누설전류 원인이 됨.When the butt contact is formed from the upper conductive layer through the gate poly-Si layer to the junction during the contact forming process of the semiconductor device, a field cutting phenomenon occurs in the field oxide layer. Cause leakage current.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
게이트 폴리실리콘층을 폴리실리콘층과 실리사이드(silicide)층으로 이중 증착함으로써 실리사이드층이 폴리실리콘층과 접합부를 직접 연결하게 하고, 버팅 콘택이 실리사이드층 위에 형성되도록 하여 필드 컷팅 현상을 제거함.By double depositing the gate polysilicon layer with the polysilicon layer and the silicide layer, the silicide layer is directly connected to the polysilicon layer and the junction, and the butting contact is formed on the silicide layer to eliminate the field cutting phenomenon.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 소자의 콘택 형성 공정.Contact formation process of a semiconductor device.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자에서 층간 인터커넥션(interconnection)으로 사용되는 버팅 콘택(butting contact) 형성에 관한 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to the formation of butting contacts used as interlayer interconnections in semiconductor devices.
도 1은 종래의 방법에 의해 형성된 반도체 소자의 콘택 문제점을 설명하기 위해 도시한 단면도로써, 제 2 폴리실리콘층(17)에서 게이트로 쓰이는 제 1 폴리실리콘(14)을 거쳐 접합부(15)와 연결되는 버팅 콘택을 형성한 소자의 단면도이다.1 is a cross-sectional view illustrating a contact problem of a semiconductor device formed by a conventional method, and is connected to the junction part 15 via a first polysilicon 14 used as a gate in the second polysilicon layer 17. It is sectional drawing of the element which formed the butting contact.
제조 공정 단계에서의 오정렬(misalign)등으로 인하여 필드 산화막(13) 위에 증착된 제 1 폴리실리콘층(14)이 필드 산화막(13)을 충분히 덮어주지 못할 경우, 산화막(16)을 식각하여 콘택 홀을 형성할 때 제 1 폴리실리콘층(14)의 바깥으로 돌출된 필드 산화막(13)도 같이 식각되는 필드 컷팅(field cutting;A) 현상이 발생된다. 따라서 필드 산화막(13) 하부의 실리콘 기판(11)이 드러남으로 인하여 접합부(15)에 바이어스(bias)가 걸릴 경우 이곳으로 누설 전류가 흐르게 된다.When the first polysilicon layer 14 deposited on the field oxide layer 13 does not sufficiently cover the field oxide layer 13 due to misalignment during the manufacturing process step, the oxide layer 16 is etched to etch the contact hole. When forming the film, a field cutting (A) phenomenon in which the field oxide film 13 protruding out of the first polysilicon layer 14 is also etched is generated. Therefore, when the silicon substrate 11 under the field oxide film 13 is exposed, a leakage current flows to the junction 15 when the bias is applied.
한편 필드 컷팅(A)을 방지하기 위하여 제 1 폴리실리콘층(14)을 접합부(15)쪽으로 늘려줄 경우에는 콘택 저항이 높아져서 역시 소자의 특성을 떨어뜨리게 된다.On the other hand, when the first polysilicon layer 14 is extended toward the junction 15 in order to prevent the field cut (A), the contact resistance is increased to deteriorate the characteristics of the device.
따라서 본 발명은 필드 컷팅 현상을 방지하여 콘택 특성을 향상시키는데 그 목적이 있다.Therefore, an object of the present invention is to improve the contact characteristics by preventing the field cutting phenomenon.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 콘택 형성 방법은, 반도체 기판상에 게이트 산화막, 필드 산화막 및 제 1 전도층을 순차로 형성하고 선택된 영역을 상기 실리콘 기판이 노출되도록 식각하는 단계와, 상기 노출된 실리콘 기판에 이온을 주입하여 접합부를 형성하고, 전체 구조 상부에 실리사이드층을 두껍게 증착한 후 패터닝하되, 게이트 형성 부위의 패터닝 및 필드 산화막이 충분히 덮힘으로써 실리사이드층을 접합부와 전기적으로 연결시키는 필드 산화막 부위의 패터닝을 실시하는 단계와, 상기 실리사이드 패턴을 포함하는 전체 구조 상부에 산화막을 증착하고 선택된 영역을 식각하여 버팅 콘택 홀을 형성한 후 버팅 콘택 홀을 포함하는 전체 구조 상부에 제 2 전도층을 증착하는 단계를 포함하여 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a contact for a semiconductor device, comprising sequentially forming a gate oxide film, a field oxide film, and a first conductive layer on a semiconductor substrate, and etching the selected region to expose the silicon substrate. And forming a junction by implanting ions into the exposed silicon substrate, depositing a thick silicide layer on the entire structure, and then patterning the same, and electrically covering the silicide layer with the junction by patterning the gate forming part and sufficiently covering the field oxide layer Patterning the field oxide layer to be connected, depositing an oxide layer on the entire structure including the silicide pattern, etching the selected region to form a butting contact hole, and then forming a butting contact hole on the entire structure including the butting contact hole. And depositing a conductive layer. The.
도 1은 종래의 방법에 의해 형성된 반도체 소자의 콘택 문제점을 설명하기 위해 도시한 단면도.1 is a cross-sectional view for explaining a contact problem of a semiconductor device formed by a conventional method.
도 2(a) 내지 도 2(d)는 본 발명에 의한 반도체 소자의 콘택 형성 방법을 설명하기 위해 순차적으로 도시한 단면도.2 (a) to 2 (d) are cross-sectional views sequentially shown to explain a method for forming a contact of a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of the drawings
11 및 21 : 실리콘 기판 12 및 22 : 게이트 산화막11 and 21: silicon substrate 12 and 22: gate oxide film
13 및 23 : 필드 산화막 14 및 24 : 제 1 폴리실리콘층13 and 23: field oxide films 14 and 24: first polysilicon layer
15, 25 및 25A : 접합부 16 및 27 : 산화막15, 25 and 25A: junctions 16 and 27: oxide film
17 및 28 : 제 2 폴리실리콘층 26 : 실리사이드층17 and 28: second polysilicon layer 26: silicide layer
첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.
도 2(a) 내지 도 2(d)는 본 발명에 의한 반도체 소자의 콘택 방법을 설명하기 위해 순차적으로 도시한 단면도이다.2 (a) to 2 (d) are cross-sectional views sequentially illustrating a method of contacting a semiconductor device according to the present invention.
도 2(a)는 실리콘 기판(21)상에 게이트 산화막(22), 필드 산화막(23) 및 제 1 폴리실리콘층(24)을 순차로 형성하고 버팅 콘택이 형성될 영역을 실리콘 기판(21)이 노출되도록 식각한 단면도이다. 이 때 제 1 폴리실리콘층(24)은 500 Å 정도로 얇게 증착하고, 노출된 실리콘 기판(21)에는 n-이온을 주입하여 접합부(25)를 형성한다.FIG. 2 (a) shows a region in which the gate oxide film 22, the field oxide film 23, and the first polysilicon layer 24 are sequentially formed on the silicon substrate 21 and the butting contact is formed in the silicon substrate 21. This is a sectional view etched to be exposed. At this time, the first polysilicon layer 24 is deposited thinly to about 500 kPa, and n − ions are implanted into the exposed silicon substrate 21 to form the junction 25.
형성된 접합부(25)를 포함하는 전체구조 상부에 약 2,000 Å 정도로 두껍게 실리사이드층(silicide;26)를 증착한 후, 도 2(b)와 같이 패터닝을 실시한다. 즉 게이트 형성 부위의 패터닝 및 필드 산화막(23)이 충분히 덮힘으로써 실리사이드층을(26) 접합부(25)와 전기적으로 연결 시키는 필드 산화막 부위의 패터닝을 실시한다.After depositing a thick layer of silicide 26 on the entire structure including the formed junction part 25 to about 2,000 mW, patterning is performed as shown in FIG. That is, patterning of the gate formation site and the field oxide film 23 are sufficiently covered to pattern the field oxide film site that electrically connects the silicide layer 26 to the junction 25.
도 2(c)는 트랜지스터 형성 공정 후 산화막(27)을 증착하여 층간 절연을 시키고, 선택된 영역을 식각하여 버팅 콘택 홀을 형성한 단면도이다. 따라서 실리사이드층(26)이 제 1 폴리실리콘층(24)과 트랜지스터 형성 과정에서 완성된 접합부(25A)를 직접 연결하게 하고, 버팅 콘택이 실리사이드층(26) 위에 형성됨으로써 필드 컷팅 현상이 일어나지 않음을 알 수 있다.FIG. 2C is a cross-sectional view of depositing an oxide layer 27 to perform interlayer insulation and etching a selected region to form a butting contact hole after a transistor forming process. Therefore, the silicide layer 26 directly connects the first polysilicon layer 24 and the junction 25A completed during the transistor formation process, and the butting contact is formed on the silicide layer 26 so that no field cutting phenomenon occurs. Able to know.
도 2(d)와 같이, 형성된 콘택 홀을 포함하는 전체 구조 상부에 제 2 폴리실리콘층(28)을 증착하여 최종 버팅 콘택을 형성한다.As illustrated in FIG. 2 (d), the second polysilicon layer 28 is deposited on the entire structure including the formed contact hole to form a final butting contact.
상술한 바와 같이 본 발명에 의하면, 실리사이드층을 이용하여 콘택 저항의 감소 없이 필드 컷팅 현상을 제거하므로, 누설 전류등이 문제되었던 소자의 콘택 특성이 향상된다.As described above, according to the present invention, since the field cutting phenomenon is eliminated without reducing the contact resistance by using the silicide layer, the contact characteristics of the device in which leakage current or the like has been improved is improved.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970028517A KR100451042B1 (en) | 1997-06-27 | 1997-06-27 | Method for forming contact of semiconductor device to eliminate leakage current of contact |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970028517A KR100451042B1 (en) | 1997-06-27 | 1997-06-27 | Method for forming contact of semiconductor device to eliminate leakage current of contact |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990004426A true KR19990004426A (en) | 1999-01-15 |
| KR100451042B1 KR100451042B1 (en) | 2004-12-03 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970028517A KR100451042B1 (en) | 1997-06-27 | 1997-06-27 | Method for forming contact of semiconductor device to eliminate leakage current of contact |
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| Country | Link |
|---|---|
| KR (1) | KR100451042B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100325600B1 (en) * | 1999-05-11 | 2002-02-25 | 황인길 | a manufacturing method of contact holes of semiconductor devices |
| KR100428627B1 (en) * | 2002-07-25 | 2004-04-28 | 아남반도체 주식회사 | Method for manufacturing MOS transistor |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4873204A (en) * | 1984-06-15 | 1989-10-10 | Hewlett-Packard Company | Method for making silicide interconnection structures for integrated circuit devices |
| US4994402A (en) * | 1987-06-26 | 1991-02-19 | Hewlett-Packard Company | Method of fabricating a coplanar, self-aligned contact structure in a semiconductor device |
| JPH0541378A (en) * | 1991-03-15 | 1993-02-19 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JPH08213342A (en) * | 1995-02-06 | 1996-08-20 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| US5612239A (en) * | 1995-08-24 | 1997-03-18 | United Microelectronics Corporation | Use of oxide spacers formed by liquid phase deposition |
| US5605853A (en) * | 1996-05-28 | 1997-02-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of making a semiconductor device having 4 transistor SRAM and floating gate memory cells |
-
1997
- 1997-06-27 KR KR1019970028517A patent/KR100451042B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100325600B1 (en) * | 1999-05-11 | 2002-02-25 | 황인길 | a manufacturing method of contact holes of semiconductor devices |
| KR100428627B1 (en) * | 2002-07-25 | 2004-04-28 | 아남반도체 주식회사 | Method for manufacturing MOS transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100451042B1 (en) | 2004-12-03 |
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