KR19990003582U - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
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- KR19990003582U KR19990003582U KR2019970017180U KR19970017180U KR19990003582U KR 19990003582 U KR19990003582 U KR 19990003582U KR 2019970017180 U KR2019970017180 U KR 2019970017180U KR 19970017180 U KR19970017180 U KR 19970017180U KR 19990003582 U KR19990003582 U KR 19990003582U
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- South Korea
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- substrate
- package
- chip
- present
- semiconductor package
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 15
- 238000005538 encapsulation Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 238000000465 moulding Methods 0.000 description 7
- 239000003795 chemical substances by application Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000009966 trimming Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
1. 청구범위에 기재된 고안이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
본 고안은 반도체 패캐이지에 관한 것으로서, 특히 소자의 전기적 특성이 향상되고 소자의 크기를 최소화할 수 있는 반도체 패캐이지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly to a semiconductor package that can improve the electrical characteristics of the device and minimize the size of the device.
2. 고안이 해결하고자 하는 기술적 과제2. The technical problem to be solved by the invention
본 고안은 전기적 특성이 향상되고 제품의 두께를 얇게하여 실장할수 있는 반도체 기판의 제공을 목적으로 한다.The object of the present invention is to provide a semiconductor substrate which can be mounted by improving electrical characteristics and thinning a product.
3. 고안의 해결의 요지3. Summary of solution
본 고안은 기판의 비아 홀에 금속패턴을 형성하여 비아 홀을 외부리드로 사용한것을 요지로 한다.The present invention is to form a metal pattern in the via hole of the substrate to use the via hole as an external lead.
4. 고안의 중요한 용도4. Important uses of the devise
본 고안은 반도체 패캐이지의 소형화에 이용된다.The present invention is used for downsizing the semiconductor package.
Description
본 고안은 반도체 패캐이지에 관한 것으로서, 특히 그 크기를 최소화할 수 있는 반도체 패캐이지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly to a semiconductor package capable of minimizing its size.
일반적으로 반도체 소자는 외부와의 신호경로로서 리드(lead) 또는 볼(ball)을 이용하게 되며, 리드를 이용한 일반적인 패캐이지와 볼을 이용한 패캐이지를 설명하면 다음과 같다.In general, a semiconductor device uses a lead or a ball as a signal path to the outside, and a general package using a lead and a package using a ball will be described as follows.
도 1(a)는 리드 프레임을 이용하여 구성된 일반적인 패캐이지의 단면도로서, 패캐이지를 제조하기 위해서는 먼저 리드 프레임의 패드(11) 표면에 칩(10)을 부착시킨 후 칩(10)과 리드 프레임의 각 내측 리드(12a)를 와이어(13)로 연결하는 와이어 본딩(wire bonding) 공정을 실시하게 된다. 와이어 본딩 공정 이후 리드 프레임 상하부에 성형제(14)를 형성하는 몰딩공정을 실시하게 되며, 몰딩공정 이후, 성형제(14) 외부로 노출된 외측리드(12b)에 대한 트리밍(trimming) 공정 및 기판으로의 실장을 위하여 외측 리드(12b)를 절곡하는 포밍(forming)공정을 실시하므로서 패캐이지가 완성된다.FIG. 1A is a cross-sectional view of a general package constructed using a lead frame. In order to manufacture the package, the chip 10 is first attached to the surface of the pad 11 of the lead frame, and then the chip 10 and the lead frame. A wire bonding process of connecting each inner lead 12a of the wire 13 to the wire 13 is performed. After the wire bonding process, a molding process is performed to form the molding agent 14 above and below the lead frame. After the molding process, a trimming process and a substrate for the outer lead 12b exposed to the outside of the molding agent 14 are performed. The package is completed by performing a forming step of bending the outer lead 12b for mounting in the furnace.
도 1(b)는 일반적인 볼 그리드 어레이 패캐이지(ball grid array package; 이하 편의상 BGA 패캐이지라 칭함)의 단면도로서, 다수의 리드들이 칩과 회로기판과의 전기적 연결기능을 수행하는 패캐이지와는 달리 패턴 형성된 기판(1)상에 칩(2)을 부착시킨 후 칩(2)과 기판(1)상의 접점을 와이어(3)로 연결하는 구성을 가지고 있다. 그리고 기판(1) 하부에는 패턴의 각 접점과 연결되어 전기적으로 통하는 다수의 솔더 볼(4)이 고정되어 있으며, 기판(1)의 상부에는 칩(2) 및 와이어(3)의 보호를 위한 성형제(5)가 몰딩된다.FIG. 1 (b) is a cross-sectional view of a general ball grid array package (hereinafter referred to as BGA package for convenience), and is a package in which a plurality of leads perform an electrical connection between a chip and a circuit board. Otherwise, the chip 2 is attached to the patterned substrate 1, and then the chip 2 and the contact point on the substrate 1 are connected by a wire 3. In addition, a plurality of solder balls 4 are fixed to the lower part of the substrate 1 and connected to each contact of the pattern, and formed on the upper part of the substrate 1 to protect the chip 2 and the wire 3. (5) is molded.
그러나 상기와 같은 구성을 갖는 패캐이지는 리드 프레임과 몰딩 컴파운드로 형성된 패캐이지(도 1a) 또는 높이로 인하여 패캐이지의 두께를 낮추는데 제약적 요소가 된다. 또한 와이어(13 및 3)의 높이로 인하여 성형제(14 및 5)는 어느정도 높이를 가져야 한다. 따라서 기판에 실장했을때 시스템의 크기를 크게 하는 요소가 되고, 소형 경박화(輕薄化)에 적합하지 않다.However, the package having the above configuration is a limiting factor in reducing the thickness of the package due to the height of the package (FIG. 1A) or the height formed by the lead frame and the molding compound. Also, due to the height of the wires 13 and 3, the molding agents 14 and 5 must have some height. Therefore, when mounted on a substrate, it becomes an element to increase the size of the system, and is not suitable for small size and thinness.
본 고안은 상기와 같은 문제점을 해결하기 위한 것으로서, 전기적 특성이 향상되고 제품의 두께를 얇게하여 실장할수 있는 반도체 패캐이지의 제공을 목적으로 한다.The present invention is to solve the above problems, it is an object of the present invention to provide a semiconductor package that can be mounted by improving the electrical properties and thin product thickness.
이러한 본 고안의 목적은 비아 홀에 금속패턴이 형성된 기판과, 기판의 상부에 부착되며 상부에 범프를 가지는 칩과, 칩의 범프와 기판의 패턴을 연결하는 와이어와, 칩의 상부에 형성되는 인캡슐레이션과, 인캡슐레이션과 기판이 접하는 부분에 형성되는 댐으로 구성된 것을 특징으로 하는 패캐이지에 의하여 달성된다.The object of the present invention is a substrate having a metal pattern formed in a via hole, a chip attached to the upper part of the substrate and having a bump on the top, a wire connecting the bump and the pattern of the chip on the substrate, and the phosphor formed on the upper part of the chip. The encapsulation is achieved by a package comprising a dam formed in a portion where the encapsulation is in contact with the substrate.
도 1(a) 및 도 1(b)는 일반적인 패캐이지의 단면도.1 (a) and 1 (b) are cross-sectional views of a typical package.
도 2는 본 고안에 이용된 반도체 기판의 정면도.2 is a front view of a semiconductor substrate used in the present invention.
도 3(a) 및 (b) 그리고 (c)는 본 고안의 기판이 완성되는 단개를 나타낸 평면도.Figure 3 (a) and (b) and (c) is a plan view showing a single stage that the substrate of the present invention is completed.
도 4(a) 및 (b)는 본 고안에 의하여 완성된 패캐이지의 단면도.Figure 4 (a) and (b) is a cross-sectional view of the package completed by the present invention.
도 4(c)는 본 고안의 일부 사시도.Figure 4 (c) is a partial perspective view of the present invention.
(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
1,1a: 기판1b: 바이어 홀1,1a: substrate 1b: via hole
1c: 상부 구리 패턴1d: 하부 구리 패턴1c: upper copper pattern 1d: lower copper pattern
2,2a,10: 칩11: 패드2,2a, 10: chip 11: pad
12a: 내측리드12b: 외측리드12a: inner lead 12b: outer lead
13: 와이어14: 성형제13: wire 14: molding agent
15:인캡슐레이션(encapsulation)17: 댐(dam)15: encapsulation 17: dam
30: 포지셔닝 홀(positioning hole)32: 라우팅 라인30: positioning hole 32: routing line
이하 첨부된 도면을 참조하여 본 고안을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2은 본 고안에 이용된 반도체 기판의 정면도로서, 기판(1a)의 구조는 일반적인 기판의 구조와 동일하나, 회로패턴이 형성될 상부 구리(copper)패턴(1c)의 두께는 1/2 oz(17.51 m)로 형성하고, 하부 구리 패턴(1d)의 두께는 1-2oz(35-701 m)로 형성한다. 이렇게 양면으로 형성한 상부 구리 패턴(1c)과 하부 구리 패턴(1d)의 두께는 일반적인 기판보다 두껍게 형성된다. 구리 패턴을 두껍게 형성한 이유는 패캐이지를 실장할 경우에 이부분을 외부리드로 이용하기 위한 것이다. 상기와 같이 상 하부에 구리 패턴을 형성한 다음에는 상부에 회로 패턴을 형성한다.FIG. 2 is a front view of a semiconductor substrate used in the present invention. The structure of the substrate 1a is the same as that of a general substrate, but the thickness of the upper copper pattern 1c on which the circuit pattern is to be formed is 1/2 oz. (17.51 m) and the thickness of the lower copper pattern (1d) is 1-2 oz (35-701) m). The thickness of the upper copper pattern 1c and the lower copper pattern 1d formed on both sides is thicker than that of a general substrate. The reason why the copper pattern is formed thick is to use this part as an external lead when mounting the package. After forming a copper pattern on the upper and lower as described above, a circuit pattern is formed on the upper.
도 3a는 기판상에 비아 홀(1b)을 보이는 도면이고, 도 3b는 밀링가공한 도면이고, 도 3c는 도 3b를 라우팅(roughting)한 도면으로서, 우선 기판상에 비아(via)홀(1b)을 가공한다. 이후 비아 홀(1b)과 비아 홀(1b: via hole)사이를 밀링(milling)가공하여 하나로 연결하고, 연결된 비아 홀에 금속으로 도금한다. 도금 이 완료된 후에는 개별 제품화 시에 필요한 절단라인을 기판에 라우팅 한다. 라우팅이라 함은 패캐이지를 완성한 후에, 기판상에 실장하기 위하여 패캐이지의 크기에 맞추어 라우팅 라인(32:절단라인)을 형성하는 것이다. 절단라인은 손으로도 손쉽게 절단될 정도로 형성되어 있다. 포지셔닝 홀(30:positioning hole)은 각 유니트의 모서리에 위치하여 트리밍이 용이하게 한다. 또한 마스크 얼라이먼트 등 위치 설정에 필요하다.FIG. 3A is a view showing a via hole 1b on a substrate, FIG. 3B is a milled view, and FIG. 3C is a roughing view of FIG. 3B. First, a via hole 1b is formed on a substrate. ). Thereafter, a milling process is performed between the via hole 1b and the via hole 1b to connect them to each other, and the connected via hole is plated with metal. After the plating is completed, the cutting lines required for individual production are routed to the substrate. Routing is to form a routing line 32 (cutting line) in accordance with the size of the package for mounting on the substrate after completing the package. The cutting line is formed to be easily cut by hand. Positioning holes 30 are located at the corners of each unit to facilitate trimming. It is also necessary for positioning such as mask alignment.
도 4a는 도 3c와 같이 형성된 기판상에 접착제를 이용하여 칩(2a)을 부착하고 칩(2a)의 상부에 범프(2b)를 형성한다. 이후 범프(2b)와 기판 상부의 구리 패턴(1c)을 와이어(13)를 이용하여 연결하는 와이어 본딩 공정을 실시하게 된다. 와이어 본딩 공정 이후 칩(2a)과 와이어(13)를 보호하기 위하여 인캡슐레이션(15: encapsulation)을 형성하게 된다. 인캡슐레이션을 형성한 이후 인캡슐레이션과 기판이 접하는 부분에 댐(17:dam)을 형성하여 인캡슐레이션이 누설되는 것을 방지하게 된다.FIG. 4A attaches the chip 2a using an adhesive on a substrate formed as shown in FIG. 3C and forms bumps 2b on top of the chip 2a. Thereafter, a wire bonding process of connecting the bumps 2b and the copper pattern 1c on the substrate using the wires 13 is performed. After the wire bonding process, encapsulation 15 is formed to protect the chip 2a and the wire 13. After the encapsulation is formed, a dam 17 is formed at a portion where the encapsulation is in contact with the substrate, thereby preventing the encapsulation from leaking.
도 4b는 도 4a의 A부분의 확대도로서, 와이어(13)가 기판상부 카퍼패턴(1c)과 연결되어 있으며, 상부 구리 패턴(1c)과 비아 홀(1b)에 형성되어 있는 금속패턴 그리고 기판 하부 구리 패턴(1d)이 모두 연결되어 전기적으로 통하고 있음을 보여주고 있다. 여기서, 비아 홀(1b)에 형성되어 있는 금속 패턴은 칩과 외부가 전기적으로 통하게하는 외부리드의 역활을 하고 있음을 보여주고 있다. 도 4c는 본 고안의 일부 사시도로서, 인캡슐레이션(15), 댐(17), 바이어 홀(1b)에 형성된 금속패턴을 도시하고 있다.4B is an enlarged view of portion A of FIG. 4A, wherein the wire 13 is connected to the upper copper pattern 1c and the metal pattern formed on the upper copper pattern 1c and the via hole 1b and the substrate. It is shown that the lower copper patterns 1d are all connected and in electrical communication. Here, it is shown that the metal pattern formed in the via hole 1b serves as an external lead through which the chip and the outside are electrically connected. FIG. 4C is a partial perspective view of the present invention and shows a metal pattern formed in the encapsulation 15, the dam 17, and the via hole 1b.
상술한 바와 같이 본 고안은 기판상의 비아 홀에 금속패턴을 형성하여 외부리드로 사용하므로서, 다음과 같은 우수한 효과가 있다.As described above, the present invention forms a metal pattern in a via hole on a substrate and uses the metal as an external lead, thereby providing the following excellent effects.
첫째, 외부리드를 사용하지 않으므로 신호경로가 짧아지게 되고 전기적 특성이 향상된다. 또한 양면기판을 사용하므로서 원가절감의 효과를 거둘수 있다.First, since the external lead is not used, the signal path is shortened and the electrical characteristics are improved. In addition, cost reduction can be achieved by using double-sided board.
둘째, 패캐이지의 두께를 얇게하므로서 패캐이지의 박형화에 기여한다. 그리고 본 고안은 칩사이즈 패캐이지(chip size package)의 제작에 용이하다.Second, it contributes to the thinning of the package by thinning the thickness of the package. And the present invention is easy to manufacture a chip size package (chip size package).
Claims (3)
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| KR2019970017180U KR200179418Y1 (en) | 1997-06-30 | 1997-06-30 | Semiconductor package |
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| KR101366418B1 (en) * | 2012-04-25 | 2014-02-25 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device |
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| KR101366418B1 (en) * | 2012-04-25 | 2014-02-25 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device |
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