KR100413475B1 - film adhesive having circuit pattern and multi chip module semiconductor package using the same - Google Patents
film adhesive having circuit pattern and multi chip module semiconductor package using the same Download PDFInfo
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- KR100413475B1 KR100413475B1 KR10-2000-0062864A KR20000062864A KR100413475B1 KR 100413475 B1 KR100413475 B1 KR 100413475B1 KR 20000062864 A KR20000062864 A KR 20000062864A KR 100413475 B1 KR100413475 B1 KR 100413475B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
본 발명은 필름어드헤시브에 배선 기능을 추가하여 멀티칩 모듈 반도체패키지의 제조시 전기적 연결이 쉽게 수행될 수 있도록 하는 한편, 멀티칩 모듈 패키지의 신뢰성을 향상시킬 수 있도록 한 것이다.The present invention allows the electrical connection to be easily performed during the manufacture of the multichip module semiconductor package by adding a wiring function to the film-adhesive, and to improve the reliability of the multichip module package.
이를 위해, 본 발명은 양면테이프로 된 베이스층(700)과, 상기 베이스층(700) 상부에 부착되고 내부에 전기적 배선이 형성되며 표면으로는 상기 내부 배선과 연결된 외부접속단자인 핑거부(701)(702)가 노출되는 회로필름층(710)과, 상기 회로필름층(710)의 핑거부(701)(702)가 노출되는 윈도우를 가지며 상기 회로필름층(710) 상부에 부착되는 어드헤시브층(720)으로 구성된 회로패턴을 갖는 필름어드헤시브가 제공되는 한편, 베이스를 이루는 회로기판(1)과, 상기 회로기판(1) 상부에 직접 부착되는 제1칩(2)과, 상기 제1칩(2)의 상면에 부착되며 회로패턴이 형성되어 상기 제2칩(3)의 본딩패드와 회로기판(1)의 접속단자를 전기적으로 연결시킴에 있어 가교(架橋)역할을 하는 회로패터닝 필름어드헤시브(7)와, 상기 회로패터닝 필름어드헤시브(7) 상면에 부착되는 제2칩(3)과, 상기 제2칩(3)과 회로패터닝 필름어드헤시브(7) 사이 및 상기 회로패터닝 필름어드헤시브(7)와 회로기판(1) 사이를 전기적으로 연결하는 한편 제1칩(2)과 회로기판(1) 사이를 전기적으로 연결하는 전도성 연결부재와, 상기 전도성 연결부재와 회로패터닝 필름어드헤시브(7), 그리고 제1칩(2) 및 제2칩(3)이 보호되도록 봉지하는 몰드바디(5)가 구비됨을 특징으로 하는 멀티칩 모듈 반도체패키지가 제공된다.To this end, the present invention is a base layer 700 made of a double-sided tape, and the finger portion 701 which is attached to the base layer 700 and formed inside the electrical wiring and the external connection terminal connected to the internal wiring on the surface. 702 has a circuit film layer 710 is exposed, the finger 701, 702 of the circuit film layer 710 has a window that is exposed and is attached to the upper portion of the circuit film layer 710 While the film-adhesive having a circuit pattern composed of the sheave layer 720 is provided, a base circuit board 1, a first chip 2 directly attached to the upper circuit board 1, and The circuit is attached to the upper surface of the first chip 2 and the circuit pattern is formed to serve as a bridge in the electrical connection between the bonding pad of the second chip 3 and the connection terminal of the circuit board (1) Patterning film advice (7) and the second chip (3) attached to the upper surface of the circuit patterning film advice (7) And the first chip 2 while electrically connecting between the second chip 3 and the circuit patterning film assist 7 and between the circuit patterning film assist 7 and the circuit board 1. A conductive connecting member electrically connecting between the circuit board 1 and the conductive connecting member, the circuit patterning film assist 7, and the first chip 2 and the second chip 3 to be protected. There is provided a multi-chip module semiconductor package, characterized in that the mold body (5) is provided.
Description
본 발명은 회로패턴을 갖는 필름어드헤시브 및 이를 이용한 멀티칩 모듈 반도체패키지에 관한 것으로서, 더욱 상세하게는 필름어드헤시브에 전기적 연결이 가능하도록 배선 기능을 추가하여 멀티칩 모듈 반도체패키지의 제조시 전기적 연결이 쉽게 수행될 수 있도록 하는 한편, 멀티칩 모듈 패키지의 신뢰성을 향상시킬 수 있도록 한 것이다.The present invention relates to a film-adhesive having a circuit pattern and a multi-chip module semiconductor package using the same, and more particularly, in the manufacture of a multi-chip module semiconductor package by adding a wiring function to enable an electrical connection to the film-adhesive. The electrical connection can be easily performed while improving the reliability of the multichip module package.
일반적으로, 멀티칩 모듈(Multi-chip Moudle: 이하, "엠시엠"이라 한다) 반도체패키지는 하나의 패키지내에 2개 이상의 반도체칩을 적층하여 내장하도록 한 것이다.In general, a multi-chip module (hereinafter referred to as an "EMC") semiconductor package is to stack two or more semiconductor chips in one package.
도 1 및 도 2는 종래의 멀티칩 모듈 패키지를 나타낸 것으로서, 베이스를 이루는 회로기판(1)과, 상기 회로기판(1) 상부에 직접 부착되는 제1칩(2)과, 상기 제1칩(2)의 본딩패드면을 벗어난 일측에 부착되며 상기 제1칩(2)보다 작은 사이즈의 제2칩(3)과, 상기 제1칩(2)의 본딩패드와 회로기판(1)의 해당 접속단자를 각각 전기적으로 연결함과 더불어 상기 제2칩(3)의 본딩패드와 회로기판(1)의 해당 접속단자를 각각 전기적으로 연결하는 골드와이어(4a)(4b)와, 상기 제1칩(2)과 제2칩(3) 및 골드와이어(4a)(4b)를 외부로부터 보호되도록 봉지하는 몰드바디(5)로 이루어지게 된다.1 and 2 illustrate a conventional multichip module package, wherein a base circuit board 1, a first chip 2 directly attached to an upper portion of the circuit board 1, and the first chip ( 2) a second chip 3 having a smaller size than the first chip 2, a bonding pad of the first chip 2, and a corresponding connection of the circuit board 1 Gold wires 4a and 4b that electrically connect the terminals, and electrically connect the bonding pads of the second chip 3 and the corresponding connection terminals of the circuit board 1, respectively, and the first chip. 2) and the mold body 5 for encapsulating the second chip 3 and the gold wires 4a and 4b to be protected from the outside.
한편, 상기 제1칩(2)과 제2칩(3) 사이에는 접착제층(800)과 필름층(810)으로 이루어진 다이 어태치용 필름 어드헤시브(8)가 구비된다.On the other hand, between the first chip 2 and the second chip 3 is provided with a film attach 8 for die attach consisting of an adhesive layer 800 and the film layer 810.
그러나, 이와 같은 종래의 멀티칩 모듈 패키지는 도 1 및 도 2에 나타낸 바와 같이, 제1칩(2)의 본딩패드와 회로기판(1)의 접속단자와는 거리가 그다지 멀지않아 와이어(4b)로 본딩하는데 별문제가 없지만, 제2칩(3)의 본딩패드와 회로기판(1)의 접속단자를 와이어(4a)로 본딩하는데는 많은 문제점이 있었다.However, such a conventional multi-chip module package, as shown in Figs. 1 and 2, the distance between the bonding pad of the first chip 2 and the connection terminal of the circuit board 1 is not far from the wire 4b. Although there is no problem in bonding with the wires, there are many problems in bonding the connection pads of the bonding pads of the second chip 3 and the circuit board 1 with the wires 4a.
즉, 제2칩(3)의 경우, 도 1 및 도 2에 있어서 도면상 우측의 본딩패드와 회로기판(1)의 접속단자 사이의 거리(D1)가 짧아, 와이어 본딩시 와이어(4a)와 제1칩(2)의 에지부분과의 간섭을 피하기 위해 와이어 루프가 급하게 휘어져야 하므로 인해, 와이어 본딩이 어려워지고 와이어(4a) 및 본딩 부위에 많은 응력이 걸리게 되므로 본딩 신뢰성이 저하되는 문제점이 있었다.That is, in the case of the second chip 3, the distance D 1 between the bonding pad on the right side of the drawing and the connection terminal of the circuit board 1 is short in FIGS. 1 and 2, so that the wire 4a at the time of wire bonding. Since the wire loop must be bent rapidly to avoid interference with the edge portion of the first chip 2, the wire bonding becomes difficult and a lot of stress is applied to the wire 4a and the bonding portion, which reduces the bonding reliability. there was.
또한, 상기한 바와는 달리, 도 1 및 도 2를 통해 알 수 있듯이, 제2칩(3) 좌측의 본딩패드와 회로기판(1)의 접속단자 사이의 거리(D2)는 상당히 먼 거리여서, 와이어 본딩 수행후에 와이어 처짐(sagging)이 발생하기 쉬우며 몰딩 수행시, 몰딩콤파운드에 의한 와이어 휩쓸림(sweeping) 현상이 발생할 우려가 커지게 된다.1 and 2, the distance D 2 between the bonding pad on the left side of the second chip 3 and the connection terminal of the circuit board 1 is considerably distant. After wire bonding, wire sagging is likely to occur, and a wire sweeping phenomenon caused by the molding compound increases when molding is performed.
뿐만 아니라, 와이어(4a)(4b)간의 간격이 좁아 전기적 단락(short-circuit)이 발생할 우려가 있는 등 많은 문제점 있었다.In addition, the gap between the wires 4a and 4b is narrow, which may cause electrical short-circuit.
본 발명은 상기한 제반 문제점을 해결하기 위한 것으로서, 멀티칩 모듈 반도체패키지 제조시 칩간 접착에만 적용되던 필름어드헤시브의 구조를 새롭게 개선하여 상부에 적층되는 반도체칩과 회로기판과의 전기적 연결이 용이하게 이루어질 수 있도록 하므로써 멀티칩 모듈 반도체패키지의 제조가 용이하게 이루어지도록 하는데 그 목적이 있다.The present invention is to solve the above-mentioned problems, it is easy to electrically connect the semiconductor chip and the circuit board stacked on top by newly improving the structure of the film-adhesive which was only applied to the chip-to-chip adhesion when manufacturing the multi-chip module semiconductor package The purpose of the present invention is to facilitate the manufacture of a multichip module semiconductor package.
도 1은 종래의 멀티칩 모듈 반도체패키지를 종단면도1 is a vertical cross-sectional view of a conventional multi-chip module semiconductor package
도 2는 도 1의 몰딩전 상태를 나타낸 사시도2 is a perspective view showing a state before molding of FIG.
도 3은 도 1의 멀티칩 모듈 반도체패키지에 적용된 종래의 필름어드헤시브 구조를 나타낸 종단면도3 is a longitudinal cross-sectional view showing a conventional film-adhesive structure applied to the multi-chip module semiconductor package of FIG.
도 4는 본 발명의 회로패터닝 필름어드헤시브를 나타낸 평면도Figure 4 is a plan view showing a circuit patterning film advice of the present invention
도 5는 도 4의 Ⅰ-Ⅰ선을 따른 종단면도5 is a longitudinal cross-sectional view along the line II of FIG. 4.
도 6은 본 발명의 회로패터닝 필름어드헤시브가 적용된 멀티칩 모듈 반도체패키지를 나타낸 종단면도Figure 6 is a longitudinal cross-sectional view showing a multi-chip module semiconductor package to which the circuit patterning film advanced of the present invention is applied;
도 7은 도 6의 몰딩전 상태를 나타낸 사시도7 is a perspective view showing a state before molding of FIG.
도 8은 본 발명의 다른 실시예를 나타낸 것으로서, 다른 형태로 회로가 패터닝된 필름어드헤시브를 이용한 멀티칩 모듈 반도체패키지의 와이어 본딩후 상태를 나타낸 평면도8 is a view showing another embodiment of the present invention, and a plan view showing a state after wire bonding of a multichip module semiconductor package using a film-adhesive patterned circuit in another form.
도 9는 본 발명의 또 다른 실시예를 나타낸 것으로서, 또 다른 형태로 회로가 패터닝된 필름어드헤시브를 이용한 멀티칩 모듈 반도체패키지의 와이어 본딩후상태를 나타낸 평면도9 is a view showing another embodiment of the present invention, and in another form, a plan view illustrating a post-bonding state of a multichip module semiconductor package using a film-adhesive patterned circuit.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1:회로기판 2:제1칩1: Circuit board 2: First chip
3:제2칩 4a,4b,4c,4d:와이어3: second chip 4a, 4b, 4c, 4d: wire
5:몰드바디 6:솔더볼5: Molded body 6: Solder ball
7:회로패터닝 어드헤시브 700:베이스층7: Circuit patterning aggressive 700: base layer
701:핑거부 710:회로필름층701: finger 710: circuit film layer
720:어드헤시브층720: Advance Floor
9:회로패턴9: circuit pattern
상기한 목적을 달성하기 위해, 본 발명은 양면테이프로 된 베이스층과, 상기 베이스층 상부에 부착되고 내부에 전기적 배선이 형성되며 표면으로는 상기 내부 배선에 의해 상호 연결된 두개의 외부접속단자인 핑거부가 노출되는 회로필름층과, 상기 회로필름층의 핑거부가 각각 노출되는 윈도우 영역과, 칩 본딩영역이 구비되며 상기 회로필름층 상부에 부착되는 어드헤시브층으로 구성됨을 특징으로 하는 회로패턴을 갖는 필름어드헤시브 제공된다.In order to achieve the above object, the present invention is a finger which is a base layer made of a double-sided tape, and two external connection terminals attached to the base layer and formed inside the electrical wiring and interconnected by the internal wiring on the surface. The circuit pattern layer has an additional exposed circuit film, a window region in which the finger portion of the circuit film layer is exposed, and a chip bonding region, and an additive layer formed on the circuit film layer. Film Advice is provided.
한편, 상기한 목적을 달성하기 위한 본 발명의 다른 형태는, 베이스를 이루는 회로기판과, 상기 회로기판 상부에 직접 부착되는 제1칩과, 상기 제1칩의 상면에 부착되며 회로패턴이 형성되어 상기 제2칩의 본딩패드와 회로기판의 접속단자를 전기적으로 연결시킴에 있어 가교(架橋)역할을 하는 회로패터닝 필름어드헤시브와, 상기 회로패터닝 어드헤시브 상면에 부착되는 제2칩과, 상기 제2칩과 회로패터닝 필름어드헤시브 사이를 전기적으로 연결함과 더불어 상기 회로패터닝 필름어드헤시브와 회로기판 사이를 전기적으로 연결하는 한편 제1칩과 회로기판을 전기적으로 연결하는 전도성 연결부재와, 상기 전도성 연결부재와 회로패터닝 필름어드헤시브 그리고 제1칩 및 제2칩이 보호되도록 봉지하는 몰드바디가 구비됨을 특징으로 하는 멀티칩 모듈 반도체패키지가 제공된다.On the other hand, another aspect of the present invention for achieving the above object, a base circuit board, a first chip directly attached to the upper portion of the circuit board, and a circuit pattern is formed on the upper surface of the first chip is formed A circuit patterning film assistant serving as a bridge in electrically connecting the bonding pads of the second chip and the connection terminal of the circuit board, a second chip attached to an upper surface of the circuit patterning assistant; A conductive connection member which electrically connects the second chip and the circuit patterning film advice, and electrically connects the circuit patterning film assistant and the circuit board, while electrically connecting the first chip and the circuit board. And a mold body for sealing the conductive connection member, the circuit patterning film advice, and the first chip and the second chip to be protected. The conductor package is provided.
이하, 본 발명의 실시예들을 첨부도면 도 4 내지 도 9를 참조하여 상세히 설명하면 다음과 같다.Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 4 to 9.
도 4는 본 발명의 회로패터닝 필름어드헤시브를 나타낸 평면도이고, 도 5는 도 4의 Ⅰ-Ⅰ선을 따른 종단면도로서, 본 발명의 회로패터닝 필름어드헤시브(7)는 양면테이프로 된 베이스층(700)과, 상기 베이스층(700) 상부에 부착되고 내부에 전기적 배선이 형성되며 표면으로는 상기 내부 배선과 연결된 외부접속단자인 핑거부(701)(702)가 노출되는 회로필름층(710)과, 상기 회로필름층(710)의 핑거부가 노출되는 윈도우 영역과 반도체 칩 본딩 영역을 동시에 가지며 상기 회로필름층(710) 상부에 부착되는 어드헤시브층(720)으로 구성된다.4 is a plan view showing the circuit patterning film assistant of the present invention, Figure 5 is a longitudinal cross-sectional view along the line I-I of Figure 4, the circuit patterning film assistant 7 of the present invention is a double-sided tape A circuit film layer which is attached to the base layer 700 and the base layer 700 and has an electrical wiring formed therein, and has the surface of the finger parts 701 and 702 which are external connection terminals connected to the internal wiring. 710, an active layer 720 having a window region and a semiconductor chip bonding region at which a finger portion of the circuit film layer 710 is exposed and attached to an upper portion of the circuit film layer 710.
한편, 도 6은 본 발명의 회로패터닝 필름어드헤시브가 적용된 멀티칩 모듈 반도체패키지를 나타낸 종단면도이고, 도 7은 도 6의 몰딩전 상태를 나타낸 사시도로서, 상기한 회로패터닝 필름어드헤시브(7)를 이용하여 제조되는 멀티칩 모듈 반도체패키지는, 베이스를 이루는 회로기판(1)과, 상기 회로기판(1) 상부에 직접 부착되는 제1칩(2)과, 상기 제1칩(2)의 상면에 부착되며 회로패턴이 형성되어 상기 제2칩(3)의 본딩패드와 회로기판(1)의 접속단자를 전기적으로 연결시킴에 있어 가교(架橋)역할을 하는 회로패터닝 필름어드헤시브(7)와, 상기 회로패터닝 필름어드헤시브(7) 상면에 부착되는 제2칩(3)과, 상기 제2칩(3)과 회로패터닝 필름어드헤시브(7) 사이 및 상기 회로패터닝 필름어드헤시브(7)와 회로기판(1) 사이를 전기적으로 연결하는 한편 제1칩(2)과 회로기판(1) 사이를 전기적으로 연결하는 전도성 연결부재와, 상기 전도성 연결부재와 회로패터닝 필름어드헤시브(7), 그리고 제1칩(2) 및 제2칩(3)이 보호되도록 봉지하는 몰드바디(5)가 구비된다.6 is a longitudinal cross-sectional view illustrating a multi-chip module semiconductor package to which the circuit patterning film assistant of the present invention is applied, and FIG. 7 is a perspective view showing a state before molding of FIG. 6, wherein the circuit patterning film assistant ( The multi-chip module semiconductor package manufactured using 7) includes a base circuit board 1, a first chip 2 directly attached to an upper portion of the circuit board 1, and the first chip 2 The circuit patterning film adhering is formed on the upper surface of the circuit pattern and serves as a bridge in electrically connecting the bonding pad of the second chip 3 and the connection terminal of the circuit board 1. 7), between the second chip 3 attached to an upper surface of the circuit patterning film assist 7, between the second chip 3 and the circuit patterning film assist 7 and the circuit patterning film ad The first chip 2 and the circuit are electrically connected between the receive 7 and the circuit board 1. A conductive connecting member electrically connecting between the plates 1, a mold encapsulating the conductive connecting member and the circuit patterning film assist 7, and the first chip 2 and the second chip 3 to be protected. The body 5 is provided.
이 때, 상기 회로패터닝 필름어드헤시브(7)의 윈도우(W) 영역 내에는 와이어 본딩시 골드와이어와의 접합성을 향상시키기 위해 전도성이 우수한 Au 또는 Ag가 플레이팅된다.In this case, Au or Ag having excellent conductivity is plated in the window W region of the circuit patterning film assist 7 to improve bonding with gold wires during wire bonding.
그리고, 상기 회로패터닝 필름어드헤시브(7)의 회로패턴(9)은 전도성이 좋은 Cu 재질로 이루어짐이 바람직하다.In addition, the circuit pattern 9 of the circuit patterning film advice 7 is preferably made of Cu material having good conductivity.
또한, 상기 회로기판(1) 하부에는 마더보드(도시는 생략함)에의 실장을 위한 솔더볼(6)등의 외부접속단자가 구비된다.In addition, the lower portion of the circuit board 1 is provided with an external connection terminal such as a solder ball 6 for mounting on a motherboard (not shown).
이와 같이 구성된 본 발명의 제1실시예에 따른 멀티칩 모듈 반도체패키지의 제조 과정 및 작용은 다음과 같다.The manufacturing process and operation of the multichip module semiconductor package according to the first embodiment of the present invention configured as described above are as follows.
먼저, 베이스를 이루는 회로기판(1) 상에 제1칩(2)이 부착되고, 이어 상기제1칩(2) 상부면 상에 회로패터닝 필름어드헤시브(7)가 부착된다.First, a first chip 2 is attached to a circuit board 1 forming a base, and a circuit patterning film assist 7 is attached to an upper surface of the first chip 2.
이 때, 상기 회로패터닝 필름어드헤시브(7)는 제1칩(2)의 본딩패드와의 간섭이 방지되도록 상기 본딩패드 내측 영역에 부착된다.In this case, the circuit patterning film advice 7 is attached to the bonding pad inner region to prevent interference with the bonding pad of the first chip 2.
한편, 제1칩(2) 상면에 회로패터닝 필름어드헤시브(7)가 부착된 후에는, 와이어 본딩을 수행하게 되는데, 상기 제1칩(2)의 본딩패드는 전도성 연결부재인 골드와이어(4b)에 의해 회로기판(1)상에 형성된 소정의 접속단자에 각각 전기적으로 연결되고, 상기 제1칩(2) 상부면상에 부착된 제2칩(3)의 본딩패드는 회로패터닝 필름어드헤시브(7)를 매개로 하여 골드와이어(4a)(4c)(4d)에 의해 회로기판(1)상에 형성된 소정의 접속단자에 각각 전기적으로 연결된다.On the other hand, after the circuit patterning film advice 7 is attached to the upper surface of the first chip 2, wire bonding is performed. The bonding pad of the first chip 2 is a gold wire, which is a conductive connection member. The bonding pads of the second chips 3 electrically connected to predetermined connection terminals respectively formed on the circuit board 1 by 4b) and attached to the upper surface of the first chips 2 are connected to the circuit patterning film. The gold wires 4a, 4c and 4d are electrically connected to predetermined connection terminals formed on the circuit board 1 via the sheaves 7 respectively.
즉, 도 6 및 도 7을 통해 알 수 있듯이, 본 발명에 따르면, 제2칩(3)의 본딩패드중 도면상 좌측에 형성된 본딩패드는 우선 골드와이어(4c)에 의해 제1칩(2) 상면에 부착된 회로패터닝 필름어드헤시브(7)의 일측 접속단자에 1차적으로 접속된다.6 and 7, according to the present invention, among the bonding pads of the second chip 3, the bonding pads formed on the left side of the drawing are first formed by the gold wires 4c. It is primarily connected to one connection terminal of the circuit patterning film passive 7 attached to the upper surface.
한편, 상기 회로패터닝 필름어드헤시브(7)의 일측 접속단자는 내부에 형성된 회로패턴(9)에 의해 상기 일측 접속단자로부터 이격된 위치의 타측 접속단자와 전기적으로 연결된 상태이다.On the other hand, one connection terminal of the circuit patterning film advanced 7 is electrically connected to the other connection terminal at a position spaced apart from the one connection terminal by a circuit pattern 9 formed therein.
따라서, 제1칩(2)의 도면상 좌측에 위치한 본딩패드와 회로패터닝 필름어드헤시브(7)의 일측 접속단자 사이를 골드와이어(4c)로써 와이어 본딩하여 1차적으로 접속시킨 후에는, 상기 회로패터닝 필름어드헤시브(7)의 타측 접속단자와 회로기판(1)의 접속단자 사이를 골드와이어(4d)로 연결하여 2차적으로 접속시키게되며, 이로 인해 제2칩(2)의 도면상 좌측에 위치한 본딩패드는 회로기판(1)에 전기적으로 연결된다.Therefore, after the wire bonding between the bonding pad located on the left side of the drawing of the first chip 2 and the one end connection terminal of the circuit patterning film advanced 7 by gold wire 4c, the primary connection is performed. The second connection between the connection terminal on the other side of the circuit patterning film receive 7 and the connection terminal of the circuit board 1 is connected by gold wire 4d to thereby make a secondary connection. The bonding pad located on the left side is electrically connected to the circuit board 1.
이 때, 상기 회로패터닝 필름어드헤시브(7)의 윈도우(W) 영역 내에는 전도성이 우수한 Au 또는 Ag가 플레이팅되므로 와이어 본딩시 골드와이어와의 접합성이 향상된다.At this time, since Au or Ag having excellent conductivity is plated in the window W region of the circuit patterning film assist 7, the bonding with the gold wire is improved during wire bonding.
한편, 제2칩(3)의 본딩패드중 도면상(도 6 및 도 7 참조) 우측에 형성된 본딩패드는 골드와이어(4a)에 의해 회로기판(1)에 전기적으로 연결된다.Meanwhile, the bonding pads formed on the right side of the bonding pads of the second chip 3 (see FIGS. 6 and 7) are electrically connected to the circuit board 1 by the gold wires 4a.
이와 같이 구성된 본 발명에 따르면, 회로패터닝 필름어드헤시브(7)의 형태 및 그 내부에 형성되는 회로패턴(9)의 변경을 통해 제2칩(3)과 회로기판(1)과의 와이어링을 거리에 관계없이 자유롭고 다양하게 변화시킬 수 있게 된다.According to the present invention configured as described above, the wiring between the second chip 3 and the circuit board 1 by changing the shape of the circuit patterning film assist 7 and the circuit pattern 9 formed therein. It can be changed freely and variously regardless of distance.
그리고, 본 발명에서는 회로패터닝 필름어드헤시브(7)의 형태 및 회로패턴(9)의 변경을 통해, 이웃하는 와이어간의 간격을 멀어지게 할 수 있음으로 인해 와이어 스윕핑(sweeping)에 의한 단락 발생을 방지할 수 있게 된다.In addition, in the present invention, a short circuit may occur due to wire sweeping because the distance between neighboring wires may be increased by changing the shape of the circuit patterning film assist 7 and the circuit pattern 9. Can be prevented.
이와 더불어, 본 발명에서는, 제2칩(3)의 본딩패드와 회로기판(1)의 접속단자 사이의 거리가 멀더라도 회로패터닝 필름어드헤시브(7)를 매개로하여 와이어링(wiring) 경로를 최적의 위치로 변화시키므로써, 제2칩(3)과 회로기판(1)을 와이어의 처짐없이 전기적으로 연결 가능하게 된다.In addition, in the present invention, even if the distance between the bonding pad of the second chip 3 and the connection terminal of the circuit board 1 is long, a wiring path is provided through the circuit patterning film assist 7. By changing the to the optimum position, the second chip 3 and the circuit board 1 can be electrically connected without sagging the wire.
또한, 본 발명의 실시예에 따른 멀티칩 모듈 패키지에서는 와이어 루프가 급격하게 휘지 않고 완만한 곡선을 그리게 되므로 인해 와이어 및 본딩 부위에 작용하는 응력이 줄어들게 되어 본딩 신뢰성이 향상된다.In addition, in the multi-chip module package according to the embodiment of the present invention, since the wire loops are not abruptly curved and draw a gentle curve, stress applied to the wire and the bonding part is reduced, thereby improving the bonding reliability.
한편, 도 8은 본 발명의 다른 실시예를 나타낸 것으로서, 다른 형태로 회로가 패터닝된 필름어드헤시브를 이용한 멀티칩 모듈 반도체패키지의 와이어 본딩후 상태를 나타낸 평면도이다.8 is a plan view illustrating a state after wire bonding of a multichip module semiconductor package using a film-adhesive patterned circuit in another form as another embodiment of the present invention.
이 경우는 회로패터닝 필름어드헤시브(7)의 회로패턴이 제2칩의 둘레를 따라 4방향에 모두 배치되는 경우이다.This case is a case where the circuit patterns of the circuit patterning film assist 7 are arranged in all four directions along the circumference of the second chip.
이 때, 상기 회로패터닝 필름어드헤시브(7)에는 그라운딩 본딩용 배선 및 캐패시터 장착용 배선을 둘 수 있다.In this case, the circuit patterning film advanced 7 may include a ground bonding wire and a capacitor mounting wire.
한편, 도 9는 본 발명의 또 다른 실시예를 나타낸 것으로서, 이 경우에는 제1칩(2) 상에 복수개의 제2칩이 한꺼번에 탑재될 수 있도록 회로패터닝 필름어드헤시브(7)의 회로를 패터닝한 경우이다.Meanwhile, FIG. 9 shows another embodiment of the present invention. In this case, the circuit of the circuit patterning film assist 7 is mounted so that a plurality of second chips can be mounted on the first chip 2 at once. Patterned case.
즉, 각 제2칩이 안착되는 위치 주변에 회로패터닝 필름어드헤시브(7)의 핑거부(701)가 위치하도록 하여 1차적으로 제2칩(3)의 본딩패드와 회로패터닝 필름어드헤시브(7)의 윈도우 영역을 통해 노출되는 핑거부(701)와의 전기적 연결이 이루어진 후, 다시 상기 회로패터닝 필름어드헤시브(7)의 핑거부(702)와 회로기판과의 연결이 이루어지도록 한다.That is, the bonding part and the circuit patterning film assistant of the second chip 3 are primarily positioned so that the finger portion 701 of the circuit patterning film advice 7 is positioned around the position where each second chip is seated. After the electrical connection is made with the finger portion 701 exposed through the window region of (7), the connection between the finger portion 702 of the circuit patterning film-adhesive 7 and the circuit board is made again.
이상에서와 같이, 본 발명은 멀티칩 모듈 반도체패키지 제조시 칩간 접착에만 적용되던 필름어드헤시브의 구조를 새롭게 개선하여 상부에 적층되는 반도체칩과 회로기판과의 전기적 연결이 용이하게 이루어질 수 있도록 한 것이다.As described above, the present invention is to improve the structure of the film-adhesive which was only applied to the chip-to-chip adhesion when manufacturing the multi-chip module semiconductor package to facilitate the electrical connection between the semiconductor chip and the circuit board stacked on top. will be.
이에 따라, 와이어 본딩시 와이어간의 단락 및 처짐이 방지되고, 와이어링경로 변경이 가능하며 와이어 및 본딩 부위의 응력이 저감되어 본딩 신뢰성이 향상되며, 결국 멀티칩 모듈 패키지의 기계적·전기적 신뢰성을 향상시킬 수 있게 된다.This prevents short circuits and sags between the wires during wire bonding, changes the wiring path, reduces the stress on the wires and bonding sites, and improves the bonding reliability, thereby improving the mechanical and electrical reliability of the multichip module package. It becomes possible.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0062864A KR100413475B1 (en) | 2000-10-25 | 2000-10-25 | film adhesive having circuit pattern and multi chip module semiconductor package using the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0062864A KR100413475B1 (en) | 2000-10-25 | 2000-10-25 | film adhesive having circuit pattern and multi chip module semiconductor package using the same |
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| Publication Number | Publication Date |
|---|---|
| KR20020032011A KR20020032011A (en) | 2002-05-03 |
| KR100413475B1 true KR100413475B1 (en) | 2003-12-31 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990006619A (en) * | 1998-06-03 | 1999-01-25 | 가나이 츠토무 | Semiconductor device and wiring tape for semiconductor device |
| JPH11317488A (en) * | 1998-05-01 | 1999-11-16 | Nec Corp | Semiconductor device, lead frame for the semiconductor device, and manufacture thereof |
| JP2000299429A (en) * | 1999-04-06 | 2000-10-24 | Kashin Senshin Denshi Kofun Yugenkoshi | Packaging method for tape multichip and tape multichip package structure |
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2000
- 2000-10-25 KR KR10-2000-0062864A patent/KR100413475B1/en active IP Right Grant
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11317488A (en) * | 1998-05-01 | 1999-11-16 | Nec Corp | Semiconductor device, lead frame for the semiconductor device, and manufacture thereof |
| KR19990006619A (en) * | 1998-06-03 | 1999-01-25 | 가나이 츠토무 | Semiconductor device and wiring tape for semiconductor device |
| JP2000299429A (en) * | 1999-04-06 | 2000-10-24 | Kashin Senshin Denshi Kofun Yugenkoshi | Packaging method for tape multichip and tape multichip package structure |
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| KR20020032011A (en) | 2002-05-03 |
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