KR19980702945A - Apparatus and method related to digital communication system - Google Patents

Abstract

The present invention relates to an apparatus and method for multiplexing / demultiplexing in a digital communication system using time division multiplexing. The device US comprises a switching device having a first switching means USC for the switching of data and second switching means TCU-1 and TCU-2 for multiplexing and / or demultiplexing the data. The one or more second switching means are connected to the first switching means via a terminal access link comprising a logical interface (USC-link) comprising a plurality of time slots arranged longitudinally and horizontally. The apparatus also includes means for providing a resource to an interface of a first terminal access link (USC-link), wherein two different functionalities specify a time-based designation and a resource-based designation at the interface. Is specified.

Description

Apparatus and method related to digital communication system

It is well known in a synchronous communication system to use an apparatus for multiplexing and / or demultiplexing to connect information in multiple channels destined for one communication channel and to distribute information in one communication channel destined for multiple communication channels.

US-A-4630261 shows a signal concentrator (multiplexer) including a buffer for storing messages and signaling information based on priority. In this device, the signaling information is assigned the highest priority, while the generated voice packet is given the lowest priority depending on whether a new voice packet is generated. In addition, low priority voice band data is given another priority and digital data packets are given another priority. The entry in the buffer includes a look-up table that indicates the priority level, identification, and location in the buffer. Another table contains a time recording of when a message from a particular voice source is present in the buffer. Through the controller executing the priority algorithm, the contents of the table and the sequence entries from the buffer are used to be sent to the communication channel based on the priority. Entries with the highest priority are sent according to the first-in-first-out principle, followed by entries with the lower priority.

Therefore, data is shifted out toward the common communication channel through the priority algorithm.

WO 93/25031 relates to monitoring the fill rate of elastic buffer memory in a synchronous digital communication system. The object of this invention described was to enable monitoring of the charge rate of a channel using less hardware than known systems. This is accomplished by using a time division scheme for monitoring the charge rate such that two or more channels of the same hierarchical level are monitored in time division units in a common monitoring unit for the channel.

However, none of the cited documents describe devices for multiplexing and / or demultiplexing in digital communication systems that use resources in a channel in an efficient manner. In addition, it is difficult to link the transmission system so that resources can be used efficiently. In addition, only devices designed for the transmission system can be connected.

The present invention uses a time division multiplexing scheme, provided with a switching device for multiplexing / demultiplexing of data and switching of data, in which control data and switching data are transmitted on an access link comprising a logical interface from which resources can be requested. An apparatus and method for multiplexing and / or demultiplexing channels in a digital communication system are provided.

The invention also relates to a switching device comprising means for controlling multiplexing and / or demultiplexing of a channel. The present invention relates to a communication system comprising such devices.

1 is a view schematically illustrating a terminal connection link connecting a plurality of second switching means with a first switching means.

2 is a diagram schematically illustrating a direct connection of an arbitrary transmission system to a terminal access link.

3 is a diagram for explaining a frame of a second interface.

4 is a diagram for explaining a frame of a first interface.

Fig. 5 shows the positions of allocation storage and map storage in the first and second switching means.

Fig. 6 is a diagram for explaining allocation of control timeslots.

It is an object of the present invention to provide an apparatus and method for providing optimum multiplexing and / or demultiplexing of channels in a digital communication system. It is also an object of the present invention to provide an apparatus comprising multiplexing and / or demultiplexing in a digital switching device in which resources, ie timeslots can be used as efficiently as possible.

Another object of the invention is an apparatus for multiplexing and / or demultiplexing in a digital switching system, in particular in a most efficient manner, so that different frame-based transmission systems, in particular systems other than 2Mbit / s or 1.5Mbit / s transmission systems, can be connected. It is to provide a device that uses them.

It is a further object of the present invention to provide a switching device comprising means for controlling multiplexing and / or demultiplexing such that channels or timeslots can be used in an efficient manner. It is still another object of the present invention that one or more transmission systems can be connected under optimal use of resources, and not particularly designed for a limited number of transmission systems, so that various frame-based transmission systems can be connected, thereby providing great flexibility. It is to provide a switching device provided with multiplexing / demultiplexing control means to provide.

Another object of the present invention is to provide a communication system including such a switching device.

These objects are achieved through a method and apparatus in which the first switching means for the switching of data is connected to a plurality of second switching means for the multiplexing and / or demultiplexing of the data via the first terminal connection link.

The first terminal connection link includes a first interface. The interface includes a number of timeslots arranged vertically. Connections relating to the second switching means are provided by a second terminal connection link, which may comprise a first and / or a second interface. Means are provided for providing resources to the first interface of the first terminal access link. Resources for the first functionality are specified using a reserve of resources based on the serialization of the interface, and in a second functionality, the assignment of resources is based on timeslot designation.

The objectives are also achieved through a switching device comprising multiplexing and / or demultiplexing control means for providing resources on the basis of the functionality of the objective, ie providing resources based on the intended use of the objectives. Is based on the column in which the timeslots of the interface connected to the first switching means are divided, and in the second functionality, the designation is based on the timeslot.

The interface includes a given number of timeslots (and a plurality of bits remainder) per frame for a given number of bits per timeslot in the interface. The interface is also divided into columns and rows of a given number of timeslots plus multiple extra timeslots.

In general, there are three different kinds of timeslots, namely the basic timeslot (BTS), the control timeslot (CTS) and the data timeslot (DTS). Basic timeslots are mainly used for frame control purposes and their position in the frame is fixed. Control timeslots are used to control data packets and data timeslots are used to switch data. In order to understand the information and to transmit the information on the terminal access link, the concept of a logical interface is used. There will be mappings and assignments. Assignment means defining a time slot from a interface to a data timeslot or control timeslot, and mapping means connecting one data timeslot of one interface with a data timeslot of another interface. Means for providing resources on the terminal access link, i.e. means for controlling multiplexing and / or demultiplexing, are as mentioned above the mapping and allocation provided for the first and second designations depending on the functionality of the required resources. Include functionality

The invention will be described in a non-limiting manner with reference to the accompanying drawings.

The invention is described with reference to an embodiment in which the switching device comprises in principle a switching US, which can compare two switching means. In this embodiment, the first switching means USC is responsible for the switching of data. The second switching means comprises a circuit having a plurality of single-connected units (TCUs) and is provided for multiplexing and / or demultiplexing of data. The switching device includes a switch control packet network (USC PN) used in circuits responsible for control, operation and maintenance functions and switching data. In FIG. 1, the second switching means including two terminal connection units TCU-1 and TCU-2 are connected. The first terminal connection unit TCU-1 is connected to the first switching means USC capable of forming a switching core through the first terminal connection link USC-link. Terminal connection links (TCU-1, TCU-2) are connected to each other by a second terminal connection link (TCU-link: here TCL-2). As can be clearly seen from the figure, a plurality of terminal units (TU) (n represents any suitable number) is connected to each terminal connection unit (TCU-1, TCU-2). The second terminal access link (TCU-link) used here for the connection of the terminal unit (TU) to the terminal access unit (TCU) is referred to as TCL-1. The terminal connection units TCU-1 and TCU-2 communicate with the device processor DP. For communication with the device processor DP, an internal second terminal connection link TCL-3 is used. These are for device processor connections only in the illustrated embodiment. As only schematically shown in FIG. 1, a plurality of terminal connection units can be connected to the first switching means or the switch core according to this embodiment. Although not shown in the drawings, it is also possible within the scope of the present invention that the terminal unit (TU) is directly connected to the switching core (USC). A plurality of other terminal connection units may be connected to the first terminal connection unit TCU-1 connected to the switch core USC, and the plurality of other terminal connection units may be connected to the second terminal connection link TCL as described above. It may be connected to another terminal access unit through -2). In addition, a plurality of terminal units (TUs) may be connected to each terminal connection unit (TCU) through the second terminal connection link (TCL-2) as mentioned above (not shown in the figure). Each terminal access unit (TCU) may communicate with one or more device processors (DP) via an internal TCU link (TCL-3). For example, if margins apply, there will be more than one device processor in the TCU. A transmission system may be connected to the terminal unit (TU). As schematically shown in Fig. 2, in another embodiment, the transmission system may be directly connected to the terminal access unit. The connection of the transmission system is further described later.

The terminal unit (TU) may include a device processor (not shown).

Each terminal access link (TCU-) (USC-link) includes an interface or logical interface. Through this, it is possible to understand the information and to transmit the information through the terminal connection link. The first terminal connection link (USC-link) is connected to the first switching means, i.e. in this case the switch core (USC), and in the embodiment which will be further described later including the interface and the second terminal connection link (TCU) ) Includes at least one interface which may or may not be different from the first interface according to a terminal access unit link (TCU-link: TCL-1, TCL-2 or TCL-3).

In the following, an embodiment including two specific interfaces is described. However, these are given for illustrative purposes only and many other alternatives are possible.

2 illustrates an embodiment in which a transmission system is directly connected to a terminal access unit (TCU). The TCU must be able to find out (eg, by reading) how the transmission system assigns its timeslot to the interface. Where Z represents a switch or the like. In a particular embodiment, it may be a TCU that provides a direct connection.

The two interfaces to be described are referred to herein as USI 2 and USI 4 (second and first interface), respectively. The USI 2 interface (second interface) is an 8.192 Mb / s interface containing 113 timeslots per frame and the remainder of 7 bits. USI 4 is an 184.32 Mb / s interface containing 2560 timeslots per frame. On both interfaces, there are 9 bits per timeslot. The frames of both interfaces are also divided into rows and columns. The USI 2 interface has 5 extra time slots in 12 and 9 rows and the USI 4 interface has 2 extra time slots in 284 and 9 rows. Frames of the USI 2 interface and the USI 4 interface are described in FIGS. 3 and 4, respectively. The timeslots TS are divided into three different kinds of timeslots, the basic timeslot BTS, the control timeslot CTS and the data timeslot DTS. Basic time slots (BTS) are mainly used for frame control purposes and they are arranged fixedly in a frame. That is, they have a fixed position within the frame. Control timeslots (CTSs) are used for control packets and timeslots are used for switching data. In the illustrated embodiment, the terminal access unit (TCU) is equipped with one or more device processors (DP), as described in detail later. Communication channels for a device processor (DP) include a device processor interface (DPI) that includes a device processor data interface (DPDI) and a device processor control interface (DPCI).

DPDI includes two channels: DPD and D64 (64 kbits of data). The DPCI allows the device processor to receive information about the USC PN control packet network. Transmission is through the control time slot (CTS) and also through the DPCI to the device processor. The control processor may also be in communication with the switching data network, and then communication is provided through a data time slot (DTS). This information is introduced to DPD and D64 via DPDI. DPD and D64 contain fixed channels in the interface. DPD channels are always mapped into DTSB2 timeslots and D64 channels are mapped into DTSB2 timeslots.

3 and 4, the frames of each USI 2 and USI 4 interface are shown. In the figure, the underlying timeslot is denoted by B. An unspecified field (time slot), ie an empty field, indicates that timeslots can be assigned to data timeslots (DTS) and control timeslots (CTS). In Fig. 3, the rest of 7 bits are denoted by X. As mentioned above, DPD is assigned to DTSB1 (1) and D64 is assigned to DTSB2 (2).

The hardware circuitry that determines the allocation of timeslots to the interface USI is represented by allocation storage AS. The storage stores can be accessed by the terminal for allocation setup and they can be accessed from the central processor software via the USC PN, control packet network.

Allocation and mapping are described with reference to FIG. 5. The assignment relates to defining the timeslot on the interface as a data timeslot (DTS) or control timeslot (CTS). Assignment storage (AS) is used to define timeslots in the transmission direction. In the receiving direction, data timeslots and control timeslots are distinguished by line coding, and each timeslot is coded into a datatimeslot or a control timeslot. The assignment storage AS0, AS1, AS2, AS3, ..., ASn is located in the first switching means or in the switch core USC in this embodiment. In addition, allocation storage (AS) is located in the terminal access unit (TCU), there is one allocation storage (AS) for each TCU link. In the switch core (USC), there is one allocation store for each USC link.

How timeslots are allocated in the interface (USI) depends on the category of each TCU link. The timeslots of the interfaces on the TCU link used for device processor communication are hardcoded in hardware and the assignment cannot be changed by the central processor software. The allocation of timeslots of the interfaces on the TCU link used for connection to the terminal unit (TU) is hardcoded for each terminal unit change. In general, there is a frame delay between the input and output frames. This means that the output frame USI4 on the USC-link is delayed relative to the input frame USI2 on the TCU link. The same applies to transmission in the other direction. In other words, the output frame USI2 on the TCU-link is delayed relative to the input frame USI4 on the USC-link. In general, the mapping algorithm (described in detail below), the longer the frame delay, the more resilient.

The terminal unit (TU), which terminates the transmission system and is also connected to the TCU via the TCU-link, must allocate a data time slot (DTS) to USI2 and one DTS for each traffic channel in the transmission system. If the terminal unit TU includes a device processor DP (described above), DTSB1 and / or DTSB2 must be allocated. The allocation information is maintained by the switch terminal unit, which is no longer described here. The corresponding TCU assignment store must be loaded with the same assignment and the CP-software of the TCU must query the CP software of the terminal unit (TU) for the specific assignment in order to be able to load the assignment store (AS). The CP software of the terminal access unit (TCU) determines the allocation of timeslots to the interfaces on the TCU link used for cascading with the USC link.

The assignment is the same in both directions, namely to switch core USC and from switching core USC.

The hardware circuitry that determines the mapping of timeslots of an interface is referred to herein as mapping storage (MS). The mapping store is accessed by the terminal for mapping setup. These terminals can be accessed from CP software. The connection of a data time slot (DTS) of one interface with a data time slot (DTS) of another interface can be understood as a mapping. The mapping store is located in the terminal access unit, where there are two mapping stores for each terminal access unit. One is for the switch in the link direction LX and the other is for the link in the switching direction LX. The mapping (as well as the assignment) is the same in both directions. That is, two mapping stores MS store the same information. The mapping is controlled by the CP software of the terminal access unit (TCU). All timeslots that are not mapped are assigned here as control timeslots (CTSs). In FIG. 3, it is only shown that a plurality of terminal access units (TCUs) can be connected to a switch core USC, which can include one or more expansion units EU-0, ..., EU-n. . Each expansion unit is provided with a plurality of allocation stores, for example the first expansion unit EU-0 has four allocation stores AS0, AS1, AS2 and AS3. The figure also shows that a plurality of terminal units (TU) can be connected to each terminal access unit (TCU).

The first and second switching means are described in more detail later. In the embodiment to be shown, the first switching means, denoted by the switch core USC, performs real time and real space switch operations on a column (stream) of data. The switch core USC is provided with a plurality of allocation stores AS, one for each USC inlet as described above. Assignment stores (ASs) are designed for USI 4 as described above, in the illustrated embodiment. They are owned by the USC CP-Software, but the USC CP-Software needs to retrieve the allocation information from the TCU CP-Software of In-TCU Assignment Storage (AS-LX), which determines the allocation of the interface (USI 4) to the USC link. There is. The switch core USC includes a device processor and an equipment processor (not shown) that can be accessed from the interface USI 4. If margins apply, there may be more than one; This may also apply to device processors in the TCU. Communication between these device processors and the equipment processor requires timeslots on the USC link and two underlying timeslots in the first USC link are preserved. There are hardware assignments that cannot be changed from the CP software. The device processor is mainly used for the maintenance of the switch core (USC), while the equipment process is used for the synchronization of the switching device.

The terminal connection unit (TCU), as its main function, multiplexes and / or demultiplexes the data sequence between the terminal unit (described further below) and the switch core USC. Multiplexing and / or demultiplexing is controlled by a mapping and allocation function, referred to as means or control means provided for providing resources. Such a function is mainly performed in the CP software of the terminal access unit (TCU).

The terminal connection unit (TCU) has one inlet for connecting the TCU to the preceding unit in the core direction if it is not the first terminal connection unit that is directly connected to the switch core USC. However, this inlet is designed for the first terminal access link USI 4. The number of terminal connection unit link inlets depends on the type of the terminal connection unit, that is, the TCU change. The TCU-link inlet used for cascade is designed for the first interface (USI 4), while the TCU link inlet used for access to the terminal unit (TU) is the first and / or second interface, i.e. Designed for USI 4 and / or USI 2. The TCU link inlet used for device processor communication is designed only for the second interface USI 2 in the illustrated embodiment. Each inlet includes allocation storage (AS) which determines the allocation of timeslots in the transmission direction.

The terminal access unit (TCU) is equipped with one device (or more, if necessary) processor (see Figure 1). The device processor DP is internally connected to the TCU via the USI 2 interface. The device processor of the TCU uses only the DPD channel (as described earlier in this document) and maps into DTSB1. Designation is required for each device processor. This designation is in units of timeslots described below, in accordance with the described embodiments. The data timeslots received at the TCU link are terminated in two first in, first out (FIFO) terminals of the terminal access unit. One of the FIFO memories is used for traffic timeslots and the other FIFO memory is used for DTSBs. DTSBs are for units equipped with one or more device processors as discussed above. Nevertheless, however, another FIFO memory is used for the control timeslots of the control packet network.

Data is introduced into and / or removed from the switching device via the terminal unit (TU). The switching device forms a switching structure comprising first and second switching means USC and TCU _i , _{i = 1...} N. The switching device is terminated in a switch terminal unit (not described) of two different types, one of which is support (USI 2) and the other of which is support (USI 4). The terminal unit also includes a mapping and allocation unit. The assignment of timeslots at the interface between the terminal unit and the switching device is given by the switch terminal unit circuit. If the external interface transmission system is connected to the terminal unit, the terminal unit also needs to map the external timeslot into the interface USI 2. In the mapping and allocation function, the terminal unit mapping and allocation forms a constant. That is, it is hardcoded as mentioned above. The mapping and allocation function needs to be informed about this allocation in order to be able to load the allocation storage (AS) and the mapping storage (MS) in the terminal access unit (TCU). The terminal unit may inquire about a data time slot (DTS) through both column based reservation and time slot based reservation. The vertical and time slot basis specifications are described below.

There is one switch store (not shown) per USC link. Thus, successive TSs from the USC are stored at successive locations in the switch store. The position number of the timeslot starts from the first USC link of expansion unit 0 (EU-0).

If USI 4 is used on the USC link, switchstore can store 2560TS. Each switch storage location corresponds to multiple locations. This means that the first link of EU-0 continues to do so, such as owning multiple locations from 0 to 2559, and the second link owning multiple locations from 2560 to 5119.

As soon as the mapping and assignment of timeslots to the user in the USC link is performed, we know where they are assigned to the user.

The mapping and assignment algorithm of the switching device is further described below. In a switch, mapping and assignment in principle involves three subfunctions: loading and unmapping and the assignment of assignment data. When the unit is running, mapping and loading of assignment data are performed. The mapping and allocation data is then loaded into the affected mapping store and allocation store. Mapping and allocation data release are performed when the unit is disconnected. The mapping and allocation data are released and the associated mapping store and allocation store are reloaded. Loading and unloading are not described further herein, which relates to the invention, including algorithms that are executed in the mapping and assignment data assignment subfunctions when the unit requests resources for the transmission system and / or resources for the device processor. This is because mapping and assignment data designation. The algorithm becomes active when building the mapping and allocation data that will be loaded into the mapping store and allocation store.

The mapping and allocation data designation function according to the present invention includes two algorithms for requesting resources in the terminal access link. That is, it includes the column base designation and the time slot base designation. Column-based assignment is used for traffic channels, while time slot-based assignment is used for device processor channels.

When a unit (e.g., a terminal unit (TU) makes a request for a parallel basis for a data timeslot, all columns are designated for this particular unit.) The number of designated columns depends on the number of requested data timeslots. Requesting a timeslot-based request for this timeslot designates idle timeslots or possibly reserved timeslots to specify timeslot use, within which data timeslots may be one unit or many different. Can belong to a unit.

Next, the column basis designation is further described. Column-based designation is used, for example, for the designation of data timeslots for transmission systems. According to the present invention, it is possible to handle any transmission system that can vary from 1 to 2547 64 kb / s channels, for example. The present invention is applied to a system having a 64kb / s channel. In principle, however, under the condition that a number of requirements are met, for example, the frames are synchronized and can be applied to other transmission systems under the same time.

In the embodiment described herein, the USI 4 interface is used in the USC link.

The frame of this interface contains nine timeslots that can be assigned in a column and there are 283 assignable columns. In the vertical basis designation, the USI 4 frame is divided into regions. The number of regions is given by dividing the number of requested data timeslots (DTS) by nine, i.e. by dividing the number of assignable timeslots in a column by nine. The number of columns that can be specified in the interface, ie excitation 283, is divided into the required number of regions to provide the number of columns in the region. The residual columns are then grouped together at the end of the frame, forming a residual area. As described below, if the request is not rejected, one column is designated in each region for the requesting unit.

An example is given in which a 2 Mbit / s transmission system having 32 channels is connected to a terminal unit. Since there are 32 timeslots, dividing them by 9 gives a 3.55 region. This number is rounded up to four areas.

To determine the number of columns per area, 283 columns are divided into 4 areas, resulting in 70.75 columns per area. This number is truncated to give 70 columns and 3 columns of residual area per area, where the last columns 283, 282 and 281 are provided. This number allows up to 70 2Mb / s transmission systems to be connected to the USC link.

Next, the algorithm starts searching for the first free column in the first region, then jumps to 70 columns to find the corresponding column in the second region, and so on for columns 3 and 4 as well. . If the corresponding column is occupied in 2, 3 or 4 columns, the procedure begins again. This means that the next free column is selected in the first region (region 1). The procedure is restarted because we want to create a structure of the designated column that makes the alternative and / or other designation of the column optimal and also have equidistantly positioned columns. The columns are advantageously equidistant in order to perform the column switching. If it is not possible to require equidistant columns, the first free column of each region is designated, which is referred to as the shifted column. If it is not possible to specify a shifted column, the request is rejected.

If the number of data timeslots requested (in this case) is not a multiple of 9, multiple timeslots remain. These will be assigned to control timeslots, as mentioned above. In a 2 Mb / s transmission system, four time slots assigned as control time slots are represented by four time slots by nine time slots, which are 36 timeslots and by subtracting 32 timeslots from 36 timeslots. This will be. They are then assigned to the designated column of the last region, as can be seen in FIG. Control timeslots (CTSs) are allocated in this manner for the purpose of eliminating the risk of underflow or overflow in the FIFO memory of the terminal access unit. In particular, the column designation provides an advantageous designation method at the time of mapping to storage and loading of assignment data and when the user wants to switch the completed column.

The time slot basis specification is now described in more detail. Time slot based designation is used here for a device processor channel or DP-channel having a communication channel to the device processor. The device processor interface (DPI) includes a device processor data interface (DPDI) and a device processor control interface (DPCI). The device processor data interface (DPDI) supplies two device processor channels (DPD and D64), as mentioned above.

The unit may use one or both of the channels. The DPD channel is mapped to the DTSB1 timeslot of the USI frame and D64 is mapped to the DTSB2 timeslot. If the DTSB is not used, it will be allocated as a control timeslot (CTS).

The timeslot basis designation starts at the last column, column number 283 in this embodiment described. Since 283 is a prime, column 283 will never be designated for a traffic channel except when one or 283 columns must be specified. The number of columns used for the traffic channel depends on the particular transmission system or systems that are connected. In the case of a 2 Mb / s transmission system, three columns, namely the column numbers 283, 282 and 281, will never be used for the column root designation. The timeslot-based algorithm establishes a trade-off between using the residual area, ie, the residual column, distributing the column evenly over the frame of the interface, minimizing the impact on the column-based assignment, and allowing different types of transmission systems to be identical. Responsible for being able to connect to USC links.

The timeslot-based algorithm starts by identifying which columns are assigned to timeslot units. If no column is specified as the time slot basis, column 283 is selected and the requested number of timeslots are allocated as the data timeslots. On the other hand, if the columns are designated as timeslot basis, these columns are identified and if there are enough free timeslots in any column, they are designated and assigned as data timeslots.

However, if there are not enough free timeslots, new columns are specified. The remaining area for the last connected transmission system is identified and the first free column is selected and the requested number of timeslots is assigned as a data timeslot (DTS).

However, if none of the remaining regions are free, then a calculation is made based on the number of timeslots requested for the last connected transmission system. This calculation substantially corresponds to the calculations made for columnar assignments as mentioned above. Thus, the number of timeslots requested is divided by nine to provide a number of regions and the number of columns is divided by the number of regions to provide the number of columns per region. According to the timeslot basis, the last column of the last region is identified first. If this column is occupied, the corresponding column of the second last region is identified, and so on, until a free column is found or all regions are identified. If all regions have been identified, the algorithm starts with the second last column of the last region and repeats the described procedure until a free column is found. If no free column can be found, the request is withdrawn.

According to the invention, the resources of the interface on the link connected to the switch core can be optimally used for one or more transmission systems. Today, there are only 32 and 24 channel systems (2 Mb / s and 1.5 Mb / s), but according to the present invention it is possible to connect different types of transmission systems or more transmission systems.

Claims (30)

First switching means USC for switching data, second switching means TCU _i , _{i = 1,..., N} for multiplexing and / or demultiplexing data, switching means USC, TCU; A switching device (US) including a connecting means in the form of a terminal connection link for interconnecting the TCUs, and a plurality of timeslots (TS) in which switching data of control signals are arranged vertically and horizontally; Multiplexing / demultiplexing in a digital communication system using a time division multiplex (TSM), which is transmitted on a terminal access link (TCL) comprising means for providing resources in the form of logical interfaces (USI4, USI2) and timeslots (TS) In the apparatus for multiplexing, The terminal access link (TCL) connects a plurality of second switching means (TCU; TU) with the first switching means (USC) and also includes a first terminal access link (USC-link) including a first interface (USI4). A second terminal connection link (TCU-link) for connection relating to a second switching means (TCU) comprising first and second interfaces (USI4, USI2), the interface of the first terminal connection link (USI4) And means for assigning resources for at least two different functionalities, respectively, by means of a serial-based designation at the interface and a time-slot-based designation at the interface. The apparatus of claim 1 wherein the second switching means comprises a plurality of terminal access links (TCUs). The device according to claim 2, wherein the second switching means further comprises a terminal unit (TC) connected to the terminal connection link (TCU). Apparatus according to any one of the preceding claims, characterized in that the first switching means (USC) comprise a switch core. The method according to any one of the preceding claims, wherein the second terminal connection link (TCL) comprises one or more terminal connection links (TCL-1) and second switching means (TCU) for connecting the terminal unit (TU) to the second switching means. Terminal connection link (TCL-2) for mutually interconnecting the terminals; and terminal connection link (TCL-3) for communication with the device processor (DP) internally in the second switching means (TCU) Device. Apparatus according to any one of the preceding claims, characterized in that a plurality of transmission systems are connected directly to a terminal access unit (TCU) or indirectly via a terminal unit (TU) connected to a terminal access link (TCU). The apparatus of any one of the preceding claims, wherein the resources are designated by column based designation for a first functionality related to designating timeslots for the traffic channel. The apparatus according to any one of the preceding claims, wherein the resources are designated by timeslot based designation for a device processor channel (DP-channel) related to the second functionality. Apparatus according to any one of the preceding claims, characterized in that a plurality of timeslots, denoted as BTSs, have positions arranged fixedly within the frame of the interface and are also used primarily for frame control purposes. The method of any one of the preceding claims, wherein the means for providing the resource is to be used for data switching, wherein the time slot (TS) is used for defining the data time slot (DTS) and the control time slot (CTS) used for the control packet. Apparatus characterized by comprising an assignment means. The apparatus of claim 10, wherein a data timeslot (DTS) may be requested via column rooting and / or timeslot grounding. 12. The apparatus of claim 11, wherein a column basis designation is used for a request of a data time slot (DTS) by a terminal unit (TU) connected to a transmission system. 13. A device according to claim 11 or 12, wherein the terminal unit comprises a device processor (DP) and for requesting resources for this, time slot based designation is used. 14. The frame according to any one of claims 11-13, wherein the frames of the interface (USI4) are requested to find the required number of regions for the column basis designation with the interface (USI4) used in the first terminal access link (USC-link). Divides the number of data timeslots (DTS) that are allocated into timeslots (TS) that can be assigned in a column, and the number of columns that can be specified in the interface (USI4) to provide the number of columns in a region into the required number of regions. Device which is divided into zones by dividing and one column of each zone is designated for a device of a transmission system directly connected to a terminal unit (TU) or a terminal access unit (TCU). 15. The apparatus of claim 14, wherein nine timeslots (TS) in a column are assignable and assignable to an interface on a first terminal access link (USC-link) is 283. 16. The apparatus according to claim 14 or 15, wherein the assigning means comprises an algorithm for finding equal intervals in each area, preferably starting from the first free column in the first area. 17. The apparatus of claim 16, wherein if an equal interval column cannot be specified, a first free column in each region is specified, i.e. a shifted column. The apparatus of claim 17, wherein if the equal interval column cannot be specified or the shifted column (ie, the first free column in each region) cannot be specified, the request is rejected. The method according to any one of claims 14 to 17, wherein if the number of timeslots (DTS) requested is not a multiple of the number of timeslots assignable in a column, the remaining timeslots are defined as control timeslots (CTS) according to a given scheme. Device characterized by being assigned. Apparatus according to any one of the preceding claims, wherein time slot basis designation is used for designation of a device processor channel (DP-channel). 21. The method according to claim 20, wherein in the time slot based designation, the designation starts from the last one of the vertical segments in which the frames of the interface USI4 of the first terminal access link USC are divided and if there is no column for the time slot based designation. If is not specified, the last column is selected and the requested number of timeslots are assigned as data timeslots (DTS). 21. The apparatus of claim 20, wherein if the columns are designated for timeslot basis assignment and there are a sufficient number of free timeslots within these columns, then these timeslots are designated and assigned as data timeslots (DTS). 21. The apparatus of claim 20, wherein if the columns are designated for time slot based assignment and if there are not enough idle timeslots in any of these columns, the last remaining area connected to the transmission system is examined to select the first idle column. . 21. The apparatus of claim 20, wherein if none of the columns specified by the column basis designation contain a sufficient number of free timeslots, then the assigning means calculates to find the number of columns per area, and then the last area of the last area. The columns starting from the last column are characterized in that they are identified in a discontinuous manner until the free column of the corresponding columns of each region is found. Control means for controlling multiplexing / demultiplexing of at least first and second switching means and timeslots, said connecting means being provided for interconnecting said first switching means and one or more second switching means, In the switching device for a digital communication system using a time division multiplex (TDM), the connection means includes an interface having a plurality of frames having a time slot arranged in a vertical, horizontal, The control means assigns the resource TS to the interface USI4 requested for the first functionality based on the column and the resource TS to the interface for the second functionality based on the timeslot. Device. The apparatus of claim 25, wherein the first functionality is related to resources (TS) for a traffic channel. 27. A device according to claim 25 or 26, wherein the second functionality is related to resources (TS) for the device processor inside the second switching means (TCU; TU). The first switching means of the switching device used in a digital communication system using time division multiplexing (TDM), in which resources of the interface (for example, timeslots) are arranged in a frame in which the resources are arranged vertically and horizontally, is mutually connected with the second switching means. In the method for assigning resources in the form of timeslots to the interface of the connecting means to connect, Resources are requested for a traffic channel according to the number of resources required, one or more of the resources are designated according to a given scheme and the resources requested for device processor channel resources are specified in units of resources. 29. The apparatus of claim 28, wherein the second switching means comprises a terminal access unit (TCU) and at least one terminal unit (TU) connected thereto, and the resources for the traffic channel and / or the device processor channel are Device requested by the terminal unit (TU) connected to. 29. The method of claim 28, wherein resources for the traffic channel and / or the device processor channel are requested by a device of a transmission system directly connected to a terminal access unit (TCU) of the second switching means.