JP3569613B2

JP3569613B2 - Loop type data transmission device

Info

Publication number: JP3569613B2
Application number: JP26571797A
Authority: JP
Inventors: 敏男中谷
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1997-09-30
Filing date: 1997-09-30
Publication date: 2004-09-22
Anticipated expiration: 2017-09-30
Also published as: JPH11112537A

Description

【０００１】
【発明の属する技術分野】
この発明は、ループ状伝送路に複数のノード装置を接続し、各ノード装置に接続された端末装置間でデータ伝送を行う、ループ式データ伝送装置に関し、特に多重伝送方式としてＳＤＨ（同期デジタル・ハイアラ−キ）によるフレーム構造を有するループ式データ伝送装置に関するものである。
【０００２】
【従来の技術】
図１４は、例えば特開平５−２６８２３５号公報に示されているＳＤＨ方式を用いたループ式データ伝送方式の構成図である。図においてＮ１〜Ｎ６はノード装置、９１はこれらノード装置に接続されている端末装置である。１０は０系伝送路、１１は１系伝送路であり、２重ループの伝送路になっている。なお、上記伝送路の信号は高速デジタル信号に適用されるＳＤＨ方式のフレーム構造を採用している。
【０００３】
図１５は、前記ノード装置Ｎ１〜Ｎ６の構成図である。各ノード装置は同一構成になっている。図１５において図１４と同じ符号のものは同じ機能のものを示す。５０は０系伝送路インタフェース、５１は１系伝送路インタフェースで、それぞれ受信回路と送信回路とを備え、０系、１系のループ伝送路とループバック回路７１の間のインタフェースをとる。７１はループバック切り替えを行うループバック回路、７２は信号の多重化または多重分離を行う多重化／多重分離部、６はループバック回路７１と多重化／多重分離部７２の切り替え動作を制御するノード制御回路、８は端末装置９１と多重化／多重分離部７２の間のインタフェース機能を司る回線インタフェースである。
【０００４】
また、図１６は、ＳＤＨの基本構造であるＳＴＭ−１の多重化フレーム構造を示す。ＳＴＭ−１では、１フレーム１２５μｓ（音声情報の符号化の基本周期）に９列２７０行のタイムスロットを持つように構成されている。ここで、１タイムスロットは６４Ｋｂ／ｓ相当の伝送容量を有する。従って、ＳＴＭ−１の伝送容量は、１５５．５２Ｍｂ／ｓとなる。
【０００５】
多重化フレームの構造は、バイト単位の行数と列数で表現されているが、これは高速となるとビット数が多くなり、横１列では書き切れないことと、ネットワークの管理に使うオーバヘッド信号を集中的に配置して見やすくするためである。ＳＴＭ−１のフレーム構造は、９列目以降２６１列は各種情報を収容するタイムスロットであり、ペイロードと呼ばれる。なお図１６に記載の例は３組のバーチャルコンテナＶＣ−３で構成されており、その先頭にコンテナの監視信号であるパスオーバヘッド（Ｐ．Ｏ．Ｈ）が配置されている。一方最初の９行×９列は各種情報を伝達する際のネットワーク管理情報を収容するセクションオーバヘッド（Ｓ．Ｏ．Ｈ）と、ペイロードに収容される多重化情報の先頭位置を指定するポインターに割り当てられている。ＳＤＨの基本構成であるＳＴＭ−１への多重化は、バーチャルコンテナ（ＶＣ）と呼ばれる規格化された伝送容量を単位として積み上げていく。バーチャルコンテナは、既存の低速情報を含む各種の情報が多重化できるように準備されているが、その最小ハンドリング単位は、１．５４４Ｍｂ／ｓ（６４Ｋｂ／ｓで、２４ＣＨ相当）である。なお、図１６で多重化されるバーチャルコンテナＶＣ−３のフレームを、ペイロードからずらせて表現しているのは、ＳＴＭ−１の時間位相とＶＣ−３のフレーム位相が変化する事を表している。
【０００６】
図１７はＴＴＣ（社団法人電信電話技術委員会）で標準化された多重化構造を示す。図からわかるように、各種の伝送容量を持ったコンテナ（Ｃ−１、Ｃ−２、Ｃ−３、Ｃ−４）を積み上げてＳＴＭ−１のフレーム構造を構築しているが、最小のコンテナはＣ１（１．５４４Ｍｂ／ｓ）コンテナである。つまりＳＴＭ−ｎの最小ハンドリング容量は１．５４４Ｍｂ／ｓである。
【０００７】
次に動作を説明する。０系伝送路１０から入力した受信信号は０系伝送路インタフェース５０に入力され、デジタル信号に変換されてループバック回路７１に導かれ、さらに伝送装置の動作状態に応じた制御による信号選択が行われ、多重化／多重分離部７２へ導かれる。多重化／多重分離部７２はＳＤＨ多重化構造に基ずき多重化されたデータを多重分離し、そのうち、端末装置９１毎に予め割り当てられているフレーム上のタイムスロット位置にマッピングされているデータを端末インタフェース８へ出力し、それ以外のデータを一時記憶する。一方端末装置９１からの信号は、回線インタフェース装置８でデジタル信号に変換されて多重化／多重分離部７２に渡される。この多重化／多重分離部７２では端末装置９１毎に予め定められているタイムスロット位置にマッピングされ、前記多重化／多重分離部７２で一時記憶されている信号と多重化されて、ループバック回路７１および０系伝送路インタフェース５０を経て０系伝送路１０に送り出される。
【０００８】
【発明が解決しようとする課題】
従来のループ式伝送装置は以上のように構成され、多重化および多重分離を段階的に行っていたが、ＳＤＨの多重化構造の規格では、１．５４４Ｍｂ／ｓから上の高速信号しか規定されておらず、このため低速信号、例えば６４Ｋｂ／ｓの信号を多重化／多重分離する場合には、別の装置により一度６４Ｋｂ／ｓから１．５４４Ｋｂ／ｓヘ多重変換を行い、この信号をノード装置の多重化／多重分離部に接続する必要があった。このため構成が複雑になるという問題があった。
【０００９】
さらに、従来のＳＤＨ方式フレーム構造の信号を使ったループ式伝送装置では、最低でも１．５４４Ｍｂ／ｓの伝送速度の単位でタイムスロットの割付が行われるので、あるノード装置間の通信に必要な伝送速度が例えば６４Ｋｂ／ｓでよい場合でも、最低のハンドリング容量である１．５４４Ｍｂ／ｓ分のタイムスロットを割り付けることになり、回線の使用効率が非常に悪いという問題があった。
【００１０】
この発明は、このような課題を解決するためになされたものであり、第１の目的は、伝送速度が６４Ｋｂ／ｓのような低速信号でも、段階的な多重化を経ることなく直接ＳＴＭ−１のフレームへ多重化し、構成の単純化と回線の使用効率を高めること、第２の目的は、多重化フレーム上のタイムスロットの位置の入替えをタイムスロット単位で出来るようにし、ノード装置内での局内交換を可能にする、かつ、この多重化フレーム上のタイムスロットの位置の割付をオンライン中でも設定出来るようにすること、第３の目的は、各構成要素、具体的には回線インタフェース部、多重化／多重化分離部の構成を単純にすること、第４の目的は、回線インタフェース部の故障や回線インタフェース部が無い場合に、不正なデータが端末から送信されるのを防止すること、第５の目的は、多重化／多重分離部の初期設定が完了していない場合に不正なデータが端末から送信されるのを防止すること、等である。
【００１１】
【課題を解決するための手段】
この発明に係るループ式データ伝送装置は、デジタル化多重信号を所定方向に伝送する第１の伝送路と所定方向とは反対方向に伝送する第２の伝送路とからなるループ状の伝送路と、ループ状の伝送路を介して相互に信号のやり取りを行う複数の端末装置と、伝送路の途中に配置され、伝送路に伝送される信号のうち、所定のタイムスロットの信号を抽出して多重分離し端末装置に向けて送り出し、または端末装置からの信号を取り込んで多重化し、伝送路へ送り出すノード装置とからなるループ式データ伝送装置において、ノード装置は、伝送路に伝送されるＳＤＨ方式の多重化フレーム信号にアクセスし、割り当てられたタイムスロットから信号を選択的に抽出して多重分離し、端末装置に向けて送り出し、または端末装置からの信号を取り込んで割り当てられたタイムスロットへ選択的に配置し、多重化して伝送路へ送り出す多重化／多重分離部を備え、多重化／多重分離部は、伝送路からのデジタル受信信号を再び伝送路へ送り出すまでの間一時記憶する受信中継メモリと、端末装置から送り込まれた多重化のためのデジタル多重化信号を一時記憶する多重メモリと、受信中継メモリから読み出される内容を多重メモリから読み出される内容に部分的に入替えるための多重化フレーム上のタイムスロットのアドレスの指定と、この入替えを制御する信号を発生する多重メモリアドレス変換部と、受信中継メモリの内容と多重メモリの内容とを多重メモリアドレス変換部からの制御に基づいて切り替えるセレクタ部とを有し、デジタル化受信中継信号とデジタル多重化信号の入替えを可能としたものである。
【００１２】
また、この発明に係るループ式データ伝送装置は、デジタル化光多重信号を所定方向に伝送する第１の伝送路と所定方向とは反対方向に伝送する第２の伝送路とからなるループ状の伝送路と、ループ状の伝送路を介して相互に信号のやり取りを行う複数の端末装置と、ループ状の伝送路の途中に配置され、伝送路に伝送される多重化フレーム信号のうち所定のタイムスロットの信号を抽出して多重分離し、端末装置に向けて送り出し、または端末装置からの信号を取り込んで前記多重化フレーム信号の所定タイムスロットへ配置して多重化し伝送路へ送り出すノード装置とからなるループ式データ伝送装置において、ノード装置は、第１の伝送路からの光信号を電気信号に変換してノード装置の内部回路へ導くともにノード装置の内部回路からの電気信号を光信号に変換して第２の伝送路に送り出す第１の終端部と、第２の伝送路からの光信号を電気信号に変換してノード装置の内部回路へ導くとともにノード装置の内部回路からの電気信号を光信号に変換して第１の伝送路に送り出す第２の終端部と、第１または第２の伝送路のうち予め設定された一方の伝送路からの信号を選択して取り込み、同方向に向う他方の伝送路、または同方向に向かう一方の伝送路へ信号の送出を行う系選択回路と、端末装置からの伝送信号を多重化フレーム信号の所定のタイムスロット位置に配置して多重化を行うと共に、系選択回路から送り込まれた多重化フレーム信号の所定のタイムスロット位置から伝送信号を抽出して多重分離を行う多重化／多重分離部と、共通の信号路で構成され、多重化／多重分離部と前記端末装置との間の信号の受け渡しをする多重／分離バスと、端末装置と前記多重／分離バスの間のインタフェースをとる回線インタフェース部と、ノード管理バスを経てノード内各装置の動作状態の管理を行うノード管理プロセッサ部とを備え、多重化／多重分離部は、伝送路からのデジタル受信信号を再び伝送路へ送り出すまでの間一時記憶する受信中継メモリと、端末装置から送り込まれた多重化のためのデジタル多重化信号を一時記憶する多重メモリと、受信中継メモリから読み出される内容を多重メモリから読み出される内容に部分的に入替えるための多重化フレーム上のタイムスロットのアドレスの指定と、この入替えを制御する信号を発生する多重メモリアドレス変換部と、受信中継メモリの内容と多重メモリの内容とを多重メモリアドレス変換部からの制御に基づいて切り替えるセレクタ部とを有し、デジタル化受信中継信号とデジタル多重化信号の入替えを可能としたものである。
【００１３】
また、この発明に係るループ式データ伝送装置は、デジタル化多重信号を所定方向に伝送する第１の伝送路と所定方向とは反対方向に伝送する第２の伝送路とからなるループ状の伝送路と、ループ状の伝送路を介して相互に信号のやり取りを行う複数の端末装置と、伝送路の途中に配置され、伝送路に伝送される信号のうち、所定のタイムスロットの信号を抽出して多重分離し前記端末装置に向けて送り出し、または端末装置からの信号を取り込んで多重化し、伝送路へ送り出すノード装置とからなるループ式データ伝送装置において、ノード装置は、前記伝送路に伝送されるＳＤＨ方式の多重化フレーム信号にアクセスし、割り当てられたタイムスロットから信号を選択的に抽出して多重分離し、端末装置に向けて送り出し、または端末装置からの信号を取り込んで割り当てられたタイムスロットへ選択的に配置し、多重化して伝送路へ送り出す多重化／多重分離部を備え、多重化／多重分離部は、伝送路からのデジタル受信信号を再び伝送路へ送り出すまでの間一時記憶する受信中継メモリと、端末装置から送り込まれる多重化のためのデジタル多重化信号を一時記憶する多重メモリと、多重メモリから読み出される内容を受信中継メモリから読み出される内容に入替える部分の多重化フレーム上のタイムスロットのアドレスの指定と、この入替えを制御する信号を発生する多重メモリアドレス変換部と、受信中継メモリの内容と多重メモリの内容を前記多重メモリアドレス変換部からの制御に基づいて切り替えるセレクタ部と、デジタル受信信号を多重分離するために一時記憶する分離メモリと、端末装置から送り込まれる多重化のためのデジタル多重化信号を一時記憶する局内交換メモリと、局内交換メモリから読み出される内容を前記分離メモリから読み出される内容に入替える部分の多重化フレーム上のタイムスロットのアドレスの指定と、この入替えを制御する信号を発生する分離メモリアドレス変換部と、分離メモリの内容と局内交換メモリの内容を分離メモリアドレス変換部からの制御に基づいて切り替えるセレクタとを有し、デジタル受信信号とデジタル多重化信号の入替え、および分離メモリの内容と局内交換メモリの内容の入替えによる局内交換を可能としたものである。
【００１４】
また、この発明に係るループ式データ伝送装置は、デジタル化光多重信号を所定方向に伝送する第１の伝送路と所定方向とは反対方向に伝送する第２の伝送路とからなるループ状の伝送路と、ループ状の伝送路を介して相互に信号のやり取りを行う複数の端末装置と、ループ状の伝送路の途中に配置され、伝送路に伝送される多重化フレーム信号のうち所定のタイムスロットの信号を抽出して多重分離し、端末装置に向けて送り出し、または端末装置からの信号を取り込んで多重化フレーム信号の所定タイムスロットへ配置して多重化し伝送路へ送り出すノード装置とからなるループ式データ伝送装置において、ノード装置は、第１の伝送路からの光信号を電気信号に変換してノード装置の内部回路へ導くとともにノード装置の内部回路からの電気信号を光信号に変換して第２の伝送路に送り出す第１の終端部と、第２の伝送路からの光信号を電気信号に変換してノード装置の内部回路へ導くとともにノード装置の内部回路からの電気信号を光信号に変換して第１の伝送路に送り出す第２の終端部と、第１または第２の伝送路のうち予め設定された一方の伝送路からの信号を選択して取り込み、同方向に向う他方の伝送路、または同方向に向かう一方の伝送路へ信号の送出を行う系選択回路と、端末装置からの伝送信号を多重化フレーム信号の所定のタイムスロット位置に配置して多重化を行うと共に、系選択回路から送り込まれた多重化フレーム信号の所定のタイムスロット位置から伝送信号を抽出して多重分離を行う多重化／多重分離部と、共通の信号路で構成され、多重化／多重分離部と前記端末装置との間の信号の受け渡しをする多重／分離バスと、端末装置と前記多重／分離バスの間のインタフェースをとる回線インタフェース部と、ノード管理バスを経てノード内各装置の動作状態の管理を行うノード管理プロセッサ部とを備え、多重化／多重分離部は、伝送路からのデジタル受信信号を再び伝送路へ送り出すまでの間一時記憶する受信中継メモリと、端末装置から送り込まれる多重化のためのデジタル多重化信号を一時記憶する多重メモリと、多重メモリから読み出される内容を受信中継メモリから読み出される内容に入替える部分の多重化フレーム上のタイムスロットのアドレスの指定と、この入替えを制御する信号を発生する多重メモリアドレス変換部と、受信中継メモリの内容と多重メモリの内容を多重メモリアドレス変換部からの制御に基づいて切り替えるセレクタ部と、デジタル受信信号を多重分離するために一時記憶する分離メモリと、端末装置から送り込まれる多重化のためのデジタル多重化信号を一時記憶する局内交換メモリと、局内交換メモリから読み出される内容を前記分離メモリから読み出される内容に入替える部分の多重化フレーム上のタイムスロットのアドレスの指定と、この入替えを制御する信号を発生する分離メモリアドレス変換部と、分離メモリの内容と局内交換メモリの内容を前記分離メモリアドレス変換部からの制御に基づいて切り替えるセレクタとを有し、デジタル受信信号とデジタル多重化信号の入替え、および分離メモリの内容と局内交換メモリの内容の入替えによる局内交換を可能としたものである。
【００１５】
また、この発明に係るループ式データ伝送装置は、デジタル化多重信号を所定方向に伝送する第１の伝送路と所定方向とは反対方向に伝送する第２の伝送路とからなるループ状の伝送路と、ループ状の伝送路を介して相互に信号のやり取りを行う複数の端末装置と、伝送路の途中に配置され、伝送路に伝送される信号のうち、所定のタイムスロットの信号を抽出して多重分離し端末装置に向けて送り出し、または端末装置からの信号を取り込んで多重化し、伝送路へ送り出すノード装置とからなるループ式データ伝送装置において、
ノード装置は、伝送路に伝送されるＳＤＨ方式の多重化フレーム信号にアクセスし、割り当てられたタイムスロットから信号を選択的に抽出して多重分離し、端末装置に向けて送り出し、または端末装置からの信号を取り込んで割り当てられたタイムスロットへ選択的に配置し、多重化して前記伝送路へ送り出す多重化／多重分離部を備え、多重化／多重分離部は、２ポートメモリで構成された多重メモリアドレス変換部および分離アドレス変換部と、ノード管理バスを経てこれらメモリの設定を行うノード管理プロセッサ部とを有したものである。
【００１６】
また、この発明に係るループ式データ伝送装置は、デジタル化光多重信号を所定方向に伝送する第１の伝送路と所定方向とは反対方向に伝送する第２の伝送路とからなるループ状の伝送路と、ループ状の伝送路を介して相互に信号のやり取りを行う複数の端末装置と、ループ状の伝送路の途中に配置され、伝送路に伝送される多重化フレーム信号のうち所定のタイムスロットの信号を抽出して多重分離し、端末装置に向けて送り出し、または端末装置からの信号を取り込んで前記多重化フレーム信号の所定タイムスロットへ配置して多重化し伝送路へ送り出すノード装置とからなるループ式データ伝送装置において、ノード装置は、第１の伝送路からの光信号を電気信号に変換してノード装置の内部回路へ導くとともにノード装置の内部回路からの電気信号を光信号に変換して第２の伝送路に送り出す第１の終端部と、第２の伝送路からの光信号を電気信号に変換してノード装置の内部回路へ導くとともにノード装置の内部回路からの電気信号を光信号に変換して第１の伝送路に送り出す第２の終端部と、第１または第２の伝送路のうち予め設定された一方の伝送路からの信号を選択して取り込み、同方向に向う他方の伝送路、または同方向に向かう一方の伝送路へ信号の送出を行う系選択回路と、端末装置からの伝送信号を多重化フレーム信号の所定のタイムスロット位置に配置して多重化を行うと共に、系選択回路から送り込まれた多重化フレーム信号の所定のタイムスロット位置から伝送信号を抽出して多重分離を行う多重化／多重分離部と、共通の信号路で構成され、多重化／多重分離部と端末装置との間の信号の受け渡しをする多重／分離バスと、端末装置と多重／分離バスの間のインタフェースをとる回線インタフェース部と、ノード管理バスを経てノード内各装置の動作状態の管理を行うノード管理プロセッサ部とを備え、多重化／多重分離部は、２ポートメモリで構成された多重メモリアドレス変換部および分離アドレス変換部と、ノード管理バスを経てこれらメモリの設定を行うノード管理プロセッサ部とを有したものである。
【００１７】
また、この発明に係るループ式データ伝送装置は、デジタル化多重信号を所定方向に伝送する第１の伝送路と所定方向とは反対方向に伝送する第２の伝送路とからなるループ状の伝送路と、ループ状の伝送路を介して相互に信号のやり取りを行う複数の端末装置と、伝送路の途中に配置され、伝送路に伝送される信号のうち、所定のタイムスロットの信号を抽出して多重分離し前記端末装置に向けて送り出し、または端末装置からの信号を取り込んで多重化し、伝送路へ送り出すノード装置とからなるループ式データ伝送装置において、ノード装置は、伝送路に伝送されるＳＤＨ方式の多重化フレーム信号にアクセスし、割り当てられたタイムスロットから信号を選択的に抽出して多重分離し、端末装置に向けて送り出し、または端末装置からの信号を取り込んで割り当てられたタイムスロットへ選択的に配置し、多重化して伝送路へ送り出す多重化／多重分離部を備え、多重化／多重分離部は、各回線インタフェース部に付与された固有のポート番号と対応ずけたポート番号を多重／分離バスへの入力信号に付与する手段を有し、多重／分離バスへの入力信号に付された固有のポート番号により、多重／分離バス上の信号を回線インタフェース部が抽出するようにしたものである。
また、この発明に係るループ式データ伝送装置は、デジタル化光多重信号を所定方向に伝送する第１の伝送路と所定方向とは反対方向に伝送する第２の伝送路とからなるループ状の伝送路と、ループ状の伝送路を介して相互に信号のやり取りを行う複数の端末装置と、ループ状の伝送路の途中に配置され、伝送路に伝送される多重化フレーム信号のうち所定のタイムスロットの信号を抽出して多重分離し、端末装置に向けて送り出し、または端末装置からの信号を取り込んで多重化フレーム信号の所定タイムスロットへ配置して多重化し伝送路へ送り出すノード装置とからなるループ式データ伝送装置において、ノード装置は、第１の伝送路からの光信号を電気信号に変換してノード装置の内部回路へ導くとともにノード装置の内部回路からの電気信号を光信号に変換して第２の伝送路に送り出す第１の終端部と、第２の伝送路からの光信号を電気信号に変換してノード装置の内部回路へ導くとともにノード装置の内部回路からの電気信号を光信号に変換して第１の伝送路に送り出す第２の終端部と、第１または第２の伝送路のうち予め設定された一方の伝送路からの信号を選択して取り込み、同方向に向う他方の伝送路、または同方向に向かう一方の伝送路へ信号の送出を行う系選択回路と、端末装置からの伝送信号を多重化フレーム信号の所定のタイムスロット位置に配置して多重化を行うと共に、系選択回路から送り込まれた多重化フレーム信号の所定のタイムスロット位置から伝送信号を抽出して多重分離を行う多重化／多重分離部と、共通の信号路で構成され、多重化／多重分離部と端末装置との間の信号の受け渡しをする多重／分離バスと、端末装置と多重／分離バスの間のインタフェースをとる回線インタフェース部と、ノード管理バスを経てノード内各装置の動作状態の管理を行うノード管理プロセッサ部とを備え、多重化／多重分離部は、各回線インタフェース部に付与された固有のポート番号と対応ずけたポート番号を多重／分離バスへの入力信号に付与する手段を有し、多重／分離バスへの入力信号に付された固有のポート番号により、多重／分離バス上の信号を回線インタフェース部が抽出するようにしたものである。
【００１８】
また、この発明に係るループ式データ伝送装置は、デジタル化多重信号を所定方向に伝送する第１の伝送路と所定方向とは反対方向に伝送する第２の伝送路とからなるループ状の伝送路と、ループ状の伝送路を介して相互に信号のやり取りを行う複数の端末装置と、伝送路の途中に配置され、伝送路に伝送される信号のうち、所定のタイムスロットの信号を抽出して多重分離し端末装置に向けて送り出し、または端末装置からの信号を取り込んで多重化し、前記伝送路へ送り出すノード装置とからなるループ式データ伝送装置において、ノード装置は、伝送路に伝送されるＳＤＨ方式の多重化フレーム信号にアクセスし、割り当てられたタイムスロットから信号を選択的に抽出して多重分離し、端末装置に向けて送り出し、または端末装置からの信号を取り込んで割り当てられたタイムスロットへ選択的に配置し、多重化して前記伝送路へ送り出す多重化／多重分離部を備え、多重化／多重分離部は、分離メモリまたは局内交換メモリから多重／分離バスへの読み出し信号に、予め設定された所属の回線インタフェースの分離バス上のポート番号を付すリード制御回路を有し、このポート番号に基づいて前記回線インタフェース部が多重／分離バスからの読み出し信号を選別して抽出するようにしたものである。
また、この発明に係るループ式データ伝送装置は、デジタル化光多重信号を所定方向に伝送する第１の伝送路と所定方向とは反対方向に伝送する第２の伝送路とからなるループ状の伝送路と、ループ状の伝送路を介して相互に信号のやり取りを行う複数の端末装置と、ループ状の伝送路の途中に配置され、伝送路に伝送される多重化フレーム信号のうち所定のタイムスロットの信号を抽出して多重分離し、端末装置に向けて送り出し、または端末装置からの信号を取り込んで多重化フレーム信号の所定タイムスロットへ配置して多重化し伝送路へ送り出すノード装置とからなるループ式データ伝送装置において、ノード装置は、第１の伝送路からの光信号を電気信号に変換してノード装置の内部回路へ導くとともにノード装置の内部回路からの電気信号を光信号に変換して第２の伝送路に送り出す第１の終端部と、第２の伝送路からの光信号を電気信号に変換してノード装置の内部回路へ導くとともにノード装置の内部回路からの電気信号を光信号に変換して第１の伝送路に送り出す第２の終端部と、第１または第２の伝送路のうち予め設定された一方の伝送路からの信号を選択して取り込み、同方向に向う他方の伝送路、または同方向に向かう一方の伝送路へ信号の送出を行う系選択回路と、端末装置からの伝送信号を多重化フレーム信号の所定のタイムスロット位置に配置して多重化を行うと共に、系選択回路から送り込まれた多重化フレーム信号の所定のタイムスロット位置から伝送信号を抽出して多重分離を行う多重化／多重分離部と、共通の信号路で構成され、多重化／多重分離部と端末装置との間の信号の受け渡しをする多重／分離バスと、前記端末装置と前記多重／分離バスの間のインタフェースをとる回線インタフェース部と、ノード管理バスを経てノード内各装置の動作状態の管理を行うノード管理プロセッサ部とを備え、多重化／多重分離部は、分離メモリまたは局内交換メモリから多重／分離バスへの読み出し信号に、予め設定された所属の回線インタフェースの分離バス上のポート番号を付すリード制御回路を有し、このポート番号に基づいて回線インタフェース部が多重／分離バスからの読み出し信号を選別して抽出するようにしたものである。
また、この発明に係るループ式データ伝送装置の多重化／多重分離部は、多重／分離バス上に設定されるアドレス信号を生成して所定の回線インタフェース部へ送るとともに、このアドレス信号による制御で、分離メモリまたは局内交換メモリの多重／分離バスへの読み出しを行うリード制御回路を備え、リード制御回路から送られてきた多重／分離バス上のアドレス信号に基づき、回線インタフェース部が多重／分離バスからの信号の読み出しを行うようにしたものである。
【００１９】
また、この発明に係るループ式データ伝送装置は、デジタル化多重信号を所定方向に伝送する第１の伝送路と所定方向とは反対方向に伝送する第２の伝送路とからなるループ状の伝送路と、ループ状の伝送路を介して相互に信号のやり取りを行う複数の端末装置と、伝送路の途中に配置され、伝送路に伝送される信号のうち、所定のタイムスロットの信号を抽出して多重分離し端末装置に向けて送り出し、または端末装置からの信号を取り込んで多重化し、伝送路へ送り出すノード装置とからなるループ式データ伝送装置において、
ノード装置は、伝送路に伝送されるＳＤＨ方式の多重化フレーム信号にアクセスし、割り当てられたタイムスロットから信号を選択的に抽出して多重分離し、端末装置に向けて送り出し、または端末装置からの信号を取り込んで割り当てられたタイムスロットへ選択的に配置し、多重化して伝送路へ送り出す多重化／多重分離部を備え、多重化／多重分離部は、回線インタフェース部からの信号に付された多重化要求信号と、多重メモリに記憶された信号の多重／中継ビットのＡＮＤ条件が論理“１”のときに、受信中継信号に代え多重メモリのデータを選択して送出するセレクタを有したものである。
また、この発明に係るループ式データ伝送装置は、デジタル化光多重信号を所定方向に伝送する第１の伝送路と所定方向とは反対方向に伝送する第２の伝送路とからなるループ状の伝送路と、ループ状の伝送路を介して相互に信号のやり取りを行う複数の端末装置と、ループ状の伝送路の途中に配置され、伝送路に伝送される多重化フレーム信号のうち所定のタイムスロットの信号を抽出して多重分離し、前記端末装置に向けて送り出し、または端末装置からの信号を取り込んで多重化フレーム信号の所定タイムスロットへ配置して多重化し前記伝送路へ送り出すノード装置とからなるループ式データ伝送装置において、
ノード装置は、第１の伝送路からの光信号を電気信号に変換してノード装置の内部回路へ導くとともに前記ノード装置の内部回路からの電気信号を光信号に変換して第２の伝送路に送り出す第１の終端部と、第２の伝送路からの光信号を電気信号に変換してノード装置の内部回路へ導くとともにノード装置の内部回路からの電気信号を光信号に変換して第１の伝送路に送り出す第２の終端部と、第１または第２の伝送路のうち予め設定された一方の伝送路からの信号を選択して取り込み、同方向に向う他方の伝送路、または同方向に向かう一方の伝送路へ信号の送出を行う系選択回路と、端末装置からの伝送信号を多重化フレーム信号の所定のタイムスロット位置に配置して多重化を行うと共に、系選択回路から送り込まれた多重化フレーム信号の所定のタイムスロット位置から伝送信号を抽出して多重分離を行う多重化／多重分離部と、共通の信号路で構成され、多重化／多重分離部と前記端末装置との間の信号の受け渡しをする多重／分離バスと、端末装置と前記多重／分離バスの間のインタフェースをとる回線インタフェース部と、ノード管理バスを経てノード内各装置の動作状態の管理を行うノード管理プロセッサ部とを備え、多重化／多重分離部は、回線インタフェース部からの信号に付された多重化要求信号と、多重メモリに記憶された信号の多重／中継ビットのＡＮＤ条件が論理“１”のときに、受信中継信号に代え多重メモリのデータを選択して送出するセレクタを有したものである。
【００２０】
また、この発明に係るループ式データ伝送装置は、デジタル化多重信号を所定方向に伝送する第１の伝送路と所定方向とは反対方向に伝送する第２の伝送路とからなるループ状の伝送路と、ループ状の伝送路を介して相互に信号のやり取りを行う複数の端末装置と、伝送路の途中に配置され、伝送路に伝送される信号のうち、所定のタイムスロットの信号を抽出して多重分離し端末装置に向けて送り出し、または端末装置からの信号を取り込んで多重化し、伝送路へ送り出すノード装置とからなるループ式データ伝送装置において、
ノード装置は、前記伝送路に伝送されるＳＤＨ方式の多重化フレーム信号にアクセスし、割り当てられたタイムスロットから信号を選択的に抽出して多重分離し、端末装置に向けて送り出し、または端末装置からの信号を取り込んで割り当てられたタイムスロットへ選択的に配置し、多重化して前記伝送路へ送り出す多重化／多重分離部を備え、多重化／多重分離部は、多重化／多重分離部の各回路に初期化を指示するとともに、初期化完了状態を保持する記憶回路を有し、多重メモリに記憶された信号の多重／中継ビットと初期化完了を示す前記記憶回路の出力とによって、多重メモリのデータを選択し出力するようにしたものである。
また、この発明に係るループ式データ伝送装置は、デジタル化光多重信号を所定方向に伝送する第１の伝送路と所定方向とは反対方向に伝送する第２の伝送路とからなるループ状の伝送路と、前記ループ状の伝送路を介して相互に信号のやり取りを行う複数の端末装置と、ループ状の伝送路の途中に配置され、伝送路に伝送される多重化フレーム信号のうち所定のタイムスロットの信号を抽出して多重分離し、端末装置に向けて送り出し、または端末装置からの信号を取り込んで多重化フレーム信号の所定タイムスロットへ配置して多重化し前記伝送路へ送り出すノード装置とからなるループ式データ伝送装置において
ノード装置は、第１の伝送路からの光信号を電気信号に変換して前記ノード装置の内部回路へ導くとともにノード装置の内部回路からの電気信号を光信号に変換して第２の伝送路に送り出す第１の終端部と、第２の伝送路からの光信号を電気信号に変換してノード装置の内部回路へ導くとともにノード装置の内部回路からの電気信号を光信号に変換して第１の伝送路に送り出す第２の終端部と、第１または第２の伝送路のうち予め設定された一方の伝送路からの信号を選択して取り込み、同方向に向う他方の伝送路、または同方向に向かう一方の伝送路へ信号の送出を行う系選択回路と、端末装置からの伝送信号を多重化フレーム信号の所定のタイムスロット位置に配置して多重化を行うと共に、系選択回路から送り込まれた多重化フレーム信号の所定のタイムスロット位置から伝送信号を抽出して多重分離を行う多重化／多重分離部と、共通の信号路で構成され、多重化／多重分離部と前記端末装置との間の信号の受け渡しをする多重／分離バスと、端末装置と多重／分離バスの間のインタフェースをとる回線インタフェース部と、ノード管理バスを経てノード内各装置の動作状態の管理を行うノード管理プロセッサ部とを備え、多重化／多重分離部は、多重化／多重分離部の各回路に初期化を指示するとともに、初期化完了状態を保持する記憶回路を有し、多重メモリに記憶された信号の多重／中継ビットと初期化完了を示す記憶回路の出力とによって、多重メモリのデータを選択し出力するようにしたものである。
【００２１】
【発明の実施の形態】
実施の形態１．
図１は、本発明に係るループ式データ伝送装置の構成図である。図において、２はノード装置（Ｎ１〜Ｎ６）、３は各々これらノード装置２に接続された端末装置、１は反時計方向の光伝送路を構成する０系伝送路１０と、時計方向の光伝送路を構成する１系伝送路１１とからなる伝送路である。また、伝送路１では、先に説明したＳＤＨ方式にかかるフレーム構造を有するＳＴＭ−１相当の広帯域デジタル信号の伝送が行われている。
【００２２】
図２は、上記ループ式データ伝送装置のノード装置２の構成図である。ここで、各ノード装置２はともに同じ構成になっている。２０ａはＡ系ＳＴＭ−１終端部、２０ｂはＢ系ＳＴＭ−１終端部で、それぞれ光伝送路１０、１１からの光信号を電気信号に変換する光／電気変換部２１１、電気信号を光信号に変換して光伝送路へ送り出す電気／光変換部２１２、ＳＴＭ−１終端部２２から構成される。
【００２３】
このループ式データ伝送装置では、０系伝送路１０からの光信号はＡ系ＳＴＭ−１終端部２０ａに入力され、Ａ系ＳＴＭ−１終端部２０ａから出力された光信号は、１系伝送路１１に送り出される。また、１系伝送路１１からの光信号は、Ｂ系ＳＴＭ−１終端部２０ｂへ入力され、Ｂ系ＳＴＭ−１終端部２０ｂから出力した光信号は０系伝送路１０へ送り出される。
【００２４】
０系伝送路１０から入力された光信号はＡ系ＳＴＭ−１終端部２０ａにおいて、また１系伝送路１１から入力された光信号はＢ系ＳＴＭ−１終端部２０ｂにおいて、それぞれの光／電気変換部２１１でシリアルな電気信号に変換された後、それぞれのＳＴＭ−１終端部２２でＳＯＨ部分（セクションオーバヘッド部分）が取り除かれ、系選択回路部２３へ出力される。
【００２５】
２３は上記Ａ系とＢ系の選択を行う系選択回路部、２４は多重化フレーム上の所定のタイムスロットへデータ信号を多重化し、あるいは多重化フレーム上の所定のタイムスロットからデータ信号を抽出して多重分離を行う多重分離化を行う多重化／多重分離部、２６は多重化／多重分離部と回線インタフェース部との間の信号のやり取りを行う多重／分離バスである。２５はノード装置２と端末装置３との間のインタフェースをとる回線インタフェース部、３は端末装置である。２７はノード管理バス２８を介してノード内の各回路と接続し各回路が所望の動作を行うようデータを設定したり監視を行うノード管理プロセッサー部である。
【００２６】
通常は系選択回路部２３は０系伝送路１０側から信号を選択して、多重化／多重分離部２４へ出力する。また多重化／多重分離部２４から出力された信号は系選択回路部２３へ出力される。通常は系選択回路部２３では多重化／多重分離部２４からの信号をＢ系ＳＴＭ−１終端部２０ｂへ出力し、Ｂ系ＳＴＭ−１終端部２０ｂでＳＯＨを付加した後、電気／光変換部２１２に出力し光信号に変換後、０系伝送路１０へ送出される。また、多重化／多重分離部２４は多重／分離バス２６を制御して、複数の回線インタフェース部２５を介してそれぞれの端末装置３との間の接続を行っている。具体的には、各回線インタフェース部２５に付された固有のポート番号と、多重／分離バス２６の入出力信号に付された固有のポート番号とにより、多重分離バス２６上の信号と回線インタフェース部２５との対応関係を特定し信号の受け渡しを制御するようにしている。
【００２７】
また、このループ式伝送装置で扱われる光信号の多重化フレーム構造は、ＳＤＨの基本構造であるＳＴＭ−１に相当する構造となっている。
ＳＴＭ−１の多重化フレーム構造は、１フレーム１２５μｓ（音声情報の符号化の基本周期）に９列２７０行のタイムスロットを持つ構造になっている。ここで、１タイムスロットは６４Ｋｂ／ｓ相当の伝送容量を有する。このフレーム構造において、９列目以降の２６１列は各種情報を収容するタイムスロットであり、ペイロードと呼ばれる。また最初の９行×９列は各種情報を伝達する際のネットワーク管理情報を収容するセクションオーバヘッド（Ｓ．Ｏ．Ｈ）と、ペイロードに収容される多重化情報の先頭位置を指定するポインターに割り当てられている。このようなフレーム構造において、低速信号を含めた効率よく多重化フレームのタイムスロット上に割り付けるため、本発明では上記ビット配列を９ビット（＝９タイムスロット）を１単位としてブロック化する。図３は、このようにブロック化したペイロード部分を示している。このブロック化によってペイロード部分のブロック化数（パスペイロード）は０から２５９迄の２６０ブロックとなる。
【００２８】
図４は、このブロック化した１ブロックに含まれるタイムスロットの構成内容を説明する図である。１つのブロックはデータスロット８個と信号スロット１個の計９個のタイムスロットから構成されている。そして、データスロットと信号スロットの各１スロットは８ビットで構成されていて、データスロット１個で６４Ｋｂ／ｓの伝送速度を有するデータの伝送を行うことができる。また、信号スロットは、収容する端末回線に応じてデータ以外のダイヤリング情報等の付加情報を伝送するためのエリアである。また、信号スロットは８ビット構成であり、最下位ビットがこの信号スロットの８個分前のデータスロットの信号ビットに割り当てられており、以下順番にデータスロット１スロット毎、信号１ビットを対応ずけて割り当てている。
【００２９】
ＳＤＨの基本構造であるＳＴＭ−１に相当するフレーム構造（以下ＳＴＭー１フレームと呼ぶ）では、１．５４４Ｍｂ／ｓを最小のハンドリング単位としているため、伝送情報を一旦１．５４４Ｍｂ／ｓに対応するフレーム信号に変換した上で、ＳＴＭ−１フレームにマッピングする（多重化する）必要があったが、上記のように９タイムスロット毎のグループ化を行うことによって、この１グループの中の所定のデータスロット１個または複数個を利用する形を取ることができるので、６４Ｋｂ／ｓの伝送速度の信号を前記ＳＴＭ−１フレームに直接マッピングすることができる。
【００３０】
図５は、各種伝送速度の信号をＳＴＭ−１フレームのペイロードへ割付（マッピング）した例を示す。ここには、９タイムスロットを１単位としたブロック毎の桝目で区切った上に、１．５Ｍｂ／ｓ（以下１．５４４Ｍｂ／ｓ信号を１．５Ｍｂ／ｓと簡略して書く）の伝送速度の信号３回線分（１．５Ｍ−＃１、−＃２、−＃３）と６Ｍｂ／ｓの伝送速度の信号３回線分（６Ｍ−＃１、−＃２、−＃３）および６４Ｋｂ／ｓの伝送速度の信号８回線分（６４Ｋ×８）のマッピング状態を示している。
【００３１】
なお、図５の中の空欄部分は、ペイロード上のタイムスロット中、割り当てがされていない状態を示しているが、先に述べたように本発明に係るループ式データ伝送では６４Ｋｂ／ｓの伝送速度に相当するタイムスロットを１ビットとして表した９ビットを１単位としてグループ化し、処理するようにしたので、端末側からは、この６４Ｋｂ／ｓ×８ＣＨの中で、１ＣＨまたは複数ＣＨにインタフェースすることによって、直接ＳＴＭ−１フレームへの多重化が可能となる。なお、図５では１行目から詰めた割り当て例を示しているが、ＳＴＭ−１フレームの任意のスロットを使った結果途中に空きスロットが生じることがあっても問題は起きない。
【００３２】
次に具体的な割り当てと信号処理の例を説明する。例えばノード装置（Ｎ１）２の端末装置３とノード装置（Ｎ２）２の端末装置３の間で伝送速度１．５Ｍｂ／ｓの端末間通信が行われる場合では、この端末間通信用として、ＳＴＭ−１フレームのペイロードの１行目の最初の２７列のタイムスロット（図５の１．５Ｍ−＃１で示す領域、ブロック数では、３ブロック、タイムスロット数では２７）を割り当てる。ノード装置（Ｎ１）に接続された端末装置３からの１．５Ｍｂ／ｓの信号は、ノード装置２内の回線インタフェース部２５でパラレル信号に変換され、多重化／多重分離部２４の制御するタイミングで多重／分離バス２６へ出力される。多重化／多重分離部２４は、多重／分離バス２６へ出力されたデータを所定の時間保持したのち、図５の１．５Ｍ−＃１で示すペイロード上のタイムスロットにデータと付加情報を配置する。他に、ノード装置（Ｎ１）２から他のノード装置２へ伝送するデータが無ければ、ノード装置（Ｎ１）２の多重化／多重分離部２４では、１．５Ｍ−＃１以外のスロットへは、受信信号のＳＴＭ−１フレーム上の同じ位置にあるデータおよび信号（前記：多重化／多重分離部２４に一時保持）を乗せかえる。多重化された信号は、ＳＴＭ−１終端部２２でＳＯＨが付加され、光信号に変換されて、下流ノード装置２へ送信される。０系伝送路１０を使用して運用している場合は、ノード装置（Ｎ１）２からの信号はノード装置（Ｎ２）２へ送信される。
【００３３】
ノード装置（Ｎ２）２では、０系伝送路１０から受信した信号は、ＳＴＭ−１終端部２２でＳＯＨが取り除かれて、系選択回路部２３を経由して、多重化／多重分離部２４へ出力される。多重化／多重分離部２４では、予め割り当てられているＳＴＭ−１フレームのペイロードの割り当てられたスロット（図５−１．５Ｍ−♯１）のデータおよび信号を多重分離して抽出し、多重／分離バス２６を介して回線インタフェース部２５へ出力する。回線インタフェース部２５ではこの信号をシリアル信号に変換し、付加信号の状態にもとづいて端末へ出力する信号を生成して端末３へ出力する。このようにしてノード装置（Ｎ１）２に接続された端末装置３のデータがノード装置（Ｎ２）２に接続された端末装置３へ伝送される。逆に、ノード装置（Ｎ２）２に接続された端末装置３からの送信も上記と同じスロット（図５の１．５Ｍ−＃１）を使用して同様の手順を経て伝送される。
【００３４】
以上のように、ノード装置に、伝送路に伝送されるＳＤＨ方式の多重化フレーム信号にアクセスし、所定の信号が割り当てられているタイムスロットから信号を選択的に抽出して多重分離し前記端末装置に向けて送り出し、または前記端末装置からの信号を取り込んで前記多重化フレーム信号の割り当てられた所定タイムスロットへ選択的に配置して多重化し前記伝送路へ送り出す多重化／多重分離手段とを備えたので、６４Ｋｂ／ｓのような低い伝送速度の信号でも、段階的な多重化処理を行うことなく直接、ＳＴＭー１フレームへ多重化を行うことができる。
【００３５】
実施の形態２．
つぎに、この発明に係るループ式データ伝送装置の実施の形態２に係る多重化／多重分離部の詳細について説明する。実施の形態２は、実施の形態１における多重化／多重分離部２４を具体化したものの一つである。したがって、以下では多重化／多重分離部２４の構成とその関連事項に主眼を置いて説明する。
図６は多重化／多重分離部２４の構成図である。図において、２４０１は系選択回路部２３から入力したデータを中継して再度系選択回路部２３へ出力する迄の間一時的に保持する受信中継メモリ、２４０２は系選択回路２３から入力したデータを多重／分離バス２６へ出力するまでの間一時的に保持する分離メモリで、２４０３は受信中継メモリ２４０１および分離メモリ２４０２へのデータ書き込み制御を行うライト制御部、２４０４ａは多重／分離バス２６から入力したデータを系選択回路部２３へ出力するまでの間一時的に保持する多重メモリ、２４０５は多重／分離バス２６から入力したデータを再度多重／分離バス２６へ出力するまでの間一時的に保持する局内交換メモリ、２４０６は多重メモリ２４０４Ａおよび局内交換メモリ２４０５へのデータ書き込みを制御するライト制御部、２４０７は受信中継メモリ２４０１または多重メモリ２４０４Ａからデータを読み出すときのアドレス信号を生成するリード゛制御部、２４０８はリード制御部２４０７から出力される信号を予め設定されたアドレスに変換する多重メモリアドレス変換部、２４０９は受信中継メモリ２４０１のリードデータと多重メモリ２４０４Ａのリードデータを選択するセレクタ部、２４１０Ａは分離メモリ２４０２または局内交換メモリ２４０５からデータを読み出すときの基準信号等を生成するリード制御部、２４１１Ａはリード制御部２４１０Ａから出力される信号を予め設定されたアドレスに変換するための分離メモリアドレス変換部、２４１２は分離メモリ２４０２のリードデータと局内交換メモリ２４０５のリードデータを選択するセレクタ部、２４１３は多重／分離バス２６の基準信号および制御信号の生成を行う多重分離バス制御部である。
【００３６】
また、多重メモリアドレス変換部２４０８の構造を図７に示す。図７において、アドレスと記載されたもの（０００〜２０７９）は、多重アドレス変換部２４０８のアドレスを示し、ＳＴＭ−１フレームのペイロードのタイムスロット番号に対応する。ビットＤ１２は多重／中継ビットである。このＤ１２のビットが、“１”か“０”かにより、図６のセレクタ部２４０９に於いて選択する信号が決定され、“１”の場合には多重メモリ２４０４Ａからのリードデータを選択し、“０”の場合は受信中継メモリ２４０１からのリードデータを選択するようになっている。Ｄ１〜Ｄ１１には多重メモリ２４０４Ａのリードアドレス（Ａ１〜Ａ１１）が設定される。
【００３７】
分離メモリアドレス変換部２４１１Ａは、リード制御部２４１０Ａから出力される基準信号をもとに、分離メモリ２４０２および局内交換メモリ２４０５のリードアドレスを作成する機能を有しており、ＲＯＭや２ポートメモリで構成される。本例では２ポートメモリを用いており、ノード管理バス２８を介して内部データを設定変更することが可能になっている。
【００３８】
分離メモリアドレス変換部２４１１Ａの構造を図８に示す。図８において、アドレスと記載されたもの（０００〜２０７９）は分離メモリアドレス変換部２４１１Ａのアドレスを示し、多重／分離バス２６のアドレスに対応する。ビットＤ１６は局内／分離ビットであり、このＤ１６のビットが“１”か“０”かにより、図６のセレクタ部２４１２によって選択される信号が決定され、“１”の場合には局内交換メモリ２４０５からのリードデータを選択し、“０”の場合は分離メモリ２４０２のリードデータを選択するする。Ｄ１１〜Ｄ０には分離メモリ２４０２または局内交換メモリ２４０５からのリードアドレス（Ａ１１〜Ａ０）が設定される。また、Ｄ１７〜Ｄ２３はポートＩＤであり、多重分離バス２６を介して入出力するデータに対応する回線インタフェース部のポート番号が設定される。
【００３９】
次に図６、図７、図８に基ずき動作について説明する。系選択回路部２３から入力される信号は連続する複数のタイムスロットからなり、ブロック０のデータスロットＤ０に始まりブロック２５０の信号スロットを最後とする２３４０個のタイムスロットが順番に入力され、ライト制御部２４０３によって制御されて受信中継メモリ２４０１および分離メモリ２４０２へ順番に書き込まれる。
【００４０】
多重分離バス制御部２４１３は、多重／分離バス２６を介して、回線インタフェース部２５と入出力をするために必要な基準信号を生成しており、多重分離バス２６から入力される信号も、複数の連続するタイムスロットデータの構造を有する。そしてライト制御部２４０６によって制御されて多重メモリ２４０４Ａおよび局内交換メモリ２４０５へ順番に書き込まれる。
【００４１】
リード制御部２４０７はライト制御部２４０３の書き込み動作から少し遅れた位相でリードアドレスを生成する。このリードアドレスにもとづいて、受信中継メモリ２４０１にすでに書き込まれているデータが順番に読み出される。多重メモリアドレス変換部２４０８ではリード制御部２４０７からのリードアドレスにもとづいて多重メモリ２４０４のリードアドレスを生成し、このリードアドレスによって多重メモリ２４０４Ａにすでに書き込まれているデータを読み出す。受信中継メモリ２４０１および多重メモリ２４０４Ａから読み出されたデータはセレクタ２４０９で選択された後、系選択回路部２３へ出力される。この時、セレクタ部２４０９における選択は多重メモリアドレス変換部２４０８からの多重／中継ビットにもとづいて行われる。セレクタ部２４０９から系選択回路部２３へ出力されるデータは、ブロック０のデータスロットＤ０に始まり、ブロック２５０の信号スロットを最後とする２３４０個のタイムスロットが順番に出力される。以上のように動作しているので、系選択回路部２３へ出力するタイムスロットデータは、系選択回路部２３から入力したタイムスロットデータと多重／分離バス２６から入力したデータとの間で１タイムスロットの単位で入替えが可能である。
【００４２】
また、リード制御部２４１０Ａはライト制御部２４０６の書き込み動作から少し遅れた位相で基準信号を生成する。分離メモリアドレス変換部２４１１Ａでは、リード制御部２４１０Ａからの基準信号にもとづいて分離メモリ２４０２および局内交換メモリ２４０５のリードアドレスを生成する。このリードアドレスにもとづいて、分離メモリ２４０２および局内交換メモリ２４０５にすでに書き込まれているデータが読み出される。分離メモリ２４０２および局内交換メモリ２４０５から読み出されたデータはセレクタ部２４１２で選択され、多重／分離バス２６へ出力される。この時セレクタ部２４１２では分離メモリアドレス変換部２４１１Ａからの局内／分離ビット（図８参照）にもとづいて分離メモリ２４０２からのデータと局内交換メモリ２４０５からのデータの選択が行われる。セレクタ部２４１２から出力するデータは複数の連続するタイムスロットデータの構造を有している。以上のようにして、多重／分離バス２６へ出力するデータは系選択回路部２３から入力したタイムスロットのデータと多重／分離バス２６から入力したデータとの間で１タイムスロット単位での入替えが可能である。
【００４３】
また分離メモリアドレス変換部２４１１からは、多重分離バス２６を介して入出力するデータに対応する回線インタフェース部２５のポート番号が出力される。回線インタフェース部２５では多重分離バス２６上で固有のポート番号が予め設定されており、このポート番号が一致した回線のデータが多重分離バス２６を介して入出力される。
【００４４】
なお、ここでは、局内交換メモリを設けたものを示したが、局内交換が必要ない場合は設けなくてもよい。また信号スロットとデータスロットの取り扱いの詳細について説明を省略したが、受信中継メモリ、多重メモリ、分離メモリ、局内交換メモリは、データスロットと信号スロットとに対応する構成である事は言うまでもない。
【００４５】
さらに、多重分離バス２６を介してデータ他が入出力される様子を図９のタイミングチャートに示す。タイムスロット番号は、図６に示したリード制御部２４１０Ａから出力されるリードアドレスに相当する信号であり、多重分離バス２６に直接出力されていないが、このタイムスロット番号を基準として各信号の入出力が行われる。多重分離バス２６に出力される分離データ、分離信号およびポートＩＤはタイムスロット番号に対応して出力される。一方多重データと多重信号については、回線インタフェース部２５の側において、ポートＩＤの一致等の処理時間を必要とするため、バイトクロックで４．５クロックの時間差を設けている。
【００４６】
以上説明したように実施の形態２に係るループ式データ伝送装置では、伝送路からの受信信号と回線インタフェース部を経て端末装置からの信号とを保持する各メモリと、これらタイムスロット毎のデータを相互に入れ替えるための多重メモリアドレス変換部、分離メモリアドレス変換部およびセレクタを設けた構成としたので、１タイムスロット毎のデータの入替えが可能である。つまり、６４Ｋｂ／ｓを最小単位とするデータの入替えが可能である。また局内交換メモリを設けた構成としたので、ノード装置内で、局内交換可能である。また、多重メモリアドレス変換部および分離メモリアドレス変換部を２ポートメモリで構成し、ノード管理バスからの設定を可能にしたので、端末装置の増設や変更が必要な場合でも、ノード装置を稼動させたままオンライン変更が可能である。さらに分離アドレス変換部から回線インタフェース部のポート番号を出力する構成としたので、回線インタフェース部に特殊な設定機構を設けなくても複数のタイムスロットが使用出来る等、回線インタフェース部の回路構成を簡略化する事が可能である。
【００４７】
なお、上記実施の形態では局内交換メモリを設けたものを示したが局内交換が必要ない場合は設けなくてもよい、また、信号スロットとデータスロットの取り扱いの詳細につては説明を省略したが受信中継メモリ、多重メモリ、分離メモリ、局内交換メモリは、データスロットと信号スロットに対応する構成である事は言うまでもない。
【００４８】
実施の形態３．
つぎに、この発明に係るループ式データ伝送装置の実施の形態３に係る多重化／多重分離部の詳細について説明する。実施の形態３は、多重化／多重分離部２４を除き実施の形態１と同じ構成になっている。また、実施の形態２との関係では、多重化／多重分離部２４の一部の構成を変更している。
以上の関係を考慮して、以下では実施の形態３の多重化／多重分離部２４の構成について、実施の態様２からの変更部分を中心に説明する。
図１０は、実施の形態３に係る多重化／多重分離部２４の構成図である。図において、２４１０Ｂは分離メモリ２４０２または局内交換メモリ２４０５からのデータを読み出す時の基準信号と、多重分離バス２６を介して回線インタフェース部２５に多重分離バスアドレス信号を生成するリード制御部、１１１２はリード制御部１１０２から出力される信号を予め設定されたアドレスに変換する分離メモリアドレス変換部、である。なお、図６に付した符号と同じ符号のものまたは部分は、実施の形態２におけるものと基本的に同じ機能のものである。
【００４９】
また、図１１は実施の形態３に係る分離メモリアドレス変換部２４１１Ｂの構造である。なお、実施の形態３における多重メモリアドレス変換部２４０８の構造は図７と同様である。
【００５０】
次に動作を説明する。なお、系選択回路部２３から入力される信号を受信中継メモリ２４０１および分離メモリ２４０２へ書き込む動作、多重／分離バス２６から入力される信号を多重メモリ２４０４Ａおよび局内交換メモリ２４０５へ書き込む動作、受信中継メモリ２４０１からの読み出し動作とこれら読み出されたデータを選択して系選択回路部２３へ出力する動作については実施の形態２の場合と同じなので説明を省略する。
【００５１】
リード制御部２４１０Ｂはライト制御部２４０６の書き込み動作から少し遅れた位相で基準信号を生成する。分離メモリアドレス変換部２４１１Ｂではリード制御部２４１０Ｂからの基準信号から分離メモリ２４０２および局内交換メモリ２４０５のリードアドレスを出力し、このリードアドレスに基ずいて、すでに書き込まれたデータが読み出される。分離メモリ２４０２および局内交換メモリ２４０５から読み出されたデータはセレクタ部２４１２で選択され、多重／分離バス２６に出力される。この時セレクタ部２４１２では分離メモリアドレス変換部２４１１Ｂからの局内／分離ビットにもとづいて選択する。セレクタ部２４１２から出力するデータは複数の連続するタイムスロットデータの構造を有している。以上のようにして、系選択回路部２３から入力したタイムスロトデータと多重／分離バス２６から入力したデータとを入替えて、多重／分離バス２６へ出力することが可能となる。
【００５２】
また、リード制御部２４１０Ｂからは、多重／分離バス２６を介して入出力するデータに対応する多重分離アドレス信号が出力される。回線インタフェース部２５には使用するタイムスロット番号およびタイムスロット数に応じて対応する多重分離アドレスが予め設定されており、多重／分離バス２６上の多重分離バスアドレスが一致した回線のデータを多重／分離バス２６を介して入出力される。なお、ここでは、局内交換メモリを設けたものを示したが、局内交換が必要ない場合は設けなくてもよい。また信号スロットとデータスロットの取り扱いの詳細について説明を省略したが、受信中継メモリ、多重メモリ、分離メモリ局内交換メモリは、データスロットと信号スロットと対応する構成である事は言うまでもない。
【００５３】
以上説明したように、本実施の形態によるループ式データ伝送装置では、リード制御部から多重分離バスアドレス信号を出力し、予め回線インタフェース部に設定された多重分離バスアドレスと一致した回線のデータを多重分離バスを介して入出力する構成としたので、多重化／多重分離部の分離メモリアドレス変換部のメモリ容量の削減および分離メモリアドレス変換部への設定回数の削減が可能であるという効果が得られる。
【００５４】
実施の形態４．
つぎに、この発明に係るループ式データ伝送装置の実施の形態４に係る多重化／多重分離部の詳細について説明する。実施の形態４は、多重化／多重分離部２４を除き実施の形態２または実施の形態３と同じ構成になっている。また、実施の形態２または実施の形態３との関係では、多重化／多重分離部２４の一部の構成を変更している。
以上の関係を考慮して、以下では実施の態様４の多重化／多重分離部２４の構成について、実施の態様２または実施の形態３からの変更部分を中心に説明する。図１２は、実施の形態４に係る多重化／多重分離部２４の構成図である。図において２４０４Ｂは多重／分離バス２６から入力したデータを系選択回路部２３へ出力する迄の期間一時的に保持するとともに多重／分離バス２６からのデータ多重要求信号を前記データと同様保持する多重メモリ、２４１４は多重メモリアドレス変換部２４０８から出力される多重／中継ビットと多重メモリ２４０４Ｂから出力されるデータ多重要求信号の論理積をとるＡＮＤゲートである。なお、他の部分の構成は実施の形態２または、実施の形態３と基本的に同じであるので説明は省略する。
【００５５】
次に動作について説明する。なお、系選択回路部２３から入力される信号を受信中継メモり２４０１および分離メモリ２４０２へ書き込む動作、分離メモリ２４０３からの読み出し動作、局内交換メモリ２４０５からの読み出し動作とこれら読み出されたデータを選択して多重分離バス２６へ出力する動作については、実施の形態１と基本的に同じである。
【００５６】
多重分離バス制御部２４１３は多重／分離バス２６を介して回路インタフェース部２５と入出力するために必要な基準信号を生成しており、多重／分離バス２６から入力される信号も複数の連続するタイムスロットデータの構造を有する。そしてライト制御部２４０６によって制御されて多重メモリ２４０４Ｂおよび局内交換メモリ２４０５へ順番に書き込まれる。このとき、多重メモリ２４０４Ｂへは多重データ／多重信号およびデータ多重要求信号が書き込まれ、局内交換メモリ２４０５へは多重データ／多重信号が書き込まれる。
【００５７】
リード制御部２４０７はライト制御部２４０３の書き込み動作から少し遅れた位相でリードアドレスを作成する。このリードアドレスに基ずいて受信中継メモリ２４０１からはすでに書き込まれたタイムスロットデータが順番に読み出される。多重メモリアドレス変換部２４０８では、リード制御部２４０７からのリードアドレス多重メモリ２４０４Ｂのリードアドレスを出力し、このリードアドレスにもとづいて書き込まれたデータが読み出される。受信中継メモリ２４０１および多重メモリ２４０４Ｂから読み出されたデータはセレクタ部２４０９で選択され、系選択回路部２３へ出力される。また多重メモリ２４０４Ｂからデータが読み出されると同時にデータ多重要求信号が読み出される。このデータ多重要求信号は多重メモリアドレス変換部２４０８からの多重／中継ビットとＡＮＤゲート２４１４にて論理積がとられる。そして、ＡＮＤゲート２４１４の出力はセレクタ２４０９へ接続されており、セレクタ部２４０９ではＡＮＤ条件成立時すなわち、データ多重要求信号が論理“１“でかつ多重／中継ビットが論理”１“の時のみ多重メモリ２４０４Ｂからのデータを選択する。セレクタ部２４０９はＡＮＤ条件が成立しない場合は、受信中継メモリ２４０１のデータを選択する。そして、セレクタ部２４０９から系選択回路２３へ出力される。なお、上記実施の形態では局内交換メモリを設けたものを示したが、局内交換が必要でない場合は設けなくてもよい。また、信号スロットとデータスロットの取り扱いの詳細につては説明を省略したが受信中継メモリ、多重メモリ、分離メモリ、局内交換メモリは、データスロットと信号スロットに対応する構成であることは言うまでもない。
【００５８】
以上説明したように、本実施の形態によるループ式データ伝送装置はデータ多重要求信号を設け、多重メモリへデータとともにデータ多重要求信号を書き込むように構成し、さらに多重メモリ及び受信中継メモリから読み出したデータを選択するとき、多重中継ビットとデータ多重要求信号のＡＮＤ条件で多重メモリのデータを選択するようにしたので、ノード装置の初期化が完了していない場合でも不正データを多重する事を防止できる。その結果、ノード装置に接続された端末へ不正なデータを送信する事が防止できる効果がある。
【００５９】
実施の形態５．
つぎに、この発明に係るループ式データ伝送装置の実施の形態５に係る多重化／多重分離部の詳細について説明する。実施の形態５は、多重化／多重分離部２４を除き実施の形態２と同じ構成になっている。また、実施の形態２との関係では、多重化／多重分離部２４の一部の構成を変更している。
以上の関係を考慮して、以下では実施の形態３の多重化／多重分離部２４の構成について、実施の形態２からの変更部分を中心に説明する。
図１３において、２４１６はノード管理プロセッサ部２７がノード管理バス２８を介して多重化／多重分離部２４へ初期化が完了したことを指示し保持しておくための初期化完了フリップフロップ回路、２４１５は多重メモリアドレス変換部２４０８から出力される多重／中継ビットと初期化完了フリップフロップ回路２４１６の出力の論理積をとるＡＮＤゲート、である。また、多重メモリアドレス変換部２４０８の構造は図７と同様であり、分離メモリアドレス変換部２４１１Ａの構造は図９と同様である。
【００６０】
次に動作について説明する。なお、系選択回路部２３から入力される信号を受信中継メモリ２４０１および分離メモリ２４０２へ書き込む動作、多重分離バスから入力される信号を多重メモリ２４０４および局内交換メモリ２４０５へ書き込む動作、さらに分離メモリ２４０２からの読み出し動作、局内交換メモリ２４０５からの読み出し動作とこれから読み出されたデータを選択して多重分離バス２６へ出力する動作については実施の形態１と同じである。
【００６１】
ノード管理プロセッサ部２７は、ノード装置を立ちあげる際にはノード装置２の各部を初期化する。その一連の処理の一つとして、多重化／多重分離部２４の多重メモリアドレス変換部２４０８、分離メモリアドレス変換部２４１１ａの初期設定を行う。初期化完了フリップフロップ回路２４１６はノード装置２へ電源を投入した直後など初期化完了以前はリセットされた状態でであり、その出力は論理“１”である。そしてノード管理プロセッサ部２７は前記初期化設定が完了した時点で、初期化完了フリップフロップ回路２４１６をセットする。そしてその出力は論理“１”となる。
【００６２】
受信中継メモリ２４０１および多重メモリ２４０４から読み出されたデータはセレクタ部２４０９で選択された後系選択回路部２３へ出力されるが、この選択条件として、前記初期化完了フリップフロップ回路２４１６の出力と多重メモリアドレス変換部２４０８からの多重／中継ビットとがＡＮＤゲート２４１５にて論理積がとられる。そして、ＡＮＤゲート２４１５の出力はセレクタ部２４０９へ接続されており、セレクタ部２４０９ではＡＮＤ条件成立時、すなわち初期化完了フリップフロップ回路２４１６の出力が論理“１”で、かつ多重／中継ビットが論理“１”のときのみ、多重メモリ２４０４からのデータを選択する。セレクタ部２４０９はＡＮＤ条件が成立しない場合は受信中継メモリ２４０１のデータを選択する。そしてセレクタ部２４０９から系選択回路部２３へ出力される。なお、上記実施例では局内交換メモリを設けたものを示しているが、局内交換が必要でない場合は設けなくてもよい。また、信号スロットとデータスロットの取り扱いの詳細につては説明を省略したが受信中継メモリ、多重メモリ、分離メモリ、局内交換メモリは、データスロットと信号スロットに対応する構成である事は言うまでもない。
【００６３】
以上説明したように、本実施の形態５によるループ式データ伝送装置は初期化完了フリップフロップを設け多重メモリ及び受信中継メモリから読み出したでデータを選択するとき、多重／中継ビットと初期化完了フリップフロップの出力信号のＡＮＤ条件で多重メモリのデータを選択するようにしているので、例えばノード装置の初期化が完了していない場合でも不正データを多重する事を防止できる。その結果、ノード装置に接続された端末へ不正なデータを送信する事が防止できる効果がある。
【００６４】
【発明の効果】
この発明は、以上説明したように構成されているので、以下に示すような効果を奏する。
【００６５】
伝送路に伝送されるＳＤＨ方式の多重化フレーム信号にアクセスして多重化フレームの所定のタイムスロットから信号を選択的に抽出して多重分離し、または端末装置からの信号を取り込んで前記多重化フレーム信号の所定タイムスロットへ選択的に配置して多重化するように構成したので、伝送速度の低い信号でも段階的な多重化処理を行うことなく直接、ＳＴＭー１フレームへアクセスして多重化を行える効果がある。
【００６６】
また、伝送路からの受信データ信号と回線インタフェース部を経て端末装置から送り込まれる多重データを保持する各メモリと、これらの信号のタイムスロット毎のデータを相互に入れ替えるための多重メモリアドレス変換部、分離メモリアドレス変換部およびセレクタを設けた構成としたので、１タイムスロット毎のデータの入替えが可能となり、ノード装置で直接低速信号（６４Ｋｂ／ｓ）のデータの多重化／多重分離を行える効果がある。
また、端末装置からのデータのタイムスロットを別のタイムスロットへ入れ替える事が出来る構成としたので、ノード装置内で局内交換を行う事が出来る効果がある。
【００６７】
また、多重メモリアドレス変換部および分離メモリアドレス変換部を２ポートメモリで構成し、ノード管理バスからの設定を可能にしたので、端末装置の増設や変更が必要な場合でも、ノード装置を稼動させたままオンラインで増設や変更が可能である。
【００６８】
さらに、分離アドレス変換部から回線インタフェースのポート番号を出力する構成としたので、回線インタフェース部に特殊な設定機構を設けなくても複数のタイムスロットが使用出来、回線インタフェースの回路構成を簡略化する事が可能である。
【００６９】
また、リード制御部からの多重分離バスアドレス信号にもとづいて、多重／分離バスを介してデータを入出力する構成としたので、多重化／多重分離部の分離メモリアドレス変換部のメモリ容量の削減および分離メモリアドレス変換部への設定回数の削減が可能となる効果が得られる。
【００７０】
さらに、データ多重要求信号の存在する事を条件としてデータの送り出し制御をするように構成したので、回線インタフェース部にトラブルがあるときにノード装置に接続された端末へ不正なデータを送信する事が防止できる効果がある。
【００７１】
さらに、ノード装置の初期化完了情報にもとづいてデータの送り出しを制御するように構成したので、初期化完了前の不正データが送信されるのを防止できる効果がある。
【図面の簡単な説明】
【図１】この発明に係るループ式データ伝送装置の構成図である。
【図２】この発明の実施の形態１にかかるループ式データ伝送装置のノード装置の構成図である。
【図３】この発明のノード装置間で使用される（９つのタイムスロットを１ブロックとしてブロック化したブロック化構成の）ＳＴＭ−１フレームのペイロード部分の構成図である。
【図４】図３に示すブロック化信号の構成を示す図である。
【図５】ＳＴＭ−１フレーム信号のペイロード部分へのマッピングを説明する図である。
【図６】この発明の実施の形態２に係るループ式データ伝送装置のノード装置に使われる多重化／多重化分離部の構成図である。
【図７】この発明の実施の形態２の多重アドレス変換部の構造を示す図である。
【図８】この発明の実施の形態２の分離アドレスメモリの構造を示す図である。
【図９】この発明の実施の形態２の多重分離バスのタイミングチャートである。
【図１０】この発明の実施の形態３に係るループ式データ伝送装置のノード装置に使われる多重化／多重化分離部の構成図である。
【図１１】この発明の実施の形態３の多重アドレス変換部の構造を示す図である。
【図１２】この発明の実施の形態４に係るループ式データ伝送装置のノード装置に使われる多重化／多重化分離部の構成図である。
【図１３】この発明の実施の形態５に係るループ式データ伝送装置のノード装置に使われる多重化／多重化分離部の構成図である。
【図１４】従来のループ式伝送装置の構成図である。
【図１５】従来のループ式伝送装置のノード装置の構成図である。
【図１６】従来のループ式伝送装置のノード装置の多重化構造を説明する図である。
【図１７】ＳＤＨのＳＴＭ−１フレーム構成の説明図である。
【符号の説明】
１伝送路、１００系伝送路、１１１系伝送路、
２ノード装置、
２０ａＡ系ＳＴＭ−１終端部、２０ｂＢ系ＳＴＭ−１終端部、
２１信号変換部、
２１１光／電気変換回路、２１２電気／光変換回路、
２２ＳＴＭ−１終端部、
２３系選択回路部、２４多重化／多重分離部、
２５回線インタフェース部、２６多重分離バス、
２７ノード管理プロセッサ部、２８ノード管理バス
３端末装置、
２４０１受信中継メモリ部、２４０２分離メモリ、
２４０３ライト制御部、２４０４Ａ多重メモリ、
２４０４ｂ多重メモリＢ、２４０５局内交換メモリ、
２４０６ライト制御部、２４０７リード制御部、
２４０８多重メモリアドレス変換部、２４０９セレクタ部、
２４１０リード制御部、２４１１Ａ分離アドレス変換部、
２４１１Ｂ分離アドレス変換部、２４１２Ａセレクタ部、
２４１２Ｂセレクタ部、２４１３多重分離バス制御部、
２４１４ＡＮＤ回路、２４１５ＡＮＤ回路、
２４１６初期化完了ＦＦ回路。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a loop-type data transmission device in which a plurality of node devices are connected to a loop transmission path and data is transmitted between terminal devices connected to each node device. (Hierarchy) and a loop-type data transmission apparatus having a frame structure.
[0002]
[Prior art]
FIG. 14 is a configuration diagram of a loop-type data transmission system using the SDH system disclosed in, for example, Japanese Patent Application Laid-Open No. 5-268235. In the figure, N1 to N6 are node devices, and 91 is a terminal device connected to these node devices. Reference numeral 10 denotes a 0-system transmission line, and 11 denotes a 1-system transmission line, which is a double loop transmission line. Note that the signal on the transmission path employs an SDH frame structure applied to high-speed digital signals.
[0003]
FIG. 15 is a configuration diagram of the node devices N1 to N6. Each node device has the same configuration. In FIG. 15, those having the same reference numerals as those in FIG. 14 indicate those having the same functions. Reference numeral 50 denotes a 0-system transmission line interface, and 51 denotes a 1-system transmission line interface, each of which includes a receiving circuit and a transmission circuit, and interfaces between the 0-system and 1-system loop transmission lines and the loopback circuit 71. Reference numeral 71 denotes a loopback circuit that performs loopback switching, 72 denotes a multiplexing / multiplexing / demultiplexing unit that performs signal multiplexing or demultiplexing, and 6 denotes a node that controls a switching operation between the loopback circuit 71 and the multiplexing / multiplexing / demultiplexing unit 72. The control circuit 8 is a line interface that controls an interface function between the terminal device 91 and the multiplexing / demultiplexing unit 72.
[0004]
FIG. 16 shows a multiplexed frame structure of STM-1, which is the basic structure of SDH. The STM-1 is configured to have a time slot of 9 columns and 270 rows in one frame of 125 μs (basic cycle of audio information encoding). Here, one time slot has a transmission capacity equivalent to 64 Kb / s. Therefore, the transmission capacity of STM-1 is 155.52 Mb / s.
[0005]
The structure of a multiplexed frame is expressed by the number of rows and columns in byte units. This means that at high speeds, the number of bits increases, and it is not possible to write over one horizontal column, and overhead signals used for network management are used. This is for the purpose of intensively arranging to make it easier to see. In the STM-1 frame structure, the ninth and subsequent 261 columns are time slots for storing various types of information, and are called payloads. Note that the example illustrated in FIG. 16 includes three sets of virtual containers VC-3, and a path overhead (POH) which is a monitoring signal of the container is arranged at the head of the virtual containers VC-3. On the other hand, the first 9 rows × 9 columns are allocated to a section overhead (SOH) for accommodating network management information when transmitting various information and a pointer for designating a head position of multiplexed information contained in the payload. Have been. Multiplexing to STM-1, which is the basic configuration of SDH, is performed in units of a standardized transmission capacity called a virtual container (VC). The virtual container is prepared so that various types of information including existing low-speed information can be multiplexed. The minimum handling unit is 1.544 Mb / s (64 Kb / s, corresponding to 24 channels). In FIG. 16, the frame of the virtual container VC-3 to be multiplexed is shifted from the payload to represent the change in the time phase of the STM-1 and the frame phase of the VC-3. .
[0006]
FIG. 17 shows a multiplexing structure standardized by TTC (Telecommunications Telecommunications Commission). As can be seen from the figure, the STM-1 frame structure is constructed by stacking containers (C-1, C-2, C-3, C-4) having various transmission capacities. Is a C1 (1.544 Mb / s) container. That is, the minimum handling capacity of STM-n is 1.544 Mb / s.
[0007]
Next, the operation will be described. The received signal input from the 0-system transmission line 10 is input to the 0-system transmission line interface 50, converted into a digital signal, guided to the loopback circuit 71, and further subjected to signal selection by control according to the operation state of the transmission device. Then, it is guided to the multiplexing / demultiplexing unit 72. The multiplexing / demultiplexing unit 72 demultiplexes the multiplexed data based on the SDH multiplexing structure, and among the data, the data mapped to the time slot position on the frame allocated in advance to each terminal device 91. Is output to the terminal interface 8 and other data is temporarily stored. On the other hand, a signal from the terminal device 91 is converted into a digital signal by the line interface device 8 and passed to the multiplexing / demultiplexing unit 72. The multiplexing / multiplexing / demultiplexing section 72 maps the signal to a predetermined time slot position for each terminal device 91 and multiplexes the signal with the signal temporarily stored in the multiplexing / multiplexing / demultiplexing section 72 to form a loopback circuit. It is sent to the 0-system transmission line 10 via the 71 and 0-system transmission line interface 50.
[0008]
[Problems to be solved by the invention]
The conventional loop transmission apparatus is configured as described above, and performs multiplexing and demultiplexing in stages. However, the standard of the multiplexing structure of SDH specifies only a high-speed signal of 1.544 Mb / s or higher. Therefore, when multiplexing / demultiplexing a low-speed signal, for example, a signal of 64 Kb / s, a multiplex conversion is performed once from 64 Kb / s to 1.544 Kb / s by another device, and this signal is converted to a node. It had to be connected to the multiplexing / demultiplexing part of the device. For this reason, there has been a problem that the configuration is complicated.
[0009]
Furthermore, in a conventional loop transmission apparatus using a signal of the SDH frame structure, a time slot is allocated in units of a transmission speed of at least 1.544 Mb / s. Even if the transmission speed is, for example, 64 Kb / s, a time slot for 1.544 Mb / s, which is the minimum handling capacity, is allocated, and there is a problem that the line use efficiency is very poor.
[0010]
The present invention has been made to solve such a problem, and a first object of the present invention is to directly perform STM-multiplexing even for a low-speed signal such as a transmission speed of 64 Kb / s without stepwise multiplexing. A second object is to multiplex the data into one frame to simplify the configuration and improve the efficiency of use of the line. The second object is to allow the position of the time slot on the multiplexed frame to be replaced in units of time slot, and The third object is to enable the intra-office exchange of the multiplexed frame and to set the assignment of the time slot position on the multiplexed frame even while online. A fourth object of the present invention is to simplify the configuration of the multiplexing / demultiplexing unit. In the event that a line interface unit fails or there is no line interface unit, incorrect data is transmitted from a terminal. Possible to prevent the that, fifth object is that incorrect if the initial setting of the multiplexing / demultiplexing unit is not complete data is prevented from being transmitted from the terminal, and so on.
[0011]
[Means for Solving the Problems]
A loop-type data transmission apparatus according to the present invention includes a loop-shaped transmission path including a first transmission path for transmitting a digitized multiplexed signal in a predetermined direction and a second transmission path for transmitting a digitized multiplexed signal in a direction opposite to the predetermined direction. A plurality of terminal devices that exchange signals with each other through a loop-shaped transmission path, and are arranged in the middle of the transmission path and extract signals of predetermined time slots from signals transmitted to the transmission path. In a loop-type data transmission device comprising a node device for demultiplexing and sending the signal to the terminal device, or taking in a signal from the terminal device and multiplexing the signal, and sending the signal to the transmission line, the node device uses an SDH system transmitted to the transmission line. Access to the multiplexed frame signal, selectively extract the signal from the assigned time slot, demultiplex and send it to the terminal device, or send the signal from the terminal device A multiplexing / multiplexing / demultiplexing unit for selectively arranging and multiplexing the data into the assigned time slot and sending the multiplexed / multiplexed data to the transmission line. A relay memory for temporarily storing the data until the data is transmitted to the terminal, a multiplex memory for temporarily storing the digital multiplexed signal for multiplexing sent from the terminal device, and a content read from the multiplex memory. The designation of the address of the time slot on the multiplexed frame for partial replacement, the multiplex memory address converter for generating a signal for controlling the replacement, and the multiplexing of the contents of the reception relay memory and the contents of the multiplex memory. And a selector unit for switching based on control from the memory address conversion unit. Those that made it possible to place.
[0012]
Further, the loop type data transmission apparatus according to the present invention has a loop-like configuration including a first transmission path for transmitting a digitized optical multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized optical multiplexed signal in a direction opposite to the predetermined direction. A transmission path, a plurality of terminal devices that exchange signals with each other via the loop transmission path, and a predetermined one of multiplexed frame signals arranged in the loop transmission path and transmitted to the transmission path. A node device that extracts a time slot signal and demultiplexes it and sends it out to the terminal device, or takes in a signal from the terminal device and places it in a predetermined time slot of the multiplexed frame signal, multiplexes it, and sends it out to the transmission path; Wherein the node device converts an optical signal from the first transmission line into an electric signal and guides the signal to an internal circuit of the node device. A first terminal for converting the electric signal into an optical signal and sending it out to the second transmission line; converting the optical signal from the second transmission line into an electric signal to guide the signal to an internal circuit of the node device; A second terminal for converting an electric signal from an internal circuit into an optical signal and sending the signal to a first transmission line; and a signal from one of the first or second transmission lines set in advance. A system selecting circuit for selecting and taking in and transmitting a signal to the other transmission path in the same direction or one transmission path in the same direction; and a predetermined time slot of a multiplexed frame signal by transmitting a transmission signal from the terminal device. A multiplexing / demultiplexing unit that performs multiplexing by arranging the multiplexing signal at a position and extracting a transmission signal from a predetermined time slot position of the multiplexed frame signal sent from the system selection circuit to perform demultiplexing; And multiplexing A multiplexing / demultiplexing bus for transferring signals between the multiplexing / demultiplexing unit and the terminal device; a line interface unit for interfacing between the terminal device and the multiplexing / demultiplexing bus; A multiplexing / multiplexing / demultiplexing unit that temporarily stores the digital reception signal from the transmission path until the signal is transmitted to the transmission path again; A multiplex memory for temporarily storing the received digital multiplex signal for multiplexing, and a time slot on a multiplex frame for partially replacing the content read from the reception relay memory with the content read from the multiplex memory. A multiplex memory address converter for generating an address designation and a signal for controlling the exchange, the contents of the reception relay memory and the multiplex memory And a selector unit for switching the contents of the digitally-received relay signal and the digitally multiplexed signal based on the control from the multiplex memory address conversion unit.
[0013]
Also, a loop-type data transmission apparatus according to the present invention provides a loop-like transmission comprising a first transmission path for transmitting a digitized multiplexed signal in a predetermined direction and a second transmission path for transmitting a digitized multiplexed signal in a direction opposite to the predetermined direction. And a plurality of terminal devices that exchange signals with each other via a loop-shaped transmission path, and extract a signal of a predetermined time slot from signals transmitted on the transmission path, which are arranged in the middle of the transmission path. And multiplexing and demultiplexing and sending the signal to the terminal device, or a node device that receives and multiplexes a signal from the terminal device and sends the multiplexed signal to a transmission line, wherein the node device transmits the signal to the transmission line. The multiplexed frame signal of the SDH system is accessed, the signal is selectively extracted from the assigned time slot, demultiplexed, and sent out to the terminal device or the terminal device. And a multiplexing / demultiplexing unit for selectively arranging signals in the assigned time slots, multiplexing the signals, and sending the multiplexed signals to a transmission line. The multiplexing / demultiplexing unit converts the digital reception signal from the transmission line into a digital signal. A reception relay memory for temporarily storing data until the signal is transmitted to the transmission path again, a multiplex memory for temporarily storing a digital multiplexed signal for multiplexing sent from the terminal device, and a content read from the multiplex memory read from the reception relay memory. The address of a time slot on the multiplexed frame of the part to be replaced with the contents to be replaced, a multiplex memory address conversion unit for generating a signal for controlling the replacement, and the contents of the receiving relay memory and the contents of the multiplex memory in the multiplex memory. A selector section that switches based on control from an address translation section, and a temporary storage section for demultiplexing a digital reception signal. Memory, a local exchange memory for temporarily storing a digital multiplexed signal for multiplexing sent from the terminal device, and a multiplexing part for replacing the contents read from the local exchange memory with the contents read from the separate memory. Specification of the address of a time slot on a frame, a separate memory address converter for generating a signal for controlling the exchange, and switching between the contents of the separate memory and the contents of the intra-office exchange memory based on control from the separate memory address converter. It has a selector, and enables intra-office exchange by exchanging digital reception signals and digital multiplexed signals, and exchanging the contents of the separation memory and the contents of the intra-exchange memory.
[0014]
Further, the loop type data transmission apparatus according to the present invention has a loop-like configuration including a first transmission path for transmitting a digitized optical multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized optical multiplexed signal in a direction opposite to the predetermined direction. A transmission path, a plurality of terminal devices that exchange signals with each other via the loop transmission path, and a predetermined one of multiplexed frame signals arranged in the loop transmission path and transmitted to the transmission path. A node device that extracts a time slot signal and demultiplexes it and sends it out to the terminal device, or takes in a signal from the terminal device and places it in a predetermined time slot of a multiplexed frame signal, multiplexes it and sends it out to the transmission line. In the loop-type data transmission device, the node device converts an optical signal from the first transmission line into an electric signal, guides the signal to an internal circuit of the node device, and outputs the signal from the internal circuit of the node device. A first terminator for converting an electric signal into an optical signal and sending it to the second transmission path; converting a light signal from the second transmission path into an electric signal to guide the signal to an internal circuit of the node device; A second terminal for converting an electric signal from the internal circuit into an optical signal and sending it to the first transmission line, and selecting a signal from one of the first or second transmission lines set in advance; And a system selection circuit for transmitting a signal to the other transmission line in the same direction or one transmission line in the same direction, and a transmission signal from the terminal device in a predetermined time slot position of a multiplexed frame signal. A multiplexing / demultiplexing unit that performs multiplexing by arranging the multiplexed frame signal and extracting a transmission signal from a predetermined time slot position of the multiplexed frame signal sent from the system selection circuit to perform demultiplexing; Multiplexed / A multiplexing / demultiplexing bus for transferring signals between the demultiplexing unit and the terminal device; a line interface unit for interfacing between the terminal device and the multiplexing / demultiplexing bus; A multiplexing / multiplexing / demultiplexing unit that temporarily stores the digital reception signal from the transmission path until the signal is transmitted to the transmission path again; A multiplexing memory for temporarily storing a digital multiplexed signal for multiplexing to be sent; and designation of an address of a time slot on a multiplexing frame of a portion for replacing the content read from the multiplexing memory with the content read from the receiving relay memory. A multiplex memory address conversion unit for generating a signal for controlling the switching, and the contents of the reception relay memory and the contents of the multiplex memory are multiplexed. A selector unit that switches based on control from a double memory address conversion unit, a separation memory that temporarily stores digital signals for demultiplexing, and a digital memory that temporarily stores digital multiplexed signals sent from a terminal device for multiplexing. Designation of an address of a time slot on a multiplexed frame of a part for replacing the contents read from the intra-office exchange memory with the contents read from the departure memory, and a separation memory address for generating a signal for controlling this exchange A conversion unit, and a selector for switching between the contents of the separation memory and the contents of the intra-office exchange memory based on the control from the separation memory address conversion unit, replacing the digital reception signal and the digital multiplexed signal, and the contents of the separation memory. And allows intra-office exchange by exchanging the contents of the intra-office exchange memory.
[0015]
Also, a loop-type data transmission apparatus according to the present invention provides a loop-like transmission comprising a first transmission path for transmitting a digitized multiplexed signal in a predetermined direction and a second transmission path for transmitting a digitized multiplexed signal in a direction opposite to the predetermined direction. And a plurality of terminal devices that exchange signals with each other via a loop-shaped transmission path, and extract a signal of a predetermined time slot from signals transmitted on the transmission path, which are arranged in the middle of the transmission path. In a loop-type data transmission device comprising a node device that demultiplexes and sends the signal to the terminal device, or multiplexes the signal from the terminal device and sends the signal to the transmission path,
The node device accesses the multiplexed frame signal of the SDH system transmitted to the transmission path, selectively extracts the signal from the assigned time slot, demultiplexes the signal, and sends out the signal to the terminal device, or And a multiplexer / demultiplexer for selectively arranging the signals in the assigned time slots, multiplexing the signals, and sending out the multiplexed signals to the transmission line. It has a memory address converter and a separate address converter, and a node management processor for setting these memories via a node management bus.
[0016]
Further, the loop type data transmission apparatus according to the present invention has a loop-like configuration including a first transmission path for transmitting a digitized optical multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized optical multiplexed signal in a direction opposite to the predetermined direction. A transmission path, a plurality of terminal devices that exchange signals with each other via the loop transmission path, and a predetermined one of multiplexed frame signals arranged in the loop transmission path and transmitted to the transmission path. A node device that extracts a time slot signal and demultiplexes it and sends it out to the terminal device, or takes in a signal from the terminal device and places it in a predetermined time slot of the multiplexed frame signal, multiplexes it, and sends it out to the transmission path; Wherein the node device converts an optical signal from the first transmission line into an electric signal, guides the signal to an internal circuit of the node device, and transmits the signal to the internal circuit of the node device. A first terminal for converting the electric signal into an optical signal and sending the signal to the second transmission line, and converting the optical signal from the second transmission line into an electric signal to guide the signal to an internal circuit of the node device, and A second terminator for converting an electric signal from an internal circuit of the device into an optical signal and sending it to the first transmission line, and a signal from one of the first or second transmission lines set in advance; And a system selection circuit for transmitting a signal to the other transmission path in the same direction or one transmission path in the same direction, and a transmission signal from the terminal device for a predetermined time of a multiplexed frame signal. A multiplexing / multiplexing / demultiplexing unit that performs multiplexing by arranging at a slot position, extracts a transmission signal from a predetermined time slot position of the multiplexed frame signal sent from the system selection circuit, and performs demultiplexing. Composed of signal paths and multiplexed Multiplexing / demultiplexing bus for transferring signals between the multiplexing / demultiplexing unit and the terminal device, a line interface unit interfacing between the terminal device and the multiplexing / demultiplexing bus, and each device in the node via the node management bus. A multiplexing / multiplexing / demultiplexing unit configured to manage an operation state; a multiplexing / multiplexing / demultiplexing unit configured by a two-port memory; And a node management processor unit that performs
[0017]
Also, a loop-type data transmission apparatus according to the present invention provides a loop-like transmission comprising a first transmission path for transmitting a digitized multiplexed signal in a predetermined direction and a second transmission path for transmitting a digitized multiplexed signal in a direction opposite to the predetermined direction. And a plurality of terminal devices that exchange signals with each other via a loop-shaped transmission path, and extract a signal of a predetermined time slot from signals transmitted on the transmission path, which are arranged in the middle of the transmission path. In the loop-type data transmission device comprising a node device that multiplexes and demultiplexes and sends the signal to the terminal device or fetches and multiplexes a signal from the terminal device and sends the signal to the transmission line, the node device is transmitted to the transmission line. Multiplexed frame signal of the SDH system, and selectively extracts a signal from an assigned time slot, demultiplexes the signal, and sends out the signal to the terminal device. And a multiplexer / demultiplexer for selectively arranging the signals in the assigned time slots, multiplexing the signals, and sending the multiplexed signals to the transmission line. Means for assigning a port number corresponding to the port number of the multiplexing / demultiplexing bus to the input signal to the multiplexing / demultiplexing bus, and using a unique port number assigned to the input signal to the multiplexing / demultiplexing bus, The signal is extracted by the line interface unit.
Further, the loop type data transmission apparatus according to the present invention has a loop-like configuration including a first transmission path for transmitting a digitized optical multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized optical multiplexed signal in a direction opposite to the predetermined direction. A transmission path, a plurality of terminal devices that exchange signals with each other via the loop transmission path, and a predetermined one of multiplexed frame signals arranged in the loop transmission path and transmitted to the transmission path. A node device that extracts a time slot signal and demultiplexes it and sends it out to the terminal device, or takes in a signal from the terminal device and places it in a predetermined time slot of a multiplexed frame signal, multiplexes it and sends it out to the transmission line. In the loop-type data transmission device, the node device converts an optical signal from the first transmission line into an electric signal, guides the signal to an internal circuit of the node device, and outputs the signal from the internal circuit of the node device. A first terminator for converting an electric signal into an optical signal and sending it to the second transmission path; converting a light signal from the second transmission path into an electric signal to guide the signal to an internal circuit of the node device; A second terminal for converting an electric signal from the internal circuit into an optical signal and sending it to the first transmission line, and selecting a signal from one of the first or second transmission lines set in advance; And a system selection circuit for transmitting a signal to the other transmission line in the same direction or one transmission line in the same direction, and a transmission signal from the terminal device in a predetermined time slot position of a multiplexed frame signal. A multiplexing / demultiplexing unit that performs multiplexing by arranging the multiplexed frame signal and extracting a transmission signal from a predetermined time slot position of the multiplexed frame signal sent from the system selection circuit to perform demultiplexing; Multiplexed / Multiplexing / demultiplexing bus for transferring signals between the demultiplexing unit and the terminal device, a line interface unit interfacing between the terminal device and the multiplexing / demultiplexing bus, and operation of each device in the node via the node management bus A multiplexing / demultiplexing unit for assigning a port number corresponding to a unique port number assigned to each line interface unit to an input signal to the multiplexing / demultiplexing bus. Means for extracting a signal on the multiplexing / demultiplexing bus by a line interface unit based on a unique port number assigned to an input signal to the multiplexing / demultiplexing bus.
[0018]
Also, a loop-type data transmission apparatus according to the present invention provides a loop-like transmission comprising a first transmission path for transmitting a digitized multiplexed signal in a predetermined direction and a second transmission path for transmitting a digitized multiplexed signal in a direction opposite to the predetermined direction. And a plurality of terminal devices that exchange signals with each other via a loop-shaped transmission path, and extract a signal of a predetermined time slot from signals transmitted on the transmission path, which are arranged in the middle of the transmission path. In a loop-type data transmission device including a node device that multiplexes and demultiplexes and sends the signal to the terminal device, or fetches and multiplexes a signal from the terminal device and sends the signal to the transmission line, the node device is transmitted to the transmission line. Multiplexed frame signal of the SDH system, and selectively extracts a signal from an assigned time slot, demultiplexes the signal, and sends out the signal to the terminal device. And a multiplexer / demultiplexer for selectively arranging the signals in the assigned time slots, multiplexing the signals, and sending out the multiplexed / demultiplexed signals to the transmission line. And a read control circuit for assigning a port number on a separation bus of a previously assigned line interface to a read signal to the separation / separation bus. The read signal is selected and extracted.
Further, the loop type data transmission apparatus according to the present invention has a loop-like configuration including a first transmission path for transmitting a digitized optical multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized optical multiplexed signal in a direction opposite to the predetermined direction. A transmission path, a plurality of terminal devices that exchange signals with each other via the loop transmission path, and a predetermined one of multiplexed frame signals arranged in the loop transmission path and transmitted to the transmission path. A node device that extracts a time slot signal and demultiplexes it and sends it out to the terminal device, or takes in a signal from the terminal device and places it in a predetermined time slot of a multiplexed frame signal, multiplexes it and sends it out to the transmission line. In the loop-type data transmission device, the node device converts an optical signal from the first transmission line into an electric signal, guides the signal to an internal circuit of the node device, and outputs the signal from the internal circuit of the node device. A first terminator for converting an electric signal into an optical signal and sending it to the second transmission path; converting a light signal from the second transmission path into an electric signal to guide the signal to an internal circuit of the node device; A second terminal for converting an electric signal from the internal circuit into an optical signal and sending it to the first transmission line, and selecting a signal from one of the first or second transmission lines set in advance; And a system selection circuit for transmitting a signal to the other transmission line in the same direction or one transmission line in the same direction, and a transmission signal from the terminal device in a predetermined time slot position of a multiplexed frame signal. A multiplexing / demultiplexing unit that performs multiplexing by arranging the multiplexed frame signal and extracting a transmission signal from a predetermined time slot position of the multiplexed frame signal sent from the system selection circuit to perform demultiplexing; Multiplexed / A multiplexing / demultiplexing bus for transferring signals between the demultiplexing unit and the terminal device; a line interface unit interfacing between the terminal device and the multiplexing / demultiplexing bus; And a multiplexing / demultiplexing unit for demultiplexing a line interface assigned to a multiplexing / demultiplexing bus from a demultiplexing memory or an intra-office switching memory to a multiplexing / demultiplexing bus. It has a read control circuit for assigning a port number on the bus, and the line interface section selects and extracts a read signal from the multiplex / demultiplex bus based on the port number.
Further, the multiplexing / demultiplexing unit of the loop type data transmission apparatus according to the present invention generates an address signal set on the multiplexing / demultiplexing bus and sends it to a predetermined line interface unit. A read control circuit for reading the demultiplexed memory or the local exchange memory to the multiplexing / demultiplexing bus, and based on the address signal on the multiplexing / demultiplexing bus sent from the read control circuit, the line interface section The signal is read out from the device.
[0019]
Also, a loop-type data transmission apparatus according to the present invention provides a loop-like transmission comprising a first transmission path for transmitting a digitized multiplexed signal in a predetermined direction and a second transmission path for transmitting a digitized multiplexed signal in a direction opposite to the predetermined direction. And a plurality of terminal devices that exchange signals with each other via a loop-shaped transmission path, and extract a signal of a predetermined time slot from signals transmitted on the transmission path, which are arranged in the middle of the transmission path. In a loop-type data transmission device comprising a node device that demultiplexes and sends the signal to the terminal device, or multiplexes the signal from the terminal device and sends the signal to the transmission path,
The node device accesses the multiplexed frame signal of the SDH system transmitted to the transmission path, selectively extracts the signal from the assigned time slot, demultiplexes the signal, and sends out the signal to the terminal device, or And a multiplexer / demultiplexer for selectively arranging the signals in the assigned time slots, multiplexing the signals, and sending the multiplexed signals to the transmission line. The multiplex / demultiplexer is attached to the signal from the line interface. When the AND condition of the multiplexing request signal and the multiplex / relay bit of the signal stored in the multiplex memory is logical "1", there is provided a selector for selecting and transmitting data of the multiplex memory instead of the reception relay signal. Things.
Further, the loop type data transmission apparatus according to the present invention has a loop-like configuration including a first transmission path for transmitting a digitized optical multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized optical multiplexed signal in a direction opposite to the predetermined direction. A transmission path, a plurality of terminal devices that exchange signals with each other via the loop transmission path, and a predetermined one of multiplexed frame signals arranged in the loop transmission path and transmitted to the transmission path. A node device that extracts a time slot signal and demultiplexes it and sends it out to the terminal device, or takes in a signal from the terminal device and arranges it in a predetermined time slot of a multiplexed frame signal, multiplexes it and sends it out to the transmission line. In the loop data transmission device consisting of
The node device converts an optical signal from the first transmission line into an electric signal and guides it to an internal circuit of the node device, and converts an electric signal from the internal circuit of the node device into an optical signal and converts the electric signal into an optical signal. A first terminal for transmitting the optical signal from the second transmission line to an electric signal and guiding the electric signal to an internal circuit of the node device, and converting an electric signal from the internal circuit of the node device to an optical signal and converting the electric signal to an optical signal. A second terminal for sending out to one transmission path, and selectively taking in a signal from one of the first or second transmission paths set in advance and the other transmission path in the same direction, or A system selection circuit for transmitting a signal to one transmission path in the same direction, and multiplexing by arranging a transmission signal from a terminal device at a predetermined time slot position of a multiplexed frame signal, and Multiplexed frame sent A multiplexing / demultiplexing unit for extracting a transmission signal from a predetermined time slot position of the signal and performing multiplexing / demultiplexing, and a common signal path, and a signal between the multiplexing / multiplexing / demultiplexing unit and the terminal device. A multiplexing / demultiplexing bus for transfer, a line interface unit for interfacing between the terminal device and the multiplexing / demultiplexing bus, and a node management processor unit for managing the operation state of each device in the node via the node management bus. The multiplexing / multiplexing / demultiplexing unit, when the AND condition of the multiplexing request signal added to the signal from the line interface unit and the multiplexing / relay bit of the signal stored in the multiplexing memory is logic “1”, It has a selector for selecting and transmitting data of a multiplex memory instead of a reception relay signal.
[0020]
Also, a loop-type data transmission apparatus according to the present invention provides a loop-like transmission comprising a first transmission path for transmitting a digitized multiplexed signal in a predetermined direction and a second transmission path for transmitting a digitized multiplexed signal in a direction opposite to the predetermined direction. And a plurality of terminal devices that exchange signals with each other via a loop-shaped transmission path, and extract a signal of a predetermined time slot from signals transmitted on the transmission path, which are arranged in the middle of the transmission path. In a loop-type data transmission device comprising a node device that demultiplexes and sends the signal to the terminal device, or multiplexes the signal from the terminal device and sends the signal to the transmission path,
The node device accesses a multiplexed frame signal of the SDH system transmitted to the transmission line, selectively extracts a signal from an assigned time slot, demultiplexes the signal, and sends out the signal to the terminal device. And a multiplexing / demultiplexing unit for selectively arranging and multiplexing the signals from the received time slots, multiplexing the signals, and sending out the multiplexed / demultiplexed signals to the transmission line. A storage circuit for instructing each circuit to perform initialization and holding an initialization completion state, wherein multiplexing / relay bits of a signal stored in a multiplex memory and an output of the storage circuit indicating initialization completion indicate multiplexing; The data in the memory is selected and output.
Further, the loop type data transmission apparatus according to the present invention has a loop-like configuration including a first transmission path for transmitting a digitized optical multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized optical multiplexed signal in a direction opposite to the predetermined direction. A transmission path, a plurality of terminal apparatuses for exchanging signals with each other via the loop transmission path, and a predetermined number of multiplexed frame signals arranged in the middle of the loop transmission path and transmitted to the transmission path. A node device that extracts a signal of a time slot and demultiplexes it and sends it out to a terminal device, or takes in a signal from a terminal device and arranges it in a predetermined time slot of a multiplexed frame signal, multiplexes it and sends it out to the transmission path. Loop data transmission device consisting of
The node device converts an optical signal from the first transmission line into an electric signal and guides the signal to an internal circuit of the node device, and converts an electric signal from the internal circuit of the node device into an optical signal and converts the signal into an optical signal. A first terminal for transmitting the optical signal from the second transmission line to an electric signal and guiding the electric signal to an internal circuit of the node device, and converting an electric signal from the internal circuit of the node device to an optical signal and converting the electric signal to an optical signal. A second terminal for sending out to one transmission path, and selectively taking in a signal from one of the first or second transmission paths set in advance and the other transmission path in the same direction, or A system selection circuit for transmitting a signal to one transmission path in the same direction, and multiplexing by arranging a transmission signal from a terminal device at a predetermined time slot position of a multiplexed frame signal, and Multiplexed frame sent A multiplexing / demultiplexing unit for extracting a transmission signal from a predetermined time slot position of the signal and performing multiplexing / demultiplexing, and a common signal path, and a signal between the multiplexing / multiplexing / demultiplexing unit and the terminal device. A multiplexing / demultiplexing bus for transfer, a line interface unit for interfacing between the terminal device and the multiplexing / demultiplexing bus, and a node management processor unit for managing the operation state of each device in the node via the node management bus. The multiplexing / multiplexing / demultiplexing unit has a storage circuit for instructing each circuit of the multiplexing / multiplexing / demultiplexing unit to perform initialization and holding an initialization completed state, and multiplexing / relaying the signal stored in the multiplexing memory. According to the bit and the output of the storage circuit indicating the completion of the initialization, the data of the multiplex memory is selected and output.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a configuration diagram of a loop-type data transmission device according to the present invention. In the figure, 2 is a node device (N1 to N6), 3 is a terminal device connected to each of these node devices 2, 1 is a 0-system transmission line 10 constituting a counterclockwise optical transmission line, and a clockwise optical transmission line. This is a transmission path including the 1-system transmission path 11 constituting the transmission path. The transmission path 1 transmits a wideband digital signal equivalent to STM-1 having a frame structure according to the SDH method described above.
[0022]
FIG. 2 is a configuration diagram of the node device 2 of the loop type data transmission device. Here, each node device 2 has the same configuration. Reference numeral 20a denotes an A-system STM-1 terminator, and 20b denotes a B-system STM-1 terminator, which converts an optical signal from the optical transmission lines 10 and 11 into an electric signal. And an STM-1 termination unit 22.
[0023]
In this loop type data transmission device, the optical signal from the 0-system transmission line 10 is input to the A-system STM-1 termination unit 20a, and the optical signal output from the A-system STM-1 termination unit 20a is transmitted to the 1-system transmission line. It is sent to 11. The optical signal from the 1-system transmission line 11 is input to the B-system STM-1 termination unit 20b, and the optical signal output from the B-system STM-1 termination unit 20b is sent to the 0-system transmission line 10.
[0024]
An optical signal input from the 0-system transmission line 10 is transmitted to the A / STM-1 termination unit 20a, and an optical signal input from the 1-system transmission line 11 is transmitted to the B / STM-1 termination unit 20b. After being converted into a serial electric signal by the converter 211, the STM-1 termination section 22 removes the SOH portion (section overhead portion) and outputs the signal to the system selection circuit section 23.
[0025]
23 is a system selection circuit for selecting the A-system and B-system, and 24 multiplexes the data signal into a predetermined time slot on the multiplexed frame or extracts a data signal from the predetermined time slot on the multiplexed frame. A multiplexing / multiplexing / demultiplexing unit 26 for performing multiplexing / demultiplexing, and a multiplexing / demultiplexing bus 26 for exchanging signals between the multiplexing / multiplexing / demultiplexing unit and the line interface unit. Reference numeral 25 denotes a line interface unit that takes an interface between the node device 2 and the terminal device 3, and 3 denotes a terminal device. Reference numeral 27 denotes a node management processor that connects to each circuit in the node via a node management bus 28 and sets data and monitors the data so that each circuit performs a desired operation.
[0026]
Normally, the system selection circuit unit 23 selects a signal from the 0-system transmission line 10 and outputs it to the multiplexing / demultiplexing unit 24. The signal output from the multiplexing / demultiplexing unit 24 is output to the system selection circuit unit 23. Normally, the system selection circuit unit 23 outputs the signal from the multiplexing / demultiplexing unit 24 to the B-system STM-1 termination unit 20b, and after adding SOH at the B-system STM-1 termination unit 20b, performs electrical / optical conversion. After being output to the unit 212 and converted into an optical signal, it is transmitted to the 0-system transmission line 10. The multiplexing / multiplexing / demultiplexing unit 24 controls the multiplexing / demultiplexing bus 26 to perform connection with each terminal device 3 via a plurality of line interface units 25. Specifically, a signal on the multiplexing / demultiplexing bus 26 and a signal on the line interface are represented by a unique port number assigned to each line interface unit 25 and a unique port number assigned to an input / output signal of the multiplexing / demultiplexing bus 26. The correspondence with the unit 25 is specified, and the transfer of signals is controlled.
[0027]
The multiplexed frame structure of the optical signal handled by the loop transmission device has a structure corresponding to STM-1, which is the basic structure of SDH.
The multiplexed frame structure of the STM-1 has a structure in which one frame has a time slot of 9 columns and 270 rows in 125 μs (basic cycle of encoding of audio information). Here, one time slot has a transmission capacity equivalent to 64 Kb / s. In this frame structure, 261 columns from the ninth column are time slots accommodating various information, and are called payloads. The first 9 rows × 9 columns are allocated to a section overhead (SOH) for accommodating network management information when transmitting various information and a pointer for designating a head position of multiplexed information contained in the payload. Have been. In such a frame structure, in order to efficiently allocate the multiplexed frame including the low-speed signal to the time slot of the multiplexed frame, in the present invention, the bit array is divided into blocks of 9 bits (= 9 time slots) as one unit. FIG. 3 shows the payload portion thus blocked. By this blocking, the number of blocks (path payload) of the payload portion becomes 260 blocks from 0 to 259.
[0028]
FIG. 4 is a diagram for explaining the configuration of a time slot included in the one block. One block is composed of eight data slots and one signal slot, for a total of nine time slots. Each one of a data slot and a signal slot is composed of 8 bits, and one data slot can transmit data having a transmission speed of 64 Kb / s. The signal slot is an area for transmitting additional information such as dialing information other than data according to the terminal line to be accommodated. Further, the signal slot has an 8-bit configuration, and the least significant bit is assigned to the signal bit of the data slot eight times before this signal slot. Assigned.
[0029]
In the frame structure corresponding to STM-1 which is the basic structure of SDH (hereinafter referred to as STM-1 frame), 1.544 Mb / s is used as the minimum handling unit, so that transmission information temporarily corresponds to 1.544 Mb / s. It is necessary to convert (multiplex) the frame signal into an STM-1 frame after converting the frame signal into a frame signal to be converted into a frame signal. Therefore, a signal having a transmission rate of 64 Kb / s can be directly mapped to the STM-1 frame.
[0030]
FIG. 5 shows an example in which signals of various transmission rates are allocated (mapped) to the payload of the STM-1 frame. Here, a transmission rate of 1.5 Mb / s (hereinafter, a signal of 1.544 Mb / s is abbreviated as 1.5 Mb / s) after being divided into squares for each block with 9 time slots as one unit. 3 signals (1.5M- # 1,-# 2,-# 3) and 6 signals (6M- # 1,-# 2,-# 3) having a transmission rate of 6 Mb / s and 64 Kb / 8 shows a mapping state of eight lines (64K × 8) of signals having a transmission rate of s.
[0031]
Note that a blank portion in FIG. 5 shows a state in which no assignment is made during a time slot on the payload. However, as described above, in the loop data transmission according to the present invention, the transmission of 64 Kb / s is performed. The time slot corresponding to the speed is represented as 1 bit, and 9 bits are grouped as one unit, and the processing is performed. From the terminal side, one or more CHs are interfaced in the 64 Kb / s × 8 CHs. This allows multiplexing directly into STM-1 frames. Although FIG. 5 shows an example of allocation from the first row, there is no problem even if an empty slot is generated in the middle as a result of using an arbitrary slot of the STM-1 frame.
[0032]
Next, specific examples of assignment and signal processing will be described. For example, when inter-terminal communication with a transmission rate of 1.5 Mb / s is performed between the terminal device 3 of the node device (N1) 2 and the terminal device 3 of the node device (N2) 2, the STM is used for the inter-terminal communication. A time slot in the first 27 columns of the first row of the payload of the -1 frame (the area indicated by 1.5M- # 1 in FIG. 5, the number of blocks is 3 blocks, and the number of time slots is 27) is allocated. The 1.5 Mb / s signal from the terminal device 3 connected to the node device (N1) is converted into a parallel signal by the line interface unit 25 in the node device 2, and the timing controlled by the multiplexing / demultiplexing unit 24. Is output to the multiplexing / demultiplexing bus 26. After holding the data output to the multiplexing / demultiplexing bus 26 for a predetermined time, the multiplexing / multiplexing / demultiplexing unit 24 places the data and additional information in the time slot on the payload indicated by 1.5M- # 1 in FIG. I do. In addition, if there is no data to be transmitted from the node device (N1) 2 to another node device 2, the multiplexing / multiplexing / demultiplexing unit 24 of the node device (N1) 2 transmits data to slots other than 1.5M- # 1. , The data and the signal at the same position on the STM-1 frame of the received signal (above: temporarily stored in the multiplexing / demultiplexing unit 24) are changed. The multiplexed signal is added with SOH by the STM-1 termination unit 22, converted into an optical signal, and transmitted to the downstream node device 2. When operating using the 0-system transmission line 10, a signal from the node device (N1) 2 is transmitted to the node device (N2) 2.
[0033]
In the node device (N2) 2, the SOH of the signal received from the 0-system transmission line 10 is removed by the STM-1 termination unit 22, and the signal is sent to the multiplexing / multiplexing / demultiplexing unit 24 via the system selection circuit unit 23. Is output. The multiplexing / demultiplexing unit 24 demultiplexes and extracts the data and signal of the slot (FIG. 5-1.5M- # 1) to which the payload of the pre-allocated STM-1 frame is allocated, and extracts and demultiplexes the data. Output to the line interface unit 25 via the separation bus 26. The line interface unit 25 converts this signal into a serial signal, generates a signal to be output to the terminal based on the state of the additional signal, and outputs the signal to the terminal 3. In this way, the data of the terminal device 3 connected to the node device (N1) 2 is transmitted to the terminal device 3 connected to the node device (N2) 2. Conversely, transmission from the terminal device 3 connected to the node device (N2) 2 is also transmitted through the same procedure using the same slot (1.5M- # 1 in FIG. 5).
[0034]
As described above, the terminal device accesses the node device by accessing the multiplexed frame signal of the SDH system transmitted to the transmission line, selectively extracting a signal from a time slot to which a predetermined signal is allocated, and demultiplexing the signal. Multiplexing / multiplexing / demultiplexing means for transmitting to the apparatus, or taking in the signal from the terminal apparatus, selectively arranging the multiplexed frame signal in a predetermined time slot to which the multiplexed frame signal is allocated, and multiplexing and transmitting the multiplexed frame signal to the transmission path. As a result, even a signal having a low transmission rate such as 64 Kb / s can be directly multiplexed into an STM-1 frame without performing a stepwise multiplexing process.
[0035]
Embodiment 2 FIG.
Next, details of the multiplexing / demultiplexing unit according to the second embodiment of the loop-type data transmission device according to the present invention will be described. The second embodiment is a specific example of the multiplexing / demultiplexing unit 24 according to the first embodiment. Therefore, the following description focuses on the configuration of the multiplexing / demultiplexing unit 24 and related matters.
FIG. 6 is a configuration diagram of the multiplexing / demultiplexing unit 24. In the figure, 2401 is a reception relay memory that relays the data input from the system selection circuit unit 23 and temporarily holds the data until the data is output to the system selection circuit unit 23 again. 2402 stores the data input from the system selection circuit unit 23. A separation memory temporarily held until output to the multiplexing / demultiplexing bus 26. Reference numeral 2403 denotes a write control unit for controlling data writing to the reception relay memory 2401 and the separation memory 2402. Reference numeral 2404a denotes an input from the multiplexing / demultiplexing bus 26. A multiplex memory for temporarily storing the input data from the multiplexing / demultiplexing bus 26 until the data is output to the system selecting circuit unit 23; The local exchange memory 2406 is a write for controlling data writing to the multiplex memory 2404A and the local exchange memory 2405. Control unit 2407 is a read control unit that generates an address signal when data is read from the reception relay memory 2401 or the multiplex memory 2404A, and 2408 is a multiplex that converts a signal output from the read control unit 2407 into a preset address. A memory address converter 2409 is a selector for selecting the read data of the reception relay memory 2401 and the read data of the multiplex memory 2404A, and 2410A is a read for generating a reference signal and the like when reading data from the separation memory 2402 or the local exchange memory 2405. A controller 2411A is a separate memory address converter for converting a signal output from the read controller 2410A to a preset address, and 2412 selects read data of the separate memory 2402 and read data of the local exchange memory 2405. The selector unit, 2413 is a demultiplexing bus control unit for generating the reference signal and the control signal of the multiplexing / demultiplexing bus 26.
[0036]
FIG. 7 shows the structure of the multiplex memory address converter 2408. In FIG. 7, what is described as an address (000 to 2079) indicates the address of the multiplex address conversion unit 2408, and corresponds to the time slot number of the payload of the STM-1 frame. Bit D12 is a multiplex / relay bit. The signal to be selected in the selector unit 2409 in FIG. 6 is determined depending on whether the bit of D12 is “1” or “0”. If the bit is “1”, the read data from the multiplex memory 2404A is selected. In the case of "0", the read data from the reception relay memory 2401 is selected. Read addresses (A1 to A11) of the multiplex memory 2404A are set in D1 to D11.
[0037]
The separation memory address conversion unit 2411A has a function of creating read addresses of the separation memory 2402 and the intra-office exchange memory 2405 based on a reference signal output from the read control unit 2410A. Be composed. In this example, a two-port memory is used, and the setting of internal data can be changed via the node management bus 28.
[0038]
FIG. 8 shows the structure of the separation memory address conversion unit 2411A. In FIG. 8, what is described as an address (000 to 2079) indicates the address of the separation memory address conversion unit 2411A, and corresponds to the address of the multiplex / demultiplex bus 26. The bit D16 is an intra-office / separation bit. The signal selected by the selector unit 2412 in FIG. 6 is determined depending on whether the bit of D16 is "1" or "0". The read data from 2405 is selected, and if it is “0”, the read data from the separation memory 2402 is selected. Read addresses (A11 to A0) from the separation memory 2402 or the local exchange memory 2405 are set in D11 to D0. D17 to D23 are port IDs, and the port numbers of the line interface units corresponding to the data input / output via the demultiplexing bus 26 are set.
[0039]
Next, the operation based on FIGS. 6, 7 and 8 will be described. The signal input from the system selection circuit unit 23 is composed of a plurality of continuous time slots, and 2340 time slots starting from the data slot D0 of the block 0 and ending with the signal slot of the block 250 are sequentially input, and the write control is performed. The data is sequentially written to the reception relay memory 2401 and the separation memory 2402 under the control of the unit 2403.
[0040]
The demultiplexing bus control unit 2413 generates a reference signal necessary for input / output with the line interface unit 25 via the multiplexing / demultiplexing bus 26. Has the structure of continuous time slot data. Then, under the control of the write control unit 2406, the data is sequentially written to the multiplex memory 2404A and the local exchange memory 2405.
[0041]
The read control unit 2407 generates a read address with a phase slightly delayed from the write operation of the write control unit 2403. Based on the read address, data already written in the reception relay memory 2401 is sequentially read. The multiplex memory address conversion unit 2408 generates a read address of the multiplex memory 2404 based on the read address from the read control unit 2407, and reads data already written in the multiplex memory 2404A by using the read address. The data read from the reception relay memory 2401 and the multiplex memory 2404A are selected by the selector 2409 and then output to the system selection circuit unit 23. At this time, selection in the selector unit 2409 is performed based on the multiplex / relay bit from the multiplex memory address conversion unit 2408. Data output from the selector unit 2409 to the system selection circuit unit 23 starts in the data slot D0 of the block 0, and 2340 time slots ending with the signal slot of the block 250 are output in order. Since the operation is performed as described above, the time slot data output to the system selection circuit unit 23 is one time between the time slot data input from the system selection circuit unit 23 and the data input from the multiplexing / demultiplexing bus 26. Swapping is possible in slot units.
[0042]
The read control unit 2410A generates a reference signal with a phase slightly delayed from the write operation of the write control unit 2406. The separation memory address conversion unit 2411A generates a read address for the separation memory 2402 and the local exchange memory 2405 based on the reference signal from the read control unit 2410A. Based on the read address, data already written in the separation memory 2402 and the local exchange memory 2405 is read. Data read from the demultiplexing memory 2402 and the local exchange memory 2405 is selected by the selector 2412 and output to the multiplexing / demultiplexing bus 26. At this time, the selector 2412 selects the data from the separation memory 2402 and the data from the local exchange memory 2405 based on the intra-office / separation bit (see FIG. 8) from the separation memory address converter 2411A. The data output from the selector unit 2412 has a structure of a plurality of continuous time slot data. As described above, the data output to the multiplexing / demultiplexing bus 26 is switched between the data of the time slot input from the system selection circuit unit 23 and the data input from the multiplexing / demultiplexing bus 26 in units of one time slot. It is possible.
[0043]
The port number of the line interface unit 25 corresponding to the data input / output via the demultiplexing bus 26 is output from the separation memory address conversion unit 2411. In the line interface unit 25, a unique port number is previously set on the multiplexing / demultiplexing bus 26, and data of a line having the same port number is input / output via the multiplexing / demultiplexing bus 26.
[0044]
Here, the one provided with the intra-office exchange memory is shown, but may not be provided when intra-office exchange is unnecessary. Although the details of the handling of the signal slot and the data slot have been omitted, it goes without saying that the reception relay memory, the multiplex memory, the separation memory, and the intra-office switching memory have a configuration corresponding to the data slot and the signal slot.
[0045]
FIG. 9 is a timing chart showing how data and the like are input and output via the demultiplexing bus 26. The time slot number is a signal corresponding to the read address output from the read control unit 2410A shown in FIG. 6 and is not directly output to the demultiplexing bus 26, but the input of each signal is based on this time slot number. Output is performed. The demultiplexed data, the demultiplexed signal, and the port ID output to the demultiplexing bus 26 are output corresponding to the time slot numbers. On the other hand, for the multiplexed data and the multiplexed signal, the line interface unit 25 requires a processing time such as a coincidence of port IDs, so that a 4.5 clock time difference is provided between byte clocks.
[0046]
As described above, in the loop-type data transmission device according to the second embodiment, each memory for holding the signal received from the transmission path and the signal from the terminal device via the line interface unit, and the data for each time slot, Since a configuration is provided in which a multiplex memory address converter, a separate memory address converter, and a selector for interchanging are provided, data can be exchanged for each time slot. That is, the data can be exchanged with the minimum unit being 64 Kb / s. Further, since the intra-office exchange memory is provided, intra-office exchange is possible within the node device. Further, since the multiplex memory address conversion unit and the separation memory address conversion unit are configured by a two-port memory and can be set from the node management bus, the node device can be operated even when the terminal device needs to be added or changed. It is possible to change online as it is. Furthermore, since the port number of the line interface unit is output from the separate address conversion unit, the circuit configuration of the line interface unit can be simplified, for example, multiple time slots can be used without providing a special setting mechanism in the line interface unit. It is possible to make it.
[0047]
In the above embodiment, the intra-office exchange memory is provided. However, if the intra-office exchange is not necessary, the intra-office exchange memory may not be provided. Also, the details of the handling of the signal slot and the data slot are omitted. It goes without saying that the reception relay memory, the multiplex memory, the separation memory, and the intra-office exchange memory have a configuration corresponding to the data slot and the signal slot.
[0048]
Embodiment 3 FIG.
Next, details of the multiplexing / demultiplexing unit according to the third embodiment of the loop-type data transmission device according to the present invention will be described. The third embodiment has the same configuration as the first embodiment except for the multiplexing / demultiplexing unit 24. Further, in relation to the second embodiment, a part of the configuration of the multiplexing / demultiplexing unit 24 is changed.
In consideration of the above relationship, the configuration of the multiplexing / multiplexing / demultiplexing unit 24 according to the third embodiment will be described below with a focus on the parts different from the second embodiment.
FIG. 10 is a configuration diagram of the multiplexing / demultiplexing unit 24 according to the third embodiment. In the figure, reference numeral 2410B denotes a reference signal for reading data from the demultiplexing memory 2402 or the local exchange memory 2405, and a read control unit 1112 for generating a demultiplexing bus address signal to the line interface unit 25 via the demultiplexing bus 26. A separation memory address conversion unit that converts a signal output from the read control unit 1102 into a preset address. The same reference numerals or portions as those in FIG. 6 basically have the same functions as those in the second embodiment.
[0049]
FIG. 11 shows the structure of the separated memory address conversion unit 2411B according to the third embodiment. The structure of the multiplex memory address converter 2408 according to the third embodiment is the same as that of FIG.
[0050]
Next, the operation will be described. Note that an operation of writing a signal input from the system selection circuit unit 23 to the reception relay memory 2401 and the separation memory 2402, an operation of writing a signal input from the multiplexing / demultiplexing bus 26 to the multiplexing memory 2404A and the local exchange memory 2405, The operation of reading from the memory 2401 and the operation of selecting these read data and outputting the selected data to the system selection circuit unit 23 are the same as those in the second embodiment, and therefore description thereof is omitted.
[0051]
The read control unit 2410B generates a reference signal with a phase slightly delayed from the write operation of the write control unit 2406. The separation memory address conversion unit 2411B outputs the read addresses of the separation memory 2402 and the intra-office exchange memory 2405 from the reference signal from the read control unit 2410B, and based on the read addresses, reads the already written data. Data read from the demultiplexing memory 2402 and the local exchange memory 2405 are selected by the selector 2412 and output to the multiplexing / demultiplexing bus 26. At this time, the selector unit 2412 selects based on the intra-office / separation bit from the separated memory address conversion unit 2411B. The data output from the selector unit 2412 has a structure of a plurality of continuous time slot data. As described above, the time slot data input from the system selection circuit unit 23 and the data input from the multiplexing / demultiplexing bus 26 can be exchanged and output to the multiplexing / demultiplexing bus 26.
[0052]
A multiplex / demultiplex address signal corresponding to data input / output via the multiplex / demultiplex bus 26 is output from the read control unit 2410B. A corresponding demultiplexing address is set in advance in the line interface unit 25 in accordance with the time slot number and the number of time slots to be used. It is input and output via the separation bus 26. Here, the one provided with the intra-office exchange memory is shown, but may not be provided when intra-office exchange is unnecessary. Although the details of the handling of the signal slot and the data slot have been omitted, it goes without saying that the reception relay memory, the multiplex memory, and the separation memory inside the office exchange memory have a configuration corresponding to the data slot and the signal slot.
[0053]
As described above, in the loop-type data transmission device according to the present embodiment, the demultiplexing bus address signal is output from the read control unit, and the data of the line that matches the demultiplexing bus address set in the line interface unit in advance is output. Since the input / output is performed via the demultiplexing bus, the memory capacity of the separation memory address conversion unit of the multiplexing / demultiplexing unit can be reduced, and the number of times of setting to the separation memory address conversion unit can be reduced. can get.
[0054]
Embodiment 4 FIG.
Next, details of the multiplexing / demultiplexing unit according to the fourth embodiment of the loop-type data transmission device according to the present invention will be described. The fourth embodiment has the same configuration as the second or third embodiment except for the multiplexing / demultiplexing unit 24. Further, in relation to the second or third embodiment, the configuration of a part of the multiplexing / demultiplexing unit 24 is changed.
In consideration of the above relationship, the configuration of the multiplexing / multiplexing / demultiplexing unit 24 according to the fourth embodiment will be described below with a focus on changes from the second embodiment or the third embodiment. FIG. 12 is a configuration diagram of the multiplexing / demultiplexing unit 24 according to the fourth embodiment. In the figure, reference numeral 2404B temporarily stores data input from the multiplexing / demultiplexing bus 26 until it is output to the system selection circuit unit 23, and also holds a data multiplexing request signal from the multiplexing / demultiplexing bus 26 in the same manner as the data. A memory 2414 is an AND gate that takes the logical product of the multiplex / relay bit output from the multiplex memory address converter 2408 and the data multiplex request signal output from the multiplex memory 2404B. The configuration of the other parts is basically the same as that of the second embodiment or the third embodiment, and therefore the description is omitted.
[0055]
Next, the operation will be described. The operation of writing the signal input from the system selection circuit unit 23 to the reception relay memory 2401 and the separation memory 2402, the operation of reading from the separation memory 2403, the operation of reading from the local exchange memory 2405, and The operation of selecting and outputting to the demultiplexing bus 26 is basically the same as in the first embodiment.
[0056]
The multiplexing / demultiplexing bus control unit 2413 generates a reference signal necessary for inputting / outputting to / from the circuit interface unit 25 via the multiplexing / demultiplexing bus 26, and a plurality of continuous signals are input from the multiplexing / demultiplexing bus 26. It has the structure of time slot data. Then, under the control of the write control unit 2406, the data is sequentially written to the multiplex memory 2404B and the local exchange memory 2405. At this time, the multiplexed data / multiplexed signal and the data multiplexing request signal are written to the multiplexed memory 2404B, and the multiplexed data / multiplexed signal is written to the intra-office switching memory 2405.
[0057]
The read control unit 2407 creates a read address with a phase slightly delayed from the write operation of the write control unit 2403. Based on this read address, the already written time slot data is sequentially read from the reception relay memory 2401. The multiplex memory address conversion unit 2408 outputs the read address of the read address multiplex memory 2404B from the read control unit 2407, and reads the written data based on the read address. The data read from the reception relay memory 2401 and the multiplex memory 2404B are selected by the selector 2409 and output to the system selection circuit 23. The data multiplex request signal is read at the same time as the data is read from the multiplex memory 2404B. This data multiplexing request signal is ANDed with the multiplex / relay bit from the multiplex memory address converter 2408 by the AND gate 2414. The output of the AND gate 2414 is connected to the selector 2409. The selector 2409 performs multiplexing only when the AND condition is satisfied, that is, when the data multiplexing request signal is logic "1" and the multiplex / relay bit is logic "1". Select data from memory 2404B. When the AND condition is not satisfied, the selector unit 2409 selects data in the reception relay memory 2401. Then, the data is output from the selector unit 2409 to the system selection circuit 23. In the above embodiment, the intra-office exchange memory is provided. However, if the intra-office exchange is not required, it may not be provided. Although the details of the handling of the signal slot and the data slot have been omitted, it goes without saying that the reception relay memory, the multiplex memory, the separation memory, and the intra-office switching memory have a configuration corresponding to the data slot and the signal slot.
[0058]
As described above, the loop-type data transmission device according to the present embodiment is provided with a data multiplexing request signal, configured to write the data multiplexing request signal together with the data into the multiplexing memory, and further read out the data from the multiplexing memory and the reception relay memory. When selecting data, the data in the multiplex memory is selected based on the AND condition of the multiplex relay bit and the data multiplex request signal. This prevents illegal data from being multiplexed even if the initialization of the node device is not completed. it can. As a result, there is an effect that illegal data can be prevented from being transmitted to the terminal connected to the node device.
[0059]
Embodiment 5 FIG.
Next, details of the multiplexing / demultiplexing unit according to the fifth embodiment of the loop type data transmission apparatus according to the present invention will be described. The fifth embodiment has the same configuration as the second embodiment except for the multiplexing / demultiplexing unit 24. Further, in relation to the second embodiment, a part of the configuration of the multiplexing / demultiplexing unit 24 is changed.
In consideration of the above relationship, the configuration of the multiplexing / multiplexing / demultiplexing unit 24 according to the third embodiment will be described below with a focus on the changes from the second embodiment.
In FIG. 13, reference numeral 2416 denotes an initialization completion flip-flop circuit for indicating and holding that the node management processor unit 27 has completed initialization to the multiplexing / demultiplexing unit 24 via the node management bus 28, and 2415. Is an AND gate that takes the logical product of the multiplex / relay bit output from the multiplex memory address converter 2408 and the output of the initialization completion flip-flop circuit 2416. The structure of the multiplex memory address conversion unit 2408 is the same as that of FIG. 7, and the structure of the separation memory address conversion unit 2411A is the same as that of FIG.
[0060]
Next, the operation will be described. Note that an operation of writing a signal input from the system selection circuit unit 23 to the reception relay memory 2401 and the separation memory 2402, an operation of writing a signal input from the demultiplexing bus to the multiplex memory 2404 and the local exchange memory 2405, and an operation of the separation memory 2402 The operation of reading data from the local exchange memory 2405 and the operation of selecting data read therefrom and outputting it to the demultiplexing bus 26 are the same as those in the first embodiment.
[0061]
The node management processor unit 27 initializes each unit of the node device 2 when starting up the node device. As one of the series of processes, initialization of the multiplex memory address conversion unit 2408 and the separation memory address conversion unit 2411a of the multiplexing / demultiplexing unit 24 is performed. The initialization completion flip-flop circuit 2416 is in a reset state immediately before the initialization is completed, for example, immediately after the power supply to the node device 2 is turned on, and its output is logic “1”. Then, when the initialization setting is completed, the node management processor unit 27 sets the initialization completion flip-flop circuit 2416. Then, its output becomes logic "1".
[0062]
The data read from the reception relay memory 2401 and the multiplex memory 2404 are selected by the selector 2409 and output to the post-system selection circuit 23. The selection conditions include the output of the initialization completion flip-flop circuit 2416 and the output of the initialization completion flip-flop 2416. The multiplex / relay bit from the multiplex memory address converter 2408 is ANDed by the AND gate 2415. The output of the AND gate 2415 is connected to the selector 2409. When the AND condition is satisfied, that is, the output of the initialization completion flip-flop circuit 2416 is logic "1" and the multiplex / relay bit is logic. Only when “1”, the data from the multiplex memory 2404 is selected. When the AND condition is not satisfied, the selector unit 2409 selects data in the reception relay memory 2401. Then, it is output from the selector unit 2409 to the system selection circuit unit 23. Although the above embodiment shows the case where the intra-office exchange memory is provided, it may not be provided if intra-office exchange is not necessary. Although the details of the handling of the signal slot and the data slot have been omitted, it goes without saying that the reception relay memory, the multiplex memory, the separation memory, and the intra-office exchange memory have a configuration corresponding to the data slot and the signal slot.
[0063]
As described above, the loop-type data transmission apparatus according to the fifth embodiment is provided with the initialization completion flip-flop, and when selecting data by reading from the multiplex memory and the reception relay memory, selecting the multiplex / relay bit and the initialization completion flip-flop. Since the data of the multiplex memory is selected based on the AND condition of the output signal of the loop, it is possible to prevent the multiplexing of illegal data even when, for example, the initialization of the node device is not completed. As a result, there is an effect that illegal data can be prevented from being transmitted to the terminal connected to the node device.
[0064]
【The invention's effect】
The present invention is configured as described above, and has the following effects.
[0065]
A multiplexed frame signal of the SDH system transmitted to the transmission line is accessed and a signal is selectively extracted from a predetermined time slot of the multiplexed frame and demultiplexed, or a signal from a terminal device is taken in and the multiplexing is performed. Since the signal is selectively arranged in a predetermined time slot of the frame signal and multiplexed, even if the signal has a low transmission speed, the STM-1 frame is directly accessed and multiplexed without performing a stepwise multiplexing process. There is an effect that can be performed.
[0066]
A memory for holding a received data signal from the transmission line and multiplexed data sent from the terminal device via the line interface unit, and a multiplexed memory address converter for exchanging data for each time slot of these signals; Since the configuration is provided with the separation memory address conversion unit and the selector, the data can be exchanged for each time slot, and the effect of directly multiplexing / demultiplexing low-speed signal (64 Kb / s) data at the node device can be obtained. is there.
Further, since the time slot of data from the terminal device can be replaced with another time slot, intra-office exchange can be performed in the node device.
[0067]
Further, since the multiplex memory address conversion unit and the separation memory address conversion unit are configured by a two-port memory and can be set from the node management bus, the node device can be operated even when the terminal device needs to be added or changed. It can be added or changed online while it is still installed.
[0068]
Furthermore, since the port number of the line interface is output from the separation address conversion unit, a plurality of time slots can be used without providing a special setting mechanism in the line interface unit, and the circuit configuration of the line interface is simplified. Things are possible.
[0069]
In addition, since data is input / output via the multiplexing / demultiplexing bus based on the multiplexing / demultiplexing bus address signal from the read control unit, the memory capacity of the separation memory address conversion unit of the multiplexing / multiplexing / demultiplexing unit is reduced. Further, the number of times of setting for the separate memory address conversion unit can be reduced.
[0070]
Furthermore, since data transmission control is performed on condition that a data multiplexing request signal is present, illegal data can be transmitted to a terminal connected to a node device when a trouble occurs in the line interface unit. There is an effect that can be prevented.
[0071]
Furthermore, since the transmission of data is controlled based on the initialization completion information of the node device, it is possible to prevent transmission of unauthorized data before the completion of initialization.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a loop-type data transmission device according to the present invention.
FIG. 2 is a configuration diagram of a node device of the loop data transmission device according to the first embodiment of the present invention;
FIG. 3 is a configuration diagram of a payload portion of an STM-1 frame used in the node devices of the present invention (in a block configuration in which nine time slots are blocked as one block).
FIG. 4 is a diagram showing a configuration of a blocked signal shown in FIG. 3;
FIG. 5 is a diagram illustrating mapping of an STM-1 frame signal to a payload portion.
FIG. 6 is a configuration diagram of a multiplexing / demultiplexing unit used in a node device of a loop-type data transmission device according to a second embodiment of the present invention.
FIG. 7 is a diagram showing a structure of a multiple address translator according to the second embodiment of the present invention.
FIG. 8 is a diagram showing a structure of a separation address memory according to Embodiment 2 of the present invention;
FIG. 9 is a timing chart of the demultiplexing bus according to the second embodiment of the present invention.
FIG. 10 is a configuration diagram of a multiplexing / demultiplexing unit used in a node device of a loop-type data transmission device according to a third embodiment of the present invention.
FIG. 11 is a diagram showing a structure of a multiple address conversion unit according to a third embodiment of the present invention.
FIG. 12 is a configuration diagram of a multiplexing / demultiplexing unit used in a node device of a loop data transmission device according to a fourth embodiment of the present invention.
FIG. 13 is a configuration diagram of a multiplexing / demultiplexing unit used in a node device of a loop data transmission device according to a fifth embodiment of the present invention.
FIG. 14 is a configuration diagram of a conventional loop transmission device.
FIG. 15 is a configuration diagram of a node device of a conventional loop transmission device.
FIG. 16 is a diagram illustrating a multiplexing structure of a node device of a conventional loop transmission device.
FIG. 17 is an explanatory diagram of an STM-1 frame configuration of SDH.
[Explanation of symbols]
1 transmission line, 100 system transmission line, 11 system 1 transmission line,
2 node device,
20a A-system STM-1 termination, 20b B-system STM-1 termination,
21 signal converter,
211 light / electricity conversion circuit, 212 light / electricity conversion circuit,
22 STM-1 termination,
23 system selection circuit section, 24 multiplexing / demultiplexing section,
25 circuit interface unit, 26 demultiplexing bus,
27 node management processor, 28 node management bus
3 terminal device,
2401 reception relay memory unit, 2402 separation memory,
2403 write control unit, 2404A multiplex memory,
2404b Multiplex memory B, 2405 Internal exchange memory,
2406 write control unit, 2407 read control unit,
2408 multiple memory address converter, 2409 selector,
2410 read control unit, 2411A separation address conversion unit,
2411B separated address converter, 2412A selector,
2412B selector unit, 2413 demultiplexing bus control unit,
2414 AND circuit, 2415 AND circuit,
2416 Initialization completed FF circuit.

Claims

A loop-shaped transmission path including a first transmission path for transmitting the digitized multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized multiplexed signal in a direction opposite to the predetermined direction; And a plurality of terminal devices for exchanging signals with each other, and a signal of a predetermined time slot is extracted and multiplexed and demultiplexed from the signals arranged on the transmission line and transmitted to the transmission line to the terminal device. A loop-type data transmission device comprising a node device for transmitting and transmitting, or multiplexing by taking in a signal from the terminal device, and transmitting the signal to the transmission line,
The node device accesses a multiplexed frame signal of the SDH system transmitted to the transmission line, selectively extracts a signal from an assigned time slot, demultiplexes the signal, and sends out the signal to the terminal device, or said selectively placed into time slots assigned captures signals from the terminal device, e Bei multiplexing / demultiplexing section for feeding to the transmission path is multiplexed, the multiplexing / demultiplexing unit, the transmission path A reception relay memory for temporarily storing a digital reception signal from the terminal until it is sent to the transmission path again, a multiplex memory for temporarily storing a digital multiplexed signal for multiplexing sent from the terminal device, and Designation of an address of a time slot on a multiplexed frame for partially replacing the read content with the content read from the multiplex memory A multiplex memory address conversion unit that generates a signal for controlling the replacement, and a selector unit that switches the contents of the reception relay memory and the contents of the multiplex memory based on control from the multiplex memory address conversion unit. A loop-type data transmission device, wherein the digitized reception relay signal and the digital multiplexed signal can be exchanged.

A first transmission path for transmitting a digitized optical multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized optical multiplexed signal in a direction opposite to the predetermined direction; A plurality of terminal devices for exchanging signals with each other, and extracting a signal of a predetermined time slot from a multiplexed frame signal arranged in the middle of the loop-shaped transmission path and transmitted to the transmission path, thereby performing demultiplexing. And a node device that sends out the signal to the terminal device, or takes in a signal from the terminal device, arranges the signal in a predetermined time slot of the multiplexed frame signal, multiplexes the signal, and sends the multiplexed frame signal to the transmission line. At
The node device converts an optical signal from the first transmission line into an electric signal and guides the signal to an internal circuit of the node device, and converts an electric signal from an internal circuit of the node device into an optical signal to generate a second signal. And a first terminating unit for transmitting the optical signal from the second transmission line into an electric signal to guide the signal to an internal circuit of the node device, and to convert the electric signal from the internal circuit of the node device to an optical signal. A second terminator for converting the signal into a signal and sending the signal to a first transmission line; and selecting and taking in a signal from one of the first or second transmission lines set in advance and transmitting the signal in the same direction. A system selection circuit for transmitting a signal to the other transmission path toward the other or one transmission path toward the same direction, and multiplexing by arranging a transmission signal from the terminal device at a predetermined time slot position of a multiplexed frame signal. And selecting the system A multiplexing / demultiplexing unit for extracting a transmission signal from a predetermined time slot position of a multiplexed frame signal sent from the channel and performing demultiplexing, and a common signal path, A multiplexing / demultiplexing bus for transferring signals to and from the terminal device, a line interface unit interfacing between the terminal device and the multiplexing / demultiplexing bus, and an operation state of each device in the node via a node management bus e Bei the node management processor unit for managing, the multiplexing / demultiplexing unit includes a receiving relay memory for temporary storage until feeding again to the transmission path digital received signal from the transmission path, sent from the terminal device A multiplex memory for temporarily storing a digital multiplexed signal for multiplexing, and contents read from the reception relay memory are read from the multiplex memory. Designation of the address of a time slot on a multiplexed frame for partial replacement, a multiplex memory address converter for generating a signal for controlling the replacement, contents of the reception relay memory and contents of the multiplex memory And a selector unit for switching between the digitized reception relay signal and the digital multiplexed signal based on the control from the multiplexed memory address conversion unit. .

A first transmission path for transmitting the digitized multiplexed signal in a predetermined direction; Is a loop-shaped transmission path composed of a second transmission path transmitting in the opposite direction, a plurality of terminal devices that exchange signals with each other via the loop-shaped transmission path, and is disposed in the middle of the transmission path. And extracting a signal of a predetermined time slot from signals transmitted to the transmission line, demultiplexing and transmitting the extracted signal to the terminal device, or taking in a signal from the terminal device and multiplexing the signal. In a loop-type data transmission device comprising
The node device accesses a multiplexed frame signal of the SDH system transmitted to the transmission line, selectively extracts a signal from an assigned time slot, demultiplexes the signal, and sends out the signal to the terminal device, or A multiplexing / multiplexing / demultiplexing unit that selectively receives signals from the terminal device, allocates the signals to the assigned time slots, multiplexes the signals, and sends out the multiplexed / multiplexed signals to the transmission line. A reception relay memory for temporarily storing the digital reception signal before sending it to the transmission path again, a multiplex memory for temporarily storing a digital multiplex signal for multiplexing sent from the terminal device, and contents read out from the multiplex memory. And the designation of the address of the time slot on the multiplexed frame of the part that replaces the content read out from the reception relay memory, A multiplex memory address conversion unit that generates a signal for controlling the switching, a selector unit that switches the contents of the reception relay memory and the contents of the multiplex memory based on control from the multiplex memory address conversion unit, and the digital reception signal. A separation memory for temporarily storing the data for demultiplexing, an intra-station switching memory for temporarily storing a digital multiplexed signal for multiplexing sent from the terminal device, and a content read from the intra-station switching memory read from the separation memory. Designation of the address of the time slot on the multiplexed frame of the part to be replaced with the contents to be replaced, a separation memory address conversion unit for generating a signal for controlling the replacement, and the contents of the separation memory and the contents of the intra-office switching memory A selector for switching based on control from the separate memory address conversion unit; Replacement of the barrel received signal and the digital multiplexed signal, and the contents of the separation memories allow station exchange by replacement of the contents of the station exchanger memory and loop type data transmission system, characterized in that the.

A first transmission path for transmitting a digitized optical multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized optical multiplexed signal in a direction opposite to the predetermined direction; A plurality of terminal devices for exchanging signals with each other, and extracting a signal of a predetermined time slot from a multiplexed frame signal arranged in the middle of the loop-shaped transmission path and transmitted to the transmission path, thereby performing demultiplexing. And a node device that sends out the signal to the terminal device, or takes in a signal from the terminal device, arranges the signal in a predetermined time slot of the multiplexed frame signal, multiplexes the signal, and sends the multiplexed frame signal to the transmission line. At
The node device converts an optical signal from the first transmission line into an electric signal and guides the signal to an internal circuit of the node device, and converts an electric signal from an internal circuit of the node device into an optical signal to generate a second signal. And a first terminating unit for transmitting the optical signal from the second transmission line into an electric signal to guide the signal to an internal circuit of the node device, and to convert the electric signal from the internal circuit of the node device to an optical signal. A second terminator for converting the signal into a signal and sending the signal to a first transmission line; and selecting and taking in a signal from one of the first or second transmission lines set in advance and transmitting the signal in the same direction. A system selection circuit for transmitting a signal to the other transmission path toward the other or one transmission path toward the same direction, and multiplexing by arranging a transmission signal from the terminal device at a predetermined time slot position of a multiplexed frame signal. And the system selection A multiplexing / demultiplexing unit for extracting a transmission signal from a predetermined time slot position of the multiplexed frame signal sent from the circuit and performing demultiplexing, and a common signal path; A multiplexing / demultiplexing bus for transferring signals to and from the terminal device, a line interface unit interfacing between the terminal device and the multiplexing / demultiplexing bus, and an operation state of each device in the node via a node management bus A multiplexing / multiplexing / demultiplexing unit, which temporarily stores digital reception signals from the transmission path until they are transmitted to the transmission path again; A multiplex memory for temporarily storing a digital multiplexed signal for multiplexing, and a content read from the multiplex memory being read from the reception relay memory. Designation of an address time slot on the multiplexed frame parts to replace the contents of the multiple memory address conversion unit for generating a signal for controlling the replacement, the contents of the multiple memory and contents of the received relay memory before A selector unit for switching based on control from the multiplex memory address conversion unit, a separation memory for temporarily storing the digital received signal for demultiplexing, and a digital multiplexed signal for multiplexing sent from the terminal device. Generates a signal for controlling the address of a time slot on a multiplexed frame of a portion where a content read from the intra-office switching memory is temporarily stored, and a content for replacing the content read from the intra-office switching memory with the content read from the separation memory, and And a selector for switching the contents of the separation memory and the contents of the intra-exchange memory based on the control from the separation memory address conversion unit, for exchanging a digital reception signal and a digital multiplexed signal. And the exchange of the contents of the separation memory and the contents of the intra-office exchange memory. Loop data transmission system, characterized in that allowed the station exchanger.

A loop-shaped transmission path including a first transmission path for transmitting the digitized multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized multiplexed signal in a direction opposite to the predetermined direction; And a plurality of terminal devices for exchanging signals with each other, and a signal of a predetermined time slot is extracted and multiplexed and demultiplexed from the signals arranged on the transmission line and transmitted to the transmission line to the terminal device. A loop-type data transmission device comprising a node device for transmitting and transmitting the signal from the terminal device, multiplexing the signal from the terminal device, and transmitting the signal to the transmission line.
The node device accesses a multiplexed frame signal of the SDH system transmitted to the transmission line, selectively extracts a signal from an assigned time slot, demultiplexes the signal, and sends out the signal to the terminal device, or A multiplexing / demultiplexing unit for selectively arranging a signal from the terminal device, arranging the multiplexed signal in an assigned time slot, multiplexing the signal, and sending the multiplexed signal to the transmission line; A loop-type data transmission device comprising: a multiplexed memory address conversion unit and a separation address conversion unit, each of which comprises: a node management processor for setting these memories via a node management bus.

A first transmission path for transmitting a digitized optical multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized optical multiplexed signal in a direction opposite to the predetermined direction; A plurality of terminal devices for exchanging signals with each other, and extracting a signal of a predetermined time slot from a multiplexed frame signal arranged in the middle of the loop-shaped transmission path and transmitted to the transmission path, thereby performing demultiplexing. And a node device that sends out the signal to the terminal device, or takes in a signal from the terminal device, arranges the signal in a predetermined time slot of the multiplexed frame signal, multiplexes the signal, and sends the multiplexed frame signal to the transmission line. At
The node device converts an optical signal from the first transmission line into an electric signal and guides the signal to an internal circuit of the node device, and converts an electric signal from an internal circuit of the node device into an optical signal to generate a second signal. And a first terminating unit for transmitting the optical signal from the second transmission line into an electric signal to guide the signal to an internal circuit of the node device, and to convert the electric signal from the internal circuit of the node device to an optical signal. A second terminator for converting the signal into a signal and sending the signal to a first transmission line; and selecting and taking in a signal from one of the first or second transmission lines set in advance and transmitting the signal in the same direction. A system selection circuit for transmitting a signal to the other transmission path toward the other or one transmission path toward the same direction, and multiplexing by arranging a transmission signal from the terminal device at a predetermined time slot position of a multiplexed frame signal. And the system selection A multiplexing / demultiplexing unit for extracting a transmission signal from a predetermined time slot position of the multiplexed frame signal sent from the circuit and performing demultiplexing, and a common signal path; A multiplexing / demultiplexing bus for transferring signals to and from the terminal device, a line interface unit interfacing between the terminal device and the multiplexing / demultiplexing bus, and an operation state of each device in the node via a node management bus A multiplexing / multiplexing / demultiplexing unit, which controls the memory via a node management bus. The multiplexing / multiplexing / demultiplexing unit includes a two-port memory. A loop-type data transmission device, comprising:

A loop-shaped transmission path including a first transmission path for transmitting the digitized multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized multiplexed signal in a direction opposite to the predetermined direction; And a plurality of terminal devices for exchanging signals with each other, Of the signals transmitted to the transmission line, a signal of a predetermined time slot is extracted and demultiplexed and sent out to the terminal device, or a signal from the terminal device is taken in and multiplexed, and the signal is transmitted to the transmission line. In a loop type data transmission device comprising a sending node device,
The node device accesses a multiplexed frame signal of the SDH system transmitted to the transmission line, selectively extracts a signal from an assigned time slot, demultiplexes the signal, and sends out the signal to the terminal device, or A multiplexing / demultiplexing unit for selectively arranging a signal from the terminal device and arranging the signal in an assigned time slot, multiplexing the signal, and sending the multiplexed signal to the transmission line; Means for assigning a port number corresponding to the unique port number assigned to the unit to the input signal to the multiplexing / demultiplexing bus, by using the unique port number assigned to the input signal to the multiplexing / demultiplexing bus. A loop-type data transmission device, wherein a signal on the multiplexing / demultiplexing bus is extracted by a line interface unit.

A first transmission path for transmitting a digitized optical multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized optical multiplexed signal in a direction opposite to the predetermined direction; A plurality of terminal devices for exchanging signals with each other, and extracting a signal of a predetermined time slot from a multiplexed frame signal arranged in the middle of the loop-shaped transmission path and transmitted to the transmission path, thereby performing demultiplexing. And a node device that sends out the signal to the terminal device, or takes in a signal from the terminal device, arranges the signal in a predetermined time slot of the multiplexed frame signal, multiplexes the signal, and sends the multiplexed frame signal to the transmission line. At
The node device converts an optical signal from the first transmission line into an electric signal and guides the signal to an internal circuit of the node device, and converts an electric signal from an internal circuit of the node device into an optical signal to generate a second signal. And a first terminating unit for transmitting the optical signal from the second transmission line into an electric signal to guide the signal to an internal circuit of the node device, and to convert the electric signal from the internal circuit of the node device to an optical signal. A second terminator for converting the signal into a signal and sending the signal to a first transmission line; and selecting and taking in a signal from one of the first or second transmission lines set in advance and transmitting the signal in the same direction. A system selection circuit for transmitting a signal to the other transmission path toward the other or one transmission path toward the same direction, and multiplexing by arranging a transmission signal from the terminal device at a predetermined time slot position of a multiplexed frame signal. And the system selection A multiplexing / demultiplexing unit for extracting a transmission signal from a predetermined time slot position of the multiplexed frame signal sent from the circuit and performing demultiplexing, and a common signal path; A multiplexing / demultiplexing bus for transferring signals to and from the terminal device, a line interface unit interfacing between the terminal device and the multiplexing / demultiplexing bus, and an operation state of each device in the node via a node management bus A multiplexing / demultiplexing unit for assigning a port number corresponding to a unique port number assigned to each line interface unit to an input signal to the multiplexing / demultiplexing bus. Means for extracting a signal on the multiplexing / demultiplexing bus based on a unique port number assigned to an input signal to the multiplexing / demultiplexing bus. Loop data transmission system, characterized in that had Unishi.

A loop-shaped transmission path including a first transmission path for transmitting the digitized multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized multiplexed signal in a direction opposite to the predetermined direction; And a plurality of terminal devices for exchanging signals with each other, and a signal of a predetermined time slot is extracted and multiplexed and demultiplexed from the signals arranged on the transmission line and transmitted to the transmission line to the terminal device. A loop-type data transmission device comprising a node device for transmitting and transmitting the signal from the terminal device, multiplexing the signal from the terminal device, and transmitting the signal to the transmission line.
The node device accesses a multiplexed frame signal of the SDH system transmitted to the transmission line, selectively extracts a signal from an assigned time slot, demultiplexes the signal, and sends out the signal to the terminal device, or A multiplexing / multiplexing / demultiplexing unit for selectively arranging a signal from the terminal device and arranging the signal in an assigned time slot, multiplexing the signal, and sending out the multiplexed / multiplexed signal to the transmission line; A read control circuit for assigning a port number of a preset line interface on the separation bus to a read signal from the intra-office switching memory to the multiplexing / demultiplexing bus, and based on the port number, the line interface unit A read signal from the multiplexing / demultiplexing bus is selectively extracted. Loop type data transmission device.

A first transmission path for transmitting a digitized optical multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized optical multiplexed signal in a direction opposite to the predetermined direction; A plurality of terminal devices for exchanging signals with each other, and extracting a signal of a predetermined time slot from a multiplexed frame signal arranged in the middle of the loop-shaped transmission path and transmitted to the transmission path, thereby performing demultiplexing. And a node device that sends out the signal to the terminal device, or takes in a signal from the terminal device, arranges the signal in a predetermined time slot of the multiplexed frame signal, multiplexes the signal, and sends the multiplexed frame signal to the transmission line. At
The node device converts an optical signal from the first transmission line into an electric signal and guides the signal to an internal circuit of the node device, and converts an electric signal from an internal circuit of the node device into an optical signal to generate a second signal. And a first terminating unit for transmitting the optical signal from the second transmission line into an electric signal to guide the signal to an internal circuit of the node device, and to convert the electric signal from the internal circuit of the node device to an optical signal. A second terminator for converting the signal into a signal and sending the signal to a first transmission line; and selecting and taking in a signal from one of the first or second transmission lines set in advance and transmitting the signal in the same direction. A system selection circuit for transmitting a signal to the other transmission path toward the other or one transmission path toward the same direction, and multiplexing by arranging a transmission signal from the terminal device at a predetermined time slot position of a multiplexed frame signal. And the system selection A multiplexing / demultiplexing unit for extracting a transmission signal from a predetermined time slot position of the multiplexed frame signal sent from the circuit and performing demultiplexing, and a common signal path; A multiplexing / demultiplexing bus for transferring signals to and from the terminal device, a line interface unit interfacing between the terminal device and the multiplexing / demultiplexing bus, and an operation state of each device in the node via a node management bus A multiplexing / multiplexing / demultiplexing unit for transmitting a read signal from the separation memory or the intra-office switching memory to the multiplexing / demultiplexing bus to a multiplexing / demultiplexing bus of the assigned line interface. And a read control circuit for assigning a port number to the line interface unit based on the port number. Loop data transmission system is characterized in that so as to extract the sorted items.

The multiplexing / demultiplexing unit generates an address signal set on the multiplexing / demultiplexing bus and sends it to a predetermined line interface unit. Under the control of this address signal, the multiplexing / demultiplexing bus of the separation memory or the intra-office switching memory is controlled. A read control circuit for reading data from the multiplex / demultiplex bus, based on an address signal on the multiplex / demultiplex bus sent from the read control circuit. 9. The loop-type data transmission device according to claim 1, wherein:

A loop-shaped transmission path including a first transmission path for transmitting the digitized multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized multiplexed signal in a direction opposite to the predetermined direction; And a plurality of terminal devices for exchanging signals with each other, and a signal of a predetermined time slot is extracted and multiplexed and demultiplexed from the signals arranged on the transmission line and transmitted to the transmission line to the terminal device. A loop-type data transmission device comprising a node device for transmitting and transmitting the signal from the terminal device, multiplexing the signal from the terminal device, and transmitting the signal to the transmission line.
The node device accesses a multiplexed frame signal of the SDH system transmitted to the transmission line, selectively extracts a signal from an assigned time slot, demultiplexes the signal, and sends out the signal to the terminal device, or A multiplexing / demultiplexing unit for selectively arranging a signal from the terminal device, allocating the multiplexed signal to an assigned time slot, multiplexing the multiplexed signal, and sending the multiplexed signal to the transmission line; When the AND condition of the multiplexing request signal added to the signal from and the multiplex / relay bit of the signal stored in the multiplex memory is logic "1", the data of the multiplex memory is selected instead of the reception relay signal. A loop-type data transmission device having a selector for sending.

A first transmission path for transmitting a digitized optical multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized optical multiplexed signal in a direction opposite to the predetermined direction; A plurality of terminal devices for exchanging signals with each other, and It is arranged on the way, extracts a signal of a predetermined time slot from the multiplexed frame signal transmitted to the transmission line, demultiplexes the signal, sends out the signal to the terminal device, or captures the signal from the terminal device. A loop type data transmission device comprising a node device arranged in a predetermined time slot of the multiplexed frame signal and multiplexed and sent to the transmission path,
The node device converts an optical signal from the first transmission line into an electric signal and guides the signal to an internal circuit of the node device, and converts an electric signal from an internal circuit of the node device into an optical signal to generate a second signal. And a first terminating unit for transmitting the optical signal from the second transmission line into an electric signal to guide the signal to an internal circuit of the node device, and to convert the electric signal from the internal circuit of the node device to an optical signal. A second terminator for converting the signal into a signal and sending the signal to a first transmission line; and selecting and taking in a signal from one of the first or second transmission lines set in advance and transmitting the signal in the same direction. A system selection circuit for transmitting a signal to the other transmission path toward the other or one transmission path toward the same direction, and multiplexing by arranging a transmission signal from the terminal device at a predetermined time slot position of a multiplexed frame signal. And the system selection A multiplexing / demultiplexing unit for extracting a transmission signal from a predetermined time slot position of the multiplexed frame signal sent from the circuit and performing demultiplexing, and a common signal path; A multiplexing / demultiplexing bus for transferring signals to and from the terminal device, a line interface unit interfacing between the terminal device and the multiplexing / demultiplexing bus, and an operation state of each device in the node via a node management bus And a multiplexing / demultiplexing unit for managing a multiplexing request signal added to a signal from the line interface unit and a multiplexing / relay bit of a signal stored in the multiplexing memory. A loop type data transmission comprising a selector for selecting and transmitting data of a multiplex memory instead of a reception relay signal when an AND condition is a logic "1". Location.

A loop-shaped transmission path including a first transmission path for transmitting the digitized multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized multiplexed signal in a direction opposite to the predetermined direction; And a plurality of terminal devices for exchanging signals with each other, and a signal of a predetermined time slot is extracted and multiplexed and demultiplexed from the signals arranged on the transmission line and transmitted to the transmission line to the terminal device. A loop-type data transmission device comprising a node device for transmitting and transmitting the signal from the terminal device, multiplexing the signal from the terminal device, and transmitting the signal to the transmission line.
The node device accesses a multiplexed frame signal of the SDH system transmitted to the transmission line, selectively extracts a signal from an assigned time slot, demultiplexes the signal, and sends out the signal to the terminal device, or A multiplexing / multiplexing / demultiplexing unit which takes in a signal from the terminal device, selectively arranges the signal in an assigned time slot, multiplexes the signal, and sends out the signal to the transmission path
The multiplexing / multiplexing / demultiplexing unit has a storage circuit that instructs each circuit of the multiplexing / multiplexing / demultiplexing unit to perform initialization and holds an initialization completed state, and multiplexes the signals stored in the multiplexing memory. A loop-type data transmission device wherein data of a multiplex memory is selected and output based on / relay bits and an output of the storage circuit indicating completion of initialization.

A first transmission path for transmitting a digitized optical multiplexed signal in a predetermined direction and a second transmission path for transmitting the digitized optical multiplexed signal in a direction opposite to the predetermined direction; A plurality of terminal devices for exchanging signals with each other, and extracting a signal of a predetermined time slot from a multiplexed frame signal arranged in the middle of the loop-shaped transmission path and transmitted to the transmission path, thereby performing demultiplexing. And a node device that sends out the signal to the terminal device, or takes in a signal from the terminal device, arranges the signal in a predetermined time slot of the multiplexed frame signal, multiplexes the signal, and sends the multiplexed frame signal to the transmission line. At
The node device converts an optical signal from the first transmission line into an electric signal and guides the signal to an internal circuit of the node device, and converts an electric signal from an internal circuit of the node device into an optical signal to generate a second signal. And a first terminating unit for transmitting the optical signal from the second transmission line into an electric signal to guide the signal to an internal circuit of the node device, and to convert the electric signal from the internal circuit of the node device to an optical signal. A second terminator for converting the signal into a signal and sending the signal to a first transmission line; and selecting and taking in a signal from one of the first or second transmission lines set in advance and transmitting the signal in the same direction. The other transmission path toward the other, or a system selection circuit that sends a signal to one transmission path toward the same direction, and a transmission signal from the terminal device is arranged at a predetermined time slot position of a multiplexed frame signal. A multiplexing / demultiplexing unit that performs multiplexing, extracts a transmission signal from a predetermined time slot position of the multiplexed frame signal sent from the system selection circuit, and performs demultiplexing, and a common signal path. A multiplexing / demultiplexing bus for transferring signals between the multiplexing / demultiplexing unit and the terminal device, a line interface unit interfacing between the terminal device and the multiplexing / demultiplexing bus, and a node management bus And a node management processor unit that manages the operation state of each device in the node via the multiplexing / demultiplexing unit. The multiplexing / multiplexing / demultiplexing unit instructs each circuit of the multiplexing / multiplexing / demultiplexing unit to perform initialization, and A multiplex / relay bit of a signal stored in the multiplex memory and an output of the storage circuit indicating the completion of initialization; Loop data transmission system is characterized in that so as to force.