KR19980086687A - Digital PLL circuit and its method - Google Patents

Abstract

The digital PLL circuit of the present invention includes an impulse noise eliminator for removing noise of an impulse component induced in an externally input reference clock signal and outputting a noise-removed reference clock signal, an operation mode signal for synchronizing with an external system A receiver for generating a reset signal in accordance with the reference clock signal from which noise has been removed, a reset circuit for resetting the reference clock signal in accordance with the reset signal and a clock signal having the same frequency as the internally divided reference clock signal, And a frequency synthesizer for generating a corrected clock signal by modifying the division ratio of the system clock signal according to the phase detection signal and a locked operation clock signal as a final output, A reliable reference clock signal is ensured by the impulse noise eliminator to prevent malfunction, To shorten the initial synchronization time, and the structure is simple.

Description

Digital PLL circuit and its method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of digital communication, and more particularly, to a digital PLL circuit and a method thereof having a short initial synchronization time.

It has to be synchronized to one network in two different networks. For example, when connecting to a basic telephone line commonly used in a private switching system and a different telephone line such as another Integrated Services Digital Network (ISDN), which is another network, the system clock signals used in each telephone line are different, There was a problem of losing data during a call.

It is an object of the present invention to provide a digital PLL circuit for maintaining two stable systems by correcting a clock signal used in another system in order to synchronize with a reference clock signal of any one system.

Another object of the present invention is to provide a method of synchronizing a clock signal used in an exchange with a reference clock signal of an external network when a service of an external network is received in a private branch exchange and a key telephone exchange, Circuit.

It is still another object of the present invention to provide a digital PLL method for maintaining two stable systems by correcting a clock signal used in another system to synchronize with a reference clock signal of any one system.

According to another aspect of the present invention, there is provided a digital PLL circuit comprising: a detector for generating a reset signal in accordance with an external reference clock signal according to an operation mode signal for synchronizing with an external system; A phase detector for generating a phase detection signal by comparing the phase of the reference clock signal with the self-divided clock signal of the same frequency as the reference clock signal, And a frequency synthesizer for generating a corrected clock signal by modifying the ratio and an operation clock signal locked as a final output.

According to another aspect of the present invention, there is provided a digital PLL method including generating a reset signal in accordance with an externally input reference clock signal according to an operation mode signal for synchronizing with an external system, Generating a phase detection signal by comparing the phases of the reference clock signal and the self-divided clock signal having the same frequency as that of the reference clock signal, and generating a phase detection signal by changing the frequency division ratio of the system clock signal according to the phase detection signal, Generating a clock signal, and generating a locked operating clock signal as a final result.

1 is a block diagram of a digital PLL circuit according to an embodiment of the present invention.

2 (a) and 2 (b) are waveform diagrams of a clock signal divided in the frequency divider shown in FIG. 1 and a reference clock signal inputted from the outside, respectively.

3 (a) to 3 (h) are timing diagrams of input and output signals of the frequency synthesizer shown in Fig.

4 (a) to 4 (c) are timing diagrams for explaining a frame synchronizing signal generated in the phase detector shown in FIG.

5 is a detailed circuit diagram of the impulse noise canceller shown in FIG.

6 (a) to 6 (k) are operation timing diagrams of the impulse noise eliminator shown in FIG.

7 is a detailed circuit diagram of the trapper shown in Fig.

8 (a) to 8 (h) are operation timing charts of the trapper shown in Fig.

9 (a) to 9 (h) are timing diagrams in which a part of the timing chart shown in Fig. 8 is enlarged.

10 is a detailed circuit diagram of the frequency synthesizer shown in FIG.

Figs. 11A to 11G are timing charts of the output signals of the frequency divider shown in Fig. 1, and Fig. 11H is a timing chart of output signals of the phase detector shown in Fig.

12 is a detailed block diagram of the phase detector shown in Fig.

13 is a detailed circuit diagram of the phase detector shown in Fig.

14A to 14C are waveform diagrams of input and output signals of the first window signal generator shown in FIG.

15A to 15C are waveform diagrams of input and output signals of the second window signal generator shown in FIG.

Hereinafter, preferred embodiments of a digital PLL circuit and a method thereof according to the present invention will be described with reference to the accompanying drawings.

1, which is a block diagram according to one embodiment of the digital PLL circuit according to the present invention, a reference clock input REF8K_IN of the impulse noise canceller 100 includes a reference clock signal REF_8KHz of 8KHz supplied from an external network, A master clock signal (C16.384 MHz) as its own system clock of 16.384 MHz is input to the clock input terminal (C16M), and an inversion reset terminal And a reference clock output terminal REF8K_OUT is coupled to the detector 200 and the phase detector 500. The reference clock output terminal REF8K_OUT is connected to the reference clock output terminal REF8K_OUT.

The trapper 200 receives an operation mode signal ACT_MODE, a system reset signal RST and a master clock signal C16.384 MHz from the outside to output a track restart signal TRACK_RESTRART through the first AND gate 1 The inversion reset stage of period 400 And outputs the track enable signal TRACK_EN to the inverting reset terminal of the phase detector 500 through the second AND gate 2 . The first AND gate 1 logically multiplies the track restart signal TRACK_RESTRART with the system reset signal RST and the second AND gate 2 outputs the track repeat signal TRACK_RESTART, the track enable signal TRACK_EN, And the system reset signal RST.

The frequency synthesizer 300 inputs the first and second window signals Win_Lag and Win_Lead from the master clock signal C16.384 MHz and the system reset signal RST and the phase detector 500 to generate a locked clock signal of 4.096 MHz Output. The frequency divider 400 is connected to the inverting output terminal of the frequency synthesizer 300 And outputs the 9-bit divided clock signal C [8: 0] to the phase detector 500. The phase detector 500 receives the 9-bit clock signal C [8: 0] The phase detector 500 includes a locked clock signal of 4.096 MHz output from the frequency synthesizer 300, divided clock signals output from the frequency divider 400, an output signal of the second AND gate 2, a master clock signal C16.384 MHz) and the impulse noise eliminator 100, and outputs the first and second window signals Win_Lag and Win_Lead to the frequency synthesizer 300, (FS).

The switching system to which the digital PLL circuit shown in FIG. 1 is applied performs a call using data obtained by processing a 4KHz band voice signal at a frequency of 8KHz using a PCM (Pulse Coded Modulation) process. Therefore, To generate synchronized clock signals (e. G., An 8KHz clock signal and a 4.096MHz clock signal) using the reference clock signal of FIG. In other words, this means synchronizing other systems based on one reference system.

In other words, when the ISDN is additionally accommodated in the private switch or the key exchange, there is a synchronization phenomenon between the ISDN and the existing network, causing a phenomenon in which the data is lost or not properly received do. In order to overcome this problem, a clock signal of 8 KHz extracted from the data transmitted through the ISDN serial line is used as a reference clock signal in the switching system, and the master clock signal 16.384 MHz used in the switching system is used, By generating 4.096 MHz and 8 KHz, it is possible to provide a stable system in which the ISDN service and the existing service are synchronized with each other.

Therefore, the impulse noise eliminator 100 removes the noise of the impulse component induced in the reference clock signal of 8 KHz to minimize the noise, thereby supplying the reliable reference clock signal to the detector 200 and the phase detector 500. The ACT_MODE and the impulse noise output from the impulse noise canceller 100 are removed when the trapping device 200 is in the initial mode, that is, until reaching the tracking area. To quickly align internal synchronization once the reference clock signal has been established. That is, when the operation mode signal ACT_MODE is low, the track re-start signal TRACK_RESTART outputted from the receiver 200 does not reset the frequency divider 400 and the free-run mode in the free- When the operation mode signal ACT_MODE changes to logic high in a case where it is required to connect to an external network and synchronize with the external network, a reset pulse is generated to reset the frequency divider 400 through the first AND gate 1, Generates an enable signal TRACK_EN and applies it to the phase detector 500 through the second AND gate 2 to enable the phase detector 500.

The frequency synthesizer 300 receives the master clock signal C16.384 MHz and generates a locked 4.096 MHz clock signal according to the window signals Win_Lag and Win_Lead supplied from the phase detector 500 or generates a corrected clock signal . In the initial mode, the frequency divider 400 divides the frequency from 4.096 MHz to 8 KHz by its own system clock signal and outputs it to the phase detector 500. Thereafter, the frequency divider 400 frequency-divides from 4.096 MHz to 8 KHz using the corrected clock signal .

Here, the phase detector 500 detects the phase of the self-divided 8 KHz clock signal in the frequency divider 400 as shown in FIG. 2A and the phase of the impulse noise canceller 100 (FIG. 2 (Lag) or lead (lag) by comparing the phase of the clock signal with the reference clock signal of 8 KHz used in the external network outputted from the first and second windows Signal (Win_Lag, Win_Lead). If the phases of the self-divided clock signal and the reference clock signal are compared with each other, it can be determined whether or not the synchronization with the current external network is correct. Also the t _pd is the total phase detection region shown in 2 (b), t _pd1 will slow down (speed down) phase detection zone, t _pd2 is speed-up (speed up) phase detection zone, t _pd3 the bypass (bypass ) phase detection area, t is the total frequency correction _correct area, t _sd is the slow-down correction frequency domain, t _su represents the respective speed-up frequency correction area.

Therefore, the phase detector 500 is always physically different when a reference clock signal is compared with an internal frequency-divided 8 KHz clock signal generated in the frequency divider 400 shown in FIG. 3 (a). However, even if the difference between the two clock signals is fine, it is determined to be one of lead and lag and the clock signal output from the frequency synthesizer 300 is corrected. In order to prevent self-jitter, when a phase difference within a window (defined as a pass window) such as the bypass case shown in FIG. 3 (c) occurs, the clock signal is passed without correction to minimize jitter . Since the digital PLL of the present invention is intended to match the ISDN S / T interface (here, BRI: Basic Rate Interface), the frequency synthesizer 300 ) Has a size of 244 nsec in one cycle as shown in Fig. 3 (d). In addition, the ISDN S / T interface is an interface between a user and a network used in the narrowband ISDN. Although there are BRI and PRI (Primary Rate Interface), it is preferable that the present invention matches the BRI.

That is, in the case of the pass window, the probability that the divided reference clock signal shown in FIG. 3 (c) and the divided 8 KHz shown in FIG. 3 (a) are exactly synchronized is small, thereby preventing self jitter. If the phase difference of the two clock signals is accommodated in the pass window region, it proceeds without correction. When a correction is made in the correction area, it is corrected by half a period of the 4.096 MHz clock signal. 3 (b) is a waveform of the master clock signal of 16.384 MHz.

The clock signal of 8 KHz divided in the frequency divider 400 (FIG. 3 (a)) is delayed in the slow down mode (clockwise) to lower the speed of the clock signal of 4.096 MHz ahead of the reference clock signal as shown in FIG. The frequency synthesizer 300 changes its own clock signal (4.096 MHz) shown in FIG. 3 (f) to generate a clock signal that is slower than the normal 4.096 MHz clock signal in the slowdown region . The number of clock signals to be corrected is changed in consideration of the slow-down correction region, and 4.096 MHz is divided into a normal size except for this correction region.

3 (a) of FIG. 3 is lower than the reference clock signal as shown in (g) of FIG. 3 in the frequency divider 400, and a speed up mode in which the speed of the clock signal of 4.096 MHz is increased The frequency synthesizer 300 changes the clock signal of 4.096 MHz as shown in FIG. 3 (h) to generate a clock signal that operates faster than the normal 4.096 MHz clock signal in the speed up area.

Therefore, if a 4.096 MHz clock signal corrected so that the external reference clock signal and the clock signal divided by itself is generated and generates 8 KHz in the frequency divider 400, the reference clock signal is ultimately synchronized with the 8 KHz clock signal It will be lost.

A phase detector 500 for inputting a master clock signal of 16.384 MHz shown in FIG. 4 (a) and a locked clock signal of 4.096 MHz as shown in FIG. 4 (b) output from the frequency synthesizer 300 And outputs a frame synchronizing signal FS which is a network synchronizing signal as shown in Fig. 4 (c). In FIG. 4C, a is 61 nsec if a is in slowdown mode, and 0 nsec when a is not.

FIG. 5 is a detailed circuit diagram of the impulse noise eliminator 100 shown in FIG. 1, in which a reference clock signal applied from an external network is sampled with a master clock, a sampled reference clock signal is shifted by shifting the shifted reference clocks, So as to remove impulses of a short size smaller than a predetermined bit.

That is, according to the master clock signal C16M shown in FIG. 6B, a reference clock signal REF8K including impulse noise NOISE 1 and NOISE 2 as shown in FIG. 6C is inputted And the inverted reset signal (Fig. 6 The waveform of the output TP1 of the first D flip-flop 102 reset as shown in Fig. 6D is as shown in Fig. 6D. The output of the first D flip-flop 102 is input in accordance with the master clock signal C16M to generate an inverted reset signal The waveform of the output TP2 of the second D flip-flop 104 which is reset by the flip-flop D2 is as shown in Fig. 6 (e). Further, the output of the second D flip-flop 104 is input in accordance with the master clock signal C16M to generate an inverted reset signal The waveform of the output TP3 of the third D flip-flop 106, which is reset by the first D flip-flop 106, is as shown in Fig. 6 (f).

The third AND gate 108 logically multiplies the outputs of the first, second and third D flip-flops 102, 104 and 106 and outputs a signal TP4 as shown in FIG. 6 (g). The fourth AND gate 110 logically multiplies the inverted outputs of the first, second and third D flip-flops 102, 104 and 106 and outputs a signal TP5 as shown in FIG. 6 (h).

The output of the third AND gate 108 is latched in accordance with the inverted master clock signal by the first inverter 112 and the inverted reset signal The waveform of the output TP6 of the fourth D flip-flop 114, which is reset by the first D flip-flop 114, is as shown in (i) of FIG. The output of the fourth AND gate 110 is latched in accordance with the master clock signal inverted by the first inverter 112 and the inverted reset signal The waveform of the output TP7 of the fifth D flip-flop 116, which is reset by the flip-flop D7, is as shown in (j) of FIG. The fifth AND gate 118 receives the inverted output of the fifth D flip-flop 116 and an inverted reset signal ).

The input stage D and the clock stage CK of the set-reset flip-flop 120 (denoted SR FF 120) drive the drive voltage V _DD and the inverted output of the fourth D flip- The output of the fifth AND gate 118 is inverted by the inversion reset stage And outputs a reference clock signal REF8K_OUT delayed by a predetermined time with the impulse noise removed as shown in (k) of FIG. 6 as an output terminal Q.

In summary, the impulse noise canceller 100 recognizes and removes only pulses of 2 or less bits of the 16.384 MHz master clock signal as impulse noise by using the D flip-flops 102, 104, and 106 serving as a 3-bit shift register. If you want to remove the larger noise, increasing the number of shift registers can also eliminate large noises. The 2-bit first noise (NOISE 1) shown in (c) of FIG. 6 is a case where low noise is included in the reference clock signal, and the second noise (NOISE 2) of 1 bit includes high noise in the reference clock signal . The impulse noise canceller 100 serves as a kind of low-pass filter for removing a high-frequency component of a reference clock signal, which is the most important signal from the network.

FIG. 7 is a detailed circuit diagram of the integrator shown in FIG. 1, in which an active period of an operation mode signal ACT_MODE used as an edge of a reference clock signal REF8K and an enable signal of a PLL circuit is used to quickly synchronize .

7, the operation mode signal ACT_MODE shown in FIG. 8D is input to the input terminal D of the sixth D flip-flip 202, and the operation mode signal ACT_MODE shown in FIG. The reference clock signal REF8K as shown in Fig. 8B, which is output from the impulse noise eliminator 100, ) Includes an inverted reset signal (" 1 ") as shown in FIG. 8 ). The output of the sixth D flip flop 202 is input to the input terminal D of the seventh D flip flop 204 and the reference clock signal CK inverted by the second inverter 206 is input to the clock terminal CK. And an inversion reset terminal ( ) Includes an inverted reset signal And an output signal TP11 as shown in (e) of FIG. 8 is outputted to the output terminal Q. As shown in FIG.

8E) of the seventh D flip-flop 204 is input to the input terminal D of the eighth D flip-flop 208 and a third inverting 210, the inverted master clock is input, and the inverted reset terminal ) Includes an inverted reset signal And outputs an output signal TP12 as shown in (f) of FIG. 8 as an output terminal Q. The waveform of the master clock signal C16M input to the third inverter 210 is as shown in FIG. 8C.

The sixth AND gate 212 logically multiplies the operation mode signal ACT_MODE and the output signal of the eighth D flip-flop 208 and outputs a track enable signal TRACK_EN as shown in FIG. 8 (g) . The first NAND gate 214 inverts and inverts the inverted output signal of the eighth D flip flop 208 and the output signal of the seventh D flip flop 204 and the seventh AND gate 216 inverts the output signal of the first NAND gate 214 and an inverted reset signal ( ) To output a track restart signal TRACK_RESTART as shown in FIG. 8 (h).

9 (a) to 9 (h) illustrate a state in which the operation mode signal ACT_MODE becomes high immediately after the operation mode signal ACT_MODE becomes high to facilitate understanding of the operation of the capturer 200 shown in FIG. 8A to 8H are enlarged views of some sections of the signals shown in Figs.

In summary, the receiver 200 does not need to synchronize with the network since the digital PLL is not operating, i.e., the operation mode (ACT_MODE) is not activated as a logic low, and the reference clock is not input, And therefore, when the operation mode signal (ACT_MODE) is changed to a logic high state, the time until synchronization with the external network is minimized.

10 is a detailed circuit diagram of the frequency synthesizer 300. As shown in FIG. 10, the output terminal of the fourth inverter 302, which inverts the master clock signal C16M, is coupled to the input T of the first T flip flop 304 (labeled TFF) ( ) ≪ / RTI > ). The output of the first T flip flop 304 and the inverted output of the second T flip flop 316 input to the first and second inputs A and B of the multiplexer 306 And outputs it to the fifth inverter 318 in accordance with the output.

The eighth AND gate 308 logically multiplies the inverted output of the ninth D flip flop 310 and the inverted output of the tenth D flip flop 314. The ninth D flip flop 310 latches the output of the eighth AND gate 308 according to the master clock signal C16M and is reset by the output of the ninth AND gate 312. The ninth AND gate 312 receives the second window signal Win_Lead output from the phase detector 500 shown in FIG. 1 and an inverted reset signal ) To multiply the ninth and tenth D flip-flops 310 and 314 by an inverted reset terminal ( .

The tenth D flip-flop 314 latches the output of the ninth D flip-flop 310 according to the master clock signal C16M. The second T flip flop 316, which receives the output of the ninth D flip flop 310, And outputs the output as a selection signal of the multiplexer 306. [

The third T flip flop 320 operates in accordance with the master clock signal C16M and is reset in accordance with the output of the tenth AND gate 322. [ The tenth AND gate 322 receives the first window signal Win_Lag output from the phase detector 500, the inverted reset signal ) And the output of the second NAND gate 342 so that the reset terminal of the third, fourth and fifth T flip-flops 322, 324, .

The fourth T flip flop 324 inputs the inverted output of the third T flip flop 322 and the fifth T flip flop 326 inputs the inverted output of the fourth T flip flop 324. The eleventh AND gate 328 logically multiplies the output of the third T flip flop 322 by the output of the fourth T flip flop 324 and outputs it to one input of the OR gate 332, Flops 322 and the inverted output of the fourth T flip-flop 324 and outputs the inverted output to the other input of the first gate 332. The thirteenth AND gate 334 logically multiplies the inverted outputs of the third and fourth T flip-flops 322 and 324 and the output of the fifth T flip flop 326.

The eleventh D flip flop 336 inputs the output of the first gate 332 in accordance with the master clock signal C16M and outputs an inverted reset signal ). The twelfth D flip-flop 338 inputs the output of the thirteenth AND gate 334 in accordance with the master clock signal C16M, and outputs the inverted reset signal ). The thirteenth D flip-flop 340 receives the output of the twelfth D flip-flop 338 in accordance with the master clock signal C16M, and outputs an inverted reset signal ). The second NAND gate 342 inverts the logical sum of the output of the twelfth D flip flop 338 and the output of the thirteenth D flip flop 340 and feeds back the result to the tenth AND gate 322.

On the other hand, the second multiplexer 344 selects the output of the fifth inverter 318 or the output of the eleventh D flip-flop 336 according to the first window signal Win_Lag and outputs it to the sixth T flip-flop 346 . The clock signal C4M of 4.096 MHz locked from the output terminal Q of the sixth T flip flop 346 is outputted and the inverted output terminal ) Output Is applied to the frequency divider 400. [ Here, the output C4M of the locked 4.096 MHz output from the sixth T flip-flop 346 becomes the output of the digital PLL circuit.

That is, when the first and second window signals Win_Lag and Win_Lead are all logic low, that is, when the difference between the 8 KHz reference clock signal and the 8 KHz clock signal divided in the frequency divider 400 is the difference in the bypass window, (T) of the master clock signal C16M through the output Q of the first T flip flop 304, the first multiplexer 306, the second multiplexer 344, the sixth T flip flop 346, Is output. Here, the first and sixth T flip flops 304 and 346 each serve to divide by 2, the first multiplexer 304 maintains the previous state, and the second multiplexer 344 always outputs the first input A, .

If the 8 KHz clock signal divided in the divider 400 is a slowdown mode that lowers the speed of the 4.096 MHz clock signal divided by the divider 400 ahead of the reference clock signal of 8 KHz, When the second window signal Win_Lead is generated, the ninth and tenth D flip-flops 310 and 314 functioning as third dividers are operated. The second T flip-flop 316 operates as a second input terminal of the first multiplexer 306 B and selects the first input A of the second multiplexer 344 and the inverted output terminal of the sixth T flip flop 346 ), I.e., the corrected clock signal of the master clock signal in the third window, which is corrected in the second window region, is output.

When the 8 KHz clock signal divided in the frequency divider 400 is lower than the reference clock signal of 8 KHz to increase the speed of the clock signal of 4.096 MHz divided by the frequency divider 400, The third, fourth and fifth T flip flops 320,324 and 326 and the eleventh, twelfth and thirteenth D flip flops 336,338 and 340 operate and the second multiplexer 344 operates when the first window signal Win_Lag of the first multiplexer 344 is generated. Flip flop 336, which is input to the second input terminal B, and outputs the inverted output terminal of the sixth T flip flop 346 Is applied to the frequency divider 400. In this case, the corrected clock signal is applied to the frequency divider 400 in the first window region.

That is, the master clock signal C16M has to be locked at 4.096 MHz through the sixth T flip-flop 346, which is four clocks for one cycle in normal state, three clocks for one cycle in the slowdown mode, Up mode, it generates a corrected clock signal having five clock signals for one period.

11A to 11G are waveforms output from the frequency divider 400 shown in FIG. 1, and the least significant bits of the frequency divider 400 are the clock signals of 4.096 MHz shown in FIG. 11A, , A clock signal of 2.048 MHz shown in FIG. 11 (b), a clock signal of 1.024 MHz shown in FIG. 11 (c), a clock signal of 512 KHz shown in FIG. 11 (d) (Not shown), a clock signal (not shown) of 64 KHz, a clock signal of 32 KHz (not shown), a clock signal of 16 KHz shown in FIG. 11 (f) A clock signal of 8 KHz shown in (g) of FIG. 11 is outputted as the most significant bit of the frequency divider 400.

11 (h) shows a window value generated by the phase detector 500 shown in FIG. 1 using a 4.096 MHz clock signal to 8 KHz clock signal divided in the frequency divider 400, Respectively.

FIG. 12 is a detailed block diagram of the phase detector 500 shown in FIG. 1, and is described in conjunction with FIG. 13, FIG. 14, and FIG. 12, the decoder 502 receives the divided clock signals output from the frequency divider 400 shown in FIG. 1 and outputs the decoded output data W000-W3FF to the first and second window signal generators 506 and 508 .

The frame synchronizing signal generator 504 includes a fourteenth AND gate 511 for logically multiplying the divided clock signals output from the frequency divider 400 as shown in FIG. 1 according to the clock signal C9 of 4.096 MHz output from the frequency synthesizer 300 shown in FIG. 1, and outputs an inverted reset signal ), And its inverted output terminal ( And a 14th D flip-flop 512 for outputting the frame synchronizing signal FS from the 16th D flip-flop.

The detailed configuration of the first window signal generator 506 is as shown in Fig. 13, and the output data W000-W018 of the decoder 502, the master clock signal C16M, the impulse noise eliminator The reference clock signal REF8K and the inverted reset signal ) To generate a first window signal Win_Lag. T1, T2, ..., Tn input to the 19th, 21st, ..., 23rd AND gates 528, 533, ..., 538 shown in FIG. 13 are decoded And this value is increased by the following equation (1).

For example, as shown in FIG. 14 (a), the reference clock signal REF8K is supplied to the decoder 502 using the self-divided clock signal, as shown in FIG. 14 (c) The first window signal Win_Lag output from the ninth AND gate 528 through the 18th, 19th, and 20th D flip-flops 524, 525, and 527 of the first window generator 506 of FIG. 13 is sampled Lt; / RTI > is applied to the frequency synthesizer 300 shown in FIG. The logic high portion of the first window signal Win_lag starts at W001 and the value of T1 that determines the logic low of the first window signal Win_Lag is W00A by the following equation (1).

That is, the first window signal generator 506 receives the clock signals from the frequency divider 400 and outputs the window values ), As shown in FIG. 13, the window value ) Is divided into 24 steps (W001-W018). The logic high point of the first window signal (Win_Lag) is predetermined according to each step, and the reference clock signal (REF8K) is sampled to determine the logic low point of the first window signal In order to determine the final Value, and the Tn value that determines this logic low portion is a predetermined value.

That is, the Tn value of the first window signal Win_Lag can be obtained by the following equation (1).

= [(D input Value / 2) * 5 + 2] * 2, Is excellent

For example, when D = 001,

T1 = [{((1-1) / 2 * 5 + 5] * 2 = A (= W00A)

When D = 002,

T2 = [(2/2) * 5 + 2] * 2 = E (= W00E)

When D = 003,

T3 = [{(3-1) / 2} * 5 + 5] * 2 = 14 (= W014).

13, and the output data of the decoder 502, the master clock signal C16M, the reference clock signal REF8K, and the inverted reset signal < RTI ID = 0.0 > ) To generate a second window signal Win_Lead.

That is, the clock signal generated by the divider 400 is input to the frequency divider 400 and the window value W The reference clock signal REF8K is sampled at the rising edge of the window, and when the result is generated, the second window signal Win_Lead is made logic high from that time, and the calculated predetermined value And is then reduced to a logic low.

The reference clock signal REF8K is sampled at the window value W3FE generated by the decoder 502 as shown in FIG. 15 (c) using the self-divided clock signal as shown in FIG. 15 (a) Only the JK flip-flop 552, the 33rd, the 34th and the 35th D flip-flops 553, 554 and 555 of the second window generator 508 of FIG. 13 are operated and the sixth NAND gate 556 and the NOR gate 558 And generates a second window signal Win_Lead as shown in Fig. 15 (b) having a logic high interval from the window value W3FE to WOO3.

The second window generator 508 of FIG. 13 is also configured to generate the second window signal Win_Lead in 24 steps, and is input to the JK flip-flops 540, .., 546 and 552 of each stage The input value K at the input of the day is given by Equation (2). The input value J of the other inputs of the JK flip-flop of each stage is a decoded value in which the reference clock signal REF8K is sampled and input.

For example, when J is 3FE,

K = 1 * 3 = 3 (= WOO 3)

When J is W3FD, K is

K = 2 * 3 = 6 (= W006).

As described above, the PLL circuit of the present invention is less expensive than the analog PLL circuit, has an effect of preventing a malfunction by ensuring a reliable reference clock signal by impulse noise elimination, and shortening the initial synchronization time , The structure has a simple effect.

Claims (15)

An encoder for generating a reset signal in accordance with an externally input reference clock signal in accordance with an operation mode signal for synchronizing with an external system, a phase detector for detecting a phase of the reference clock signal, A phase detector for generating a phase detection signal by comparing a phase of the first clock signal with a self-divided first clock signal having the same frequency as the first clock signal, and a clock signal corrected by modifying a division ratio of the system clock signal according to the phase detection signal, And a frequency synthesizer for generating a locked operating clock signal. The apparatus of claim 1, further comprising: an impulse noise canceller that removes noise of an impulse component included in a reference clock signal input from the outside and outputs a noise-removed reference clock signal to the trapper and the phase detector; And a frequency divider dividing the system clock signal to supply a plurality of frequency-divided clock signals including the first clock signal to the phase detector. The apparatus as claimed in claim 1, wherein the impulse noise eliminator includes a plurality of shift registers for shifting an input reference clock signal, and a logic circuit for summing outputs of the plurality of shift registers, And removing a pulse having a size smaller than a predetermined value. 3. The apparatus of claim 2, wherein the capturer maintains a free-run mode when the operation mode signal is inactive and generates a reset signal to synchronize the noise-removed reference clock signal when the operation mode signal becomes active And outputs it to the frequency divider and the phase detector. 3. The apparatus of claim 2, wherein the phase detector comprises: a decoder for decoding the plurality of clock signals and outputting a decoded value; and a decoder for using the decoded value when the first clock signal is behind the reference clock signal A first generator for generating a first window signal as the phase detection signal indicative of a first window area for increasing the speed of the operating clock signal and a second generator for generating a first window signal using the decoded value if the first clock signal is ahead of the reference clock signal And a second generator for generating a second window signal as said phase detection signal indicative of a second window region for lowering the speed of said operating clock signal. 6. The apparatus of claim 5, wherein the phase detector further comprises a frame synchronizing signal generator for generating a frame synchronizing signal in synchronization with the locked operation clock signal output from the frequency synthesizer by logically multiplying the plurality of frequency- Circuit. 6. The method of claim 5, wherein the starting point of the active period of the first and second window signals is a decoded value of the sampled time point of the reference clock signal sampled with the decoded value, Is a predetermined value determined by a decoded value at a sampled time point of the digital PLL circuit. 2. The digital PLL circuit of claim 1, wherein the frequency synthesizer does not correct the locked operating clock signal if the reference clock signal is received within a pass window region to prevent self jitter. The frequency synthesizer according to claim 6, wherein the frequency synthesizer includes: a first frequency divider circuit for dividing the system clock signal into a first predetermined number and generating a locked operation clock signal when the first window signal and the second window signal are not generated; A second dividing circuit for dividing the system clock signal into a second predetermined number in the first window region in response to a first window signal to generate the corrected clock signal and a second dividing circuit for generating the corrected clock signal in response to the second window signal, And a third dividing circuit for dividing the system clock signal into a third predetermined number in a window region to generate the corrected clock signal. (a) generating a reset signal in accordance with an externally input reference clock signal in accordance with an operation mode signal for synchronizing with an external system, (b) after resetting according to the reset signal, Comparing the phases of the reference clock signal and the self-divided first clock signal having the same frequency as the reference clock signal to generate a phase detection signal; and (c) varying the frequency division ratio of the system clock signal according to the phase detection signal. And generating a locked operating clock signal as a final result. The method of claim 10, further comprising the steps of: (d) generating a reference clock signal from which noise is removed by removing noise of an impulse component induced in an externally input reference clock signal; and (e) And dividing the system clock signal to generate a plurality of frequency-divided clock signals including the first clock signal. The method of claim 11, wherein the step (b) further comprises: (b1) decoding the plurality of clock signals to generate a decoded value; (b2) Generating a first window signal as the phase detection signal indicating a first window region that increases the speed of the operating clock signal using the decoded value; and (b3) And generating a second window signal as the phase detection signal indicating a second window region for lowering the speed of the operating clock signal using the decoded value. 13. The digital PLL method of claim 12, wherein step (b) further comprises: (b4) logically multiplying the plurality of divided clock signals to generate a frame synchronization signal in synchronization with the locked operation clock signal. 13. The method of claim 12, wherein the starting point of the active period of the first and second window signals is a decoded value of the sampled time point of the reference clock signal with the decoded value, Is a predetermined value determined by a decoded value at a sampled time point of the digital PLL. The method as claimed in claim 12, wherein the step (c) comprises the steps of: (c1) generating the operating clock signal by dividing the system clock signal by a first predetermined number if the first window signal and the second window signal are not generated (c2) dividing the system clock signal into a second predetermined number in the first window area in response to the first window signal to generate the corrected clock signal; and (c3) And generating the corrected clock signal by dividing the system clock signal into a third predetermined number in the second window area in response to the second clock signal.