KR19980085264A - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
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- KR19980085264A KR19980085264A KR1019970021322A KR19970021322A KR19980085264A KR 19980085264 A KR19980085264 A KR 19980085264A KR 1019970021322 A KR1019970021322 A KR 1019970021322A KR 19970021322 A KR19970021322 A KR 19970021322A KR 19980085264 A KR19980085264 A KR 19980085264A
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- forming
- metal wiring
- contact hole
- plug
- insulating film
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 42
- 239000002184 metal Substances 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 34
- 230000015572 biosynthetic process Effects 0.000 title claims description 3
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 24
- 239000010936 titanium Substances 0.000 claims description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- 239000007789 gas Substances 0.000 claims description 6
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 238000007599 discharging Methods 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 38
- 229910052721 tungsten Inorganic materials 0.000 description 38
- 239000010937 tungsten Substances 0.000 description 38
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 다층 금속배선의 제조공정을 간소화시키도록 한 반도체 소자의 금속배선 제조방법에 관한 것으로서, 반도체 기판상에 일정한 폭을 갖는 제 1 금속배선을 형성하는 단계와, 상기 제 1 금속배선의 표면이 소정부분 노출되도록 콘택홀을 갖는 절연막을 형성하는 단계와, 상기 콘택홀을 포함한 기판의 전면에 제 1, 제 2 도전층을 형성하는 단계와, 상기 콘택홀 내부의 제 2 도전층상에 플러그를 형성하는 단계와, 상기 플러그 주변을 제외한 제 1, 제 2 도전층을 제거하는 단계와, 상기 절연막을 표면으로부터 소정깊이로 식각하는 단계와, 그리고 상기 플러그와 콘택되도록 기판상에 제 2 금속배선을 형성하는 단계를 포함하여 형성함을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a metal wiring of a semiconductor device to simplify the manufacturing process of a multilayer metal wiring, the method comprising: forming a first metal wiring having a predetermined width on a semiconductor substrate, and forming a surface of the first metal wiring; Forming an insulating film having a contact hole to expose the predetermined portion, forming first and second conductive layers on the entire surface of the substrate including the contact hole, and plugging the plug on the second conductive layer inside the contact hole. Forming a layer, removing the first and second conductive layers excluding the plug periphery, etching the insulating layer to a predetermined depth from a surface, and forming a second metal wiring on the substrate to be in contact with the plug. Forming comprising the step of forming.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 다층 금속배선의 제조공정을 간소화시키도록 한 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a metal wiring of a semiconductor device to simplify a manufacturing process of a multilayer metal wiring.
일반적으로 다층배선을 이용하는 제품을 만드는 경우 층간의 배선을 연결하는 콘택(Contact)이 층간에 직렬로 되어 있을 경우에는 배선간의 절연층 두께 만큼의 깊이를 갖는 콘택에 알루미늄(Al)을 직접 채울 수 없다.In general, when a product using a multi-layer wiring is made, when a contact connecting the wirings between layers is in series between layers, aluminum (Al) cannot be directly filled in a contact having a depth equal to the thickness of the insulating layer between the wirings. .
그래서 CVD(Chermical Vapor Deposition) 방식으로 텅스텐을 콘택홀 내부에 채우고 남도록 두껍게 증착하여 에치백 공정을 실시하여 콘택홀 내부에 텅스텐 플러그를 형성한다.Thus, tungsten is deposited inside the contact hole by CVD (Chemmical Vapor Deposition) method and deposited thickly so as to remain to form an etchback process to form a tungsten plug inside the contact hole.
그러나 텅스텐 플러그를 형성할 때 제품의 전체구조 즉, 단차가 높은 부분과 낮은 부분의 단차 정도와 기울기 정도에 따라 텅스텐이 콘택홀을 제외한 다른 부분에 남는 것을 방지하기 위해 충분히 식각해주게 되는데 이때 텅스텐 플러그의 손실이 많아져 이후 배선공정이 복잡해지는 것을 알 수 있다.However, when the tungsten plug is formed, the entire structure of the product, that is, the degree of inclination and the degree of inclination of the high and low parts, is sufficiently etched to prevent the tungsten from remaining in the other parts except the contact hole. It can be seen that the losses are more complicated then the wiring process.
이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 금속배선 형성방법을 설명하면 다음과 같다.Hereinafter, a metal wiring forming method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 종래의 반도체 소자의 금속배선 형성방법을 나타낸 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming metal wirings in a conventional semiconductor device.
먼저, 도 1a에 도시한 바와같이 반도체 기판(11)상에 금속층을 증착하고, 상기 금속층을 사진석판술 및 식각공정으로 선택적으로 제거하여 상기 반도체 기판(11)상에 제 1 금속배선(12)을 형성한다.First, as shown in FIG. 1A, a metal layer is deposited on the semiconductor substrate 11, and the metal layer is selectively removed by photolithography and etching, thereby forming the first metal wiring 12 on the semiconductor substrate 11. To form.
이어, 상기 제 1 금속배선(12)을 포함한 반도체 기판(11)의 전면에 절연막(13)을 형성하고, 상기 제 1 금속배선(12)의 표면이 일정부분 노출되도록 상기 절연막(13)을 선택적으로 제거하여 콘택홀(Contact Hole)(14)을 형성한다.Next, an insulating film 13 is formed on the entire surface of the semiconductor substrate 11 including the first metal wiring 12, and the insulating film 13 is selectively selected so that the surface of the first metal wiring 12 is partially exposed. To form a contact hole 14.
도 1b에 도시한 바와같이 상기 콘택홀(14)을 포함한 반도체 기판(11)의 전면에 제 1 티타늄(Ti)막(15)과 제 1 티타늄 질화막(TiN)(16)을 차례로 형성하고, 상기 제 1 티타늄 질화막(16)을 포함한 반도체 기판(11)의 전면에 CVD(Chemical Vapor Deposition)법으로 텅스텐(17)을 증착한다.As shown in FIG. 1B, a first titanium (Ti) film 15 and a first titanium nitride film (TiN) 16 are sequentially formed on the entire surface of the semiconductor substrate 11 including the contact hole 14. Tungsten 17 is deposited on the entire surface of the semiconductor substrate 11 including the first titanium nitride film 16 by CVD (Chemical Vapor Deposition).
여기서 상기 제 1 티타늄막(15)과 제 1 티타늄 질화막(16)은 일반적으로 텅스텐과 절연막과의 접착도가 좋지 않아서 절연막상에 텅스텐을 증착하는 경우에 에지(Edge) 부분에 들뜨는 현상이 발생하여 불량이 발생하게 된다.In this case, the first titanium film 15 and the first titanium nitride film 16 generally have poor adhesion between tungsten and the insulating film. Thus, when tungsten is deposited on the insulating film, a phenomenon occurs in the edge part. Defects will occur.
이런 현상을 방지하고자 절연막과 접착도가 좋은 상기 제 1 티타늄막(15)과 제 1 티타늄 질화막(16)을 증착한 후, 상기 텅스텐(17)을 증착한다.In order to prevent this phenomenon, the first titanium film 15 and the first titanium nitride film 16 having good adhesion with the insulating film are deposited, and then the tungsten 17 is deposited.
그리고 상기 텅스텐(17)은 상기 제 1 티타늄 질화막(16)의 표면으로부터 3000Å 이상으로 상기 콘택홀(14)을 채우고 남도록 증착한다.The tungsten 17 is deposited so as to fill and leave the contact hole 14 at 3000 Å or more from the surface of the first titanium nitride film 16.
도 1c에 도시한 바와같이 상기 텅스텐(17)의 전면에 에치백 공정을 실시하여 상기 콘택홀(14)내부에 텅스텐 플러그(17a)를 형성한다.As shown in FIG. 1C, an etchback process is performed on the entire surface of the tungsten 17 to form a tungsten plug 17a in the contact hole 14.
이때 상기 텅스텐 플러그(17a)는 상기 제 1 티타늄 질화막(16)의 표면까지 상기 텅스텐(17)을 모두 식각함으로 상기 콘택홀(14)내부에만 상기 제 1 티타늄 질화막(16)의 표면과 동일 높이로 텅스텐 플러그(17a)를 형성해야 하는데 상기 텅스텐 플러그(17a)는 제 1 티타늄 질화막(16)의 표면으로부터 적게는 몇 백 Å부터 몇 천 Å까지 들어가게 형성된다.At this time, the tungsten plug 17a etches all the tungsten 17 to the surface of the first titanium nitride film 16 so that only the inside of the contact hole 14 is flush with the surface of the first titanium nitride film 16. A tungsten plug 17a should be formed, which is formed so as to enter from a few hundred kW to several thousand kW from the surface of the first titanium nitride film 16.
도 1d에 도시한 바와같이 상기 텅스텐 플러그(17a)가 상기 제 1 티타늄 질화막(16)의 표면과 단차가 심하기 때문에 단차를 줄이기 위해 상기 텅스텐 플러그(17a)를 포함한 반도체 기판(11)의 전면에 200 ~ 300Å 두께의 제 2 티타늄막(18)과 500 ~ 1000Å 두께의 제 2 티타늄 질화막(19)을 차례로 형성한다.As shown in FIG. 1D, since the tungsten plug 17a is severely stepped with the surface of the first titanium nitride film 16, the front surface of the semiconductor substrate 11 including the tungsten plug 17a is reduced in order to reduce the step difference. A second titanium nitride film 18 having a thickness of ˜300 kPa and a second titanium nitride film 19 having a thickness of 500˜1000 kPa are formed in this order.
이어, 상기 제 2 티타늄 질화막(19)을 포함한 반도체 기판(11)의 전면에 PVD(Physical Vapor Deposition)법으로 알루미늄을 증착하여 제 2 금속배선(20)을 형성한다.Subsequently, aluminum is deposited on the entire surface of the semiconductor substrate 11 including the second titanium nitride layer 19 by PVD (Physical Vapor Deposition) to form a second metal wiring 20.
이때 상기 제 2 금속배선(20)을 형성하기 위해 알루미늄의 증착은 리플로우(Reflow)라는 방식을 사용하는데 이 방식은 고온에서 알루미늄을 녹여 콘택홀을 채운 후 다시 저온에서 응고시키는 방법을 써서 전기 전도 특성을 좋게한다.At this time, in order to form the second metal wiring 20, deposition of aluminum uses a reflow method, which melts aluminum at a high temperature to fill a contact hole, and then solidifies again at a low temperature. Improve the properties.
그러나 이와 같은 종래의 반도체 소자의 금속배선 형성방법에 있어서 다음과 같은 문제점이 있었다.However, in the conventional method of forming metal wiring of the semiconductor device, there are the following problems.
즉, 에치백 공정을 실시하여 텅스텐 플러그를 형성하기 위해 텅스텐을 티타늄 질화막의 표면까지 식각할 경우 콘택홀 내부의 텅스텐 플러그의 손실이 많고, 이후 공정에서 리플로우 방식을 사용하여 알루미늄을 증착하는 공정이 복잡하고 많은 시간이 소요된다.That is, when the tungsten is etched to the surface of the titanium nitride film to perform the etch back process to form the tungsten plug, there is a large loss of the tungsten plug inside the contact hole, and a process of depositing aluminum using a reflow method in the subsequent process is performed. It is complicated and time consuming.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 텅스텐 플러그의 손실을 최소로하여 이후 공정을 간소화시키도록 한 반도체 소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above problems, and an object thereof is to provide a method for forming a metal wiring of a semiconductor device to minimize the loss of a tungsten plug and simplify the subsequent process.
도 1a 내지 도 1d는 종래의 반도체 소자의 금속배선 형성방법을 나타낸 공정단면도1A through 1D are cross-sectional views illustrating a method of forming metal wirings in a conventional semiconductor device.
도 2a 내지 도 2f는 본 발명에 의한 반도체 소자의 금속배선 형성방법을 나타낸 공정단면도2A through 2F are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
21 : 반도체 기판 22 : 제 1 금속배선21 semiconductor substrate 22 first metal wiring
23 : 절연막 24 : 콘택홀23 insulating film 24 contact hole
25 : 티타늄막 26 : 티타늄 질화막25: titanium film 26: titanium nitride film
27 : 텅스텐 27a : 텅스텐 플러그27: tungsten 27a: tungsten plug
28 : 제 2 금속배선28: second metal wiring
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 금속배선 형성방법은 반도체 기판상에 일정한 폭을 갖는 제 1 금속배선을 형성하는 단계와, 상기 제 1 금속배선의 표면이 소정부분 노출되도록 콘택홀을 갖는 절연막을 형성하는 단계와, 상기 콘택홀을 포함한 기판의 전면에 제 1, 제 2 도전층을 형성하는 단계와, 상기 콘택홀 내부의 제 2 도전층상에 플러그를 형성하는 단계와, 상기 플러그 주변을 제외한 제 1, 제 2 도전층을 제거하는 단계와, 상기 절연막을 표면으로부터 소정깊이로 식각하는 단계와, 그리고 상기 플러그와 콘택되도록 기판상에 제 2 금속배선을 형성하는 단계를 포함하여 형성함을 특징으로 한다.In order to achieve the above object, a method of forming a metal wiring of a semiconductor device according to the present invention includes forming a first metal wiring having a predetermined width on a semiconductor substrate, and exposing a surface of the first metal wiring to a predetermined portion. Forming an insulating film having a contact hole, forming first and second conductive layers on the entire surface of the substrate including the contact hole, forming a plug on the second conductive layer inside the contact hole; Removing the first and second conductive layers except for the plug periphery, etching the insulating film to a predetermined depth from a surface, and forming a second metal wiring on the substrate to be in contact with the plug. It is characterized by forming.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 금속배선 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a metal wiring forming method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명에 의한 반도체 소자의 금속배선 형성방법을 나타낸 공정단면도이다.2A to 2F are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to the present invention.
먼저, 도 2a에 도시한 바와같이 반도체 기판(21)상에 금속층을 증착하고, 상기 금속층을 사진석판술 및 식각공정으로 선택적으로 제거하여 상기 반도체 기판(21)상에 제 1 금속배선(22)을 형성한다.First, as illustrated in FIG. 2A, a metal layer is deposited on the semiconductor substrate 21, and the metal layer is selectively removed by photolithography and etching to remove the metal layer on the semiconductor substrate 21. To form.
이어, 상기 제 1 금속배선(22)을 포함한 반도체 기판(21)의 전면에 절연막(23)을 형성하고, 상기 제 1 금속배선(22)의 표면이 일정부분 노출되도록 절연막(23)을 선택적으로 제거하여 콘택홀(Contact Hole)(24)을 형성한다.Subsequently, an insulating film 23 is formed on the entire surface of the semiconductor substrate 21 including the first metal wiring 22, and the insulating film 23 is selectively exposed to expose a portion of the surface of the first metal wiring 22. The contact hole 24 is formed by removing the contact hole 24.
도 2b에 도시한 바와같이 상기 콘택홀(24)을 포함한 반도체 기판(21)의 전면에 티타늄(Ti)막(25)과 티타늄 질화막(TiN)(26)을 차례로 형성하고, 상기 티타늄 질화막(26)을 포함한 반도체 기판(21)의 전면에 CVD(Chemical Vapor Deposition)법으로 텅스텐(27)을 증착한다.As shown in FIG. 2B, a titanium (Ti) film 25 and a titanium nitride film (TiN) 26 are sequentially formed on the entire surface of the semiconductor substrate 21 including the contact hole 24, and the titanium nitride film 26 is formed. The tungsten 27 is deposited on the entire surface of the semiconductor substrate 21 including the () by chemical vapor deposition (CVD).
여기서 상기 텅스텐(27)은 상기 절연막(23)과 접착도가 좋지 않기 때문에 상기 절연막(23)과 접착도가 좋은 상기 티타늄막(25)과 티타늄 질화막(26)을 증착한 후, 상기 텅스텐(27)을 증착한다.Here, since the tungsten 27 has poor adhesion with the insulating film 23, the titanium film 25 and the titanium nitride film 26 having good adhesion with the insulating film 23 are deposited, and then the tungsten 27 E).
그리고 상기 텅스텐(27)은 상기 티타늄 질화막(26)의 표면으로부터 3000Å 이상으로 상기 콘택홀(24)을 채우고 남도록 증착한다.The tungsten 27 is deposited so as to fill and leave the contact hole 24 at 3000 Å or more from the surface of the titanium nitride film 26.
도 2c에 도시한 바와같이 상기 텅스텐(27)의 전면에 에치백 공정을 실시하여 상기 콘택홀(24)내부에 텅스텐 플러그(27a)를 형성한다.As illustrated in FIG. 2C, an etchback process is performed on the entire surface of the tungsten 27 to form a tungsten plug 27a in the contact hole 24.
이때 상기 텅스텐 플러그(27a)는 상기 티타늄 질화막(26)의 표면까지 상기 텅스텐(27)을 모두 식각함으로 상기 콘택홀(24)내부에만 상기 티타늄 질화막(26)의 표면과 동일 높이로 텅스텐 플러그(27a)를 형성해야 하는데 상기 텅스텐 플러그(27a)는 티타늄 질화막(26)의 표면으로부터 적게는 몇 백 Å부터 몇 천 Å까지 들어가게 형성된다.At this time, the tungsten plug 27a etches all the tungsten 27 to the surface of the titanium nitride film 26 so that the tungsten plug 27a is flush with the surface of the titanium nitride film 26 only inside the contact hole 24. The tungsten plug 27a is formed to enter from as few as several hundred microseconds to several thousand microseconds from the surface of the titanium nitride film 26.
도 2d에 도시한 바와같이 상기 텅스텐 플러그(27a)의 주변을 제외한 상기 티타늄 질화막(26)과 티타늄막(25)을 제거한다.As shown in FIG. 2D, the titanium nitride film 26 and the titanium film 25 except for the periphery of the tungsten plug 27a are removed.
도 2e에 도시한 바와같이 상기 절연막(23)을 표면으로부터 300 ~ 500Å정도 식각하는데, 이때 식각방법은 불소(F)기의 가스를 산소(O2)(100sccm)가스에 소량(5 ~ 15sccm) 첨가하여 고밀도 플라즈마 장비에서 식각공정을 실시한다.As shown in FIG. 2E, the insulating film 23 is etched from about 300 to 500 kPa from the surface, wherein the etching method is a small amount (5 to 15 sccm) of fluorine (F) gas into oxygen (O 2 ) (100 sccm) gas. In addition, the etching process is performed in a high density plasma apparatus.
여기서 상기 고밀도 플라즈마 장비에서 플라즈마를 방전시키는 소스 파워(Source Power)는 2000 W 정도로 사용하고, 식각 가스의 직진성을 유도하는 반도체 기판(21)이 놓이는 쪽에 바이어스 파워(Bias Power)를 200 ~ 300 W 정도 가하면 상기 텅스텐 플러그(27a)가 형성된 콘택홀(24) 입구 부분은 0.2㎛ 정도로 넓게 커지고 전체적으로 절연막(23)의 두께가 감소한다.Here, the source power for discharging the plasma in the high density plasma equipment is about 2000 W, and the bias power is about 200 to 300 W on the side where the semiconductor substrate 21 for inducing the straightness of the etching gas is placed. In this case, the inlet portion of the contact hole 24 in which the tungsten plug 27a is formed is widened to about 0.2 μm and the thickness of the insulating film 23 is reduced as a whole.
도 2f에 도시한 바와같이 상기 콘택홀(24)내부에 형성된 상기 텅스텐 플러그(27a)을 포함한 반도체 기판(21)의 전면에 PVD(Physical Vapor Deposition)법으로 알루미늄을 증착하여 제 2 금속배선(28)을 형성한다.As shown in FIG. 2F, aluminum is deposited on the entire surface of the semiconductor substrate 21 including the tungsten plug 27a formed in the contact hole 24 by PVD (Physical Vapor Deposition) to form a second metal wiring 28. ).
이상에서 설명한 바와같이 본 발명에 의한 반도체 소자의 금속배선 형성방법에 있어서 다음과 같은 효과가 있다.As described above, the metal wiring formation method of the semiconductor device according to the present invention has the following effects.
첫째, 텅스텐 플러그를 형성한 후 티타늄막과 티타늄 질화막을 제거하고 절연막을 소정깊이로 식각함으로써 텅스텐 플러그의 손실을 최소로 할 수 있다.First, after forming the tungsten plug, the loss of the tungsten plug can be minimized by removing the titanium film and the titanium nitride film and etching the insulating film to a predetermined depth.
둘째, 고밀도 플라즈마 장비에서 산소가스에 불소가스를 첨가함으로써 콘택홀 주위의 사이즈를 키우기 때문에 이후 금속배선 형성시 전기 전도 특성을 향상 시킬 수 있다.Second, since the fluorine gas is added to the oxygen gas in the high-density plasma equipment to increase the size around the contact hole, it is possible to improve the electrical conduction property when forming the metal wiring.
셋째, 텅스텐 플러그가 표면과 단차가 적기 때문에 알루미늄을 증착할 때 리플로우 방식을 생략함으로써 공정이 간소하고, 시간도 단축할 수 있다.Third, since the tungsten plug has a small step from the surface, the process can be simplified and the time can be shortened by eliminating the reflow method when depositing aluminum.
Claims (5)
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