KR19980073904A - Multilayer Circuit Board and Manufacturing Method Thereof - Google Patents
Multilayer Circuit Board and Manufacturing Method Thereof Download PDFInfo
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- KR19980073904A KR19980073904A KR1019970009488A KR19970009488A KR19980073904A KR 19980073904 A KR19980073904 A KR 19980073904A KR 1019970009488 A KR1019970009488 A KR 1019970009488A KR 19970009488 A KR19970009488 A KR 19970009488A KR 19980073904 A KR19980073904 A KR 19980073904A
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- circuit board
- insulating
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
- H05K3/4608—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated comprising an electrically conductive base or core
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
Abstract
본 발명은 다층회로기판 및 그 제조방법에 관한 것이다. 본 발명에 따르면 상, 하면 사이를 관통하며 측벽이 절연수지로 절연처리된 제1 쑤루홀이 복수개 구비된 메탈코어, 상기 메탈코어의 상, 하면에 적층된 절연수지층, 상기 절연수지층 위에 적층되며 회로패턴이 형성된 감광성 절연물질층, 상기 회로패턴을 상호 도통시키기 위해 상기 제1 쑤루홀의 내부에 주입된 전도성 부재, 상기 감광성 절연물질층 위에 적층되며 상기 회로패턴을 외부 또는 다른층의 회로와 전기적으로 접속시키는 제2 쑤루홀이 형성되어 있는 절연층을 포함하여 된 다층회로기판 및 그 제조방법이 제공된다. 본 발명인 다층회로기판 및 그 제조방법에서는 회로기판의 열적변형이 발생하지 않으므로 신뢰성이 향상되며, 기판 제조공정이 단순화 된다는 장점이 있다.The present invention relates to a multilayer circuit board and a method of manufacturing the same. According to the present invention, a metal core having a plurality of first through-holes having sidewalls insulated with an insulating resin and penetrating between upper and lower surfaces, an insulating resin layer laminated on upper and lower surfaces of the metal core, and laminated on the insulating resin layer And a photosensitive insulating material layer having a circuit pattern formed thereon, a conductive member injected into the first through hole to mutually conduct the circuit pattern, and stacked on the photosensitive insulating material layer to electrically connect the circuit pattern with a circuit of an external or other layer. Provided is a multilayer circuit board including an insulating layer having a second through hole connected thereto, and a method of manufacturing the same. In the present invention, the multilayer circuit board and the method of manufacturing the same have advantages in that thermal deformation of the circuit board does not occur, thereby improving reliability and simplifying the board manufacturing process.
Description
본 발명은 다층회로기판에 관한 것으로서, 좀더 상세하게는 회로기판의 구조를 개선하여 열적변형이 발생하지 않고 제조공정이 단순화 된 다층회로기판 및 그 제조방법에 관한 것이다.The present invention relates to a multilayer circuit board, and more particularly, to a multilayer circuit board and a method of manufacturing the same, by improving the structure of the circuit board, without the thermal deformation occurring, and the manufacturing process being simplified.
반도체 패키지용 기판으로 단층 및 다층의 기판이 널리 사용되고 있다. 특히, 고직접화에 따른 추세에 맞추어 소형의 기판에 다수의 소자를 집적할 수 있는 다층회로기판에 관한 연구가 활발히 진행중에 있다.Single and multilayer substrates are widely used as substrates for semiconductor packages. In particular, in accordance with the trend of high directivity, research on a multilayer circuit board capable of integrating a large number of devices in a small substrate is being actively conducted.
종래에는 칩 캐리어 또는 PCB용 기재 기판으로서 고가의 세라믹 기판을 사용하거나 또는 폴리아미드계 수지, 플루오로계 수지 및 실리콘계 수지 등을 소재로 하는 수지 기판을 사용하여 왔다. 상기 세라믹 기판이나 수지 기판은 모두 그 소재가 절연성이기 때문에 홀을 형성하고 그 홀내에 전도성 부재를 형성하더라도 쇼트 현상이 일어나는 경우가 없으며, 따라서 상기 세라믹 기판 또는 수지 기판에 대해서는 절연물질을 도포하는 별도 공정을 실시하지 않아도 된다.Conventionally, expensive ceramic substrates have been used as chip carriers or PCB substrate substrates, or resin substrates made of polyamide resins, fluoro resins, silicone resins, and the like have been used. Since the ceramic substrate and the resin substrate are both insulating materials, even if a hole is formed and a conductive member is formed in the hole, a short phenomenon does not occur. Therefore, a separate process of applying an insulating material to the ceramic substrate or the resin substrate. It is not necessary to carry out.
하지만, 수지 기판은 그 재료가 고가이며, 내습성 및 내열성 등이 불량하다는 단점이 있다. 따라서, 상기 수지 기판이 칩 캐리어용 기판으로 제작될 때, 기판의 휨발생 및 칩의 크랙 등이 발생할 수 있다는 문제점이 있다. 또한, 상기 세라믹 기판은 내열성에서는 우수하지만 마찬가지로 고가이며, 레이저 가공을 주로 해야하는 가공상의 어려움이 있다는 문제점이 있다.However, the resin substrate has a disadvantage that its material is expensive and its moisture resistance and heat resistance are poor. Therefore, when the resin substrate is manufactured as a chip carrier substrate, there is a problem that warpage of the substrate and cracks of the chip may occur. In addition, the ceramic substrate is excellent in heat resistance, but is also expensive, and there is a problem in that there is a difficulty in processing that requires mainly laser processing.
이러한 종래 기재 기판의 문제점을 극복하기 위해 메탈코어를 사용하는 회로기판이 공지된 바 있다. 그러나, 이 경우, 회로패턴을 형성하기 위해 기판에 감광물질층을 적층하여 패턴을 형성한 후, 식각공정 등을 실시함으로써 회로패턴을 형성한다. 이어서, 상기 감광물질층을 박리하는 공정이 필요하므로 전체적인 제작공정이 복잡해진다는 문제점이 있다.In order to overcome the problems of the conventional substrate, a circuit board using a metal core has been known. However, in this case, after forming a pattern by laminating a photosensitive material layer on a substrate to form a circuit pattern, the circuit pattern is formed by performing an etching process or the like. Subsequently, since the process of peeling the photosensitive material layer is necessary, there is a problem that the overall manufacturing process is complicated.
본 발명은 상기와 같은 문제점을 감안하여 창출된 것으로서, 열적변형이 발생하지 않는 신뢰성이 향상되고, 제작공정이 단순화 된 다층회로기판 및 그 제조방법을 제공하는데 그 목적이 있다.The present invention has been made in view of the above problems, and an object thereof is to provide a multilayer circuit board and a method of manufacturing the same, which improves reliability in which thermal deformation does not occur and simplifies the manufacturing process.
도 1은 본 발명에 따른 다층회로기판을 도시한 단면도.1 is a cross-sectional view showing a multilayer circuit board according to the present invention.
도 2는 본 발명에 따른 다층회로기판 제조방법을 도시한 공정흐름도.2 is a process flow diagram illustrating a method for manufacturing a multilayer circuit board according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
10.메탈코어11.제1 쑤루홀10.Metal Core 11
12.절연수지층13.회로패턴12. Insulation resin layer 13. Circuit pattern
14.감광성 절연물질층15.전도성 부재14. Layer of photosensitive insulating material 15. Conductive member
16.절연층17.제2 쑤루홀16.Insulation layer 17.Second hole
상기와 같은 목적을 달성하기 위해 본 발명인 다층회로기판은, 상, 하면 사이를 관통하며 측벽이 절연수지로 절연처리된 제1 쑤루홀이 복수개 구비된 메탈코어, 상기 메탈코어의 상, 하면에 적층된 절연수지층, 상기 절연수지층 위에 적층되며 회로패턴이 형성된 감광성 절연물질층, 상기 회로패턴을 상호 도통시키기 위해 상기 제1 쑤루홀의 내부에 주입된 전도성 부재, 상기 감광성 절연물질층 위에 적층되며 상기 회로패턴을 외부 또는 다른층의 회로와 전기적으로 접속시키는 제2 쑤루홀이 형성되어 있는 절연층을 포함하는 것을 특징으로 하는 다층회로기판이다.In order to achieve the above object, a multi-layer circuit board of the present invention includes a metal core having a plurality of first through-holes penetrated between upper and lower surfaces and having sidewalls insulated with an insulating resin, and stacked on upper and lower surfaces of the metal core. The insulating resin layer, the photosensitive insulating material layer laminated on the insulating resin layer and having a circuit pattern formed thereon, a conductive member injected into the first through hole to mutually conduct the circuit pattern, and laminated on the photosensitive insulating material layer A multi-layer circuit board comprising an insulating layer having a second through hole electrically connecting a circuit pattern to a circuit of an external or other layer.
또한, 본 발명인 다층회로기판 제조방법은, a) 메탈코어에 홀을 형성한 후, 절연수지를 상기 홀이 형성된 소재의 양면에 압착하는 단계; b) 상기 절연수지가 채워진 홀내에 제1 쑤루홀을 형성한 후, 상기 제1 쑤루홀에 전도성 부재를 삽입하는 단계; c) 상기 단계 b)후의 결과물의 상면에 감광성 물질을 도포하고, 상기 감광성 물질에 패턴을 형성하는 단계; d) 상기 감광성 물질에 형성된 패턴에 전도성 부재를 삽입하여 회로패턴을 형성하는 단계; e) 상기 단계 d)후 결과물의 상면에 절연층을 도포한 후, 상기 절연층에 홀을 형성한 후, 상기 홀에 전도성 부재를 삽입하여 제2 쑤루홀을 형성하는 단계; f) 상기 단계 e)후 결과물의 하면에 감광성 물질을 도포하고 패턴을 형성한 후, 상기 패턴에 전도성 부재를 삽입하여 회로패턴을 형성하는 단계; g) 상기 단계 f)후 결과물의 하면에 절연층을 도포하고 홀을 형성한 후, 상기 홀에 전도성 부재를 삽입하여 제2 쑤루홀을 형성하는 단계;를 포함하여 된 것을 특징으로 한다.In addition, the present invention is a method of manufacturing a multilayer circuit board, a) forming a hole in the metal core, the step of pressing the insulating resin on both sides of the material in which the hole is formed; b) forming a first through hole in the hole filled with the insulating resin, and then inserting a conductive member into the first through hole; c) applying a photosensitive material to the upper surface of the resultant after step b) and forming a pattern on the photosensitive material; d) forming a circuit pattern by inserting a conductive member into the pattern formed on the photosensitive material; e) applying an insulating layer to the upper surface of the resultant after step d), and then forming a hole in the insulating layer, inserting a conductive member into the hole to form a second through hole; f) applying a photosensitive material to the lower surface of the resultant after step e) and forming a pattern, and then inserting a conductive member into the pattern to form a circuit pattern; g) after the step f) after applying the insulating layer on the lower surface of the resultant to form a hole, by inserting a conductive member in the hole to form a second through-hole; characterized in that it comprises a.
이하 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명에 따른 다층회로기판의 일 실시예를 도시한 단면도이다.1 is a cross-sectional view showing an embodiment of a multilayer circuit board according to the present invention.
도면을 참조하면, 본 발명에 따른 다층회로기판은 지지층인 메탈코어에 대하여 복수개의 회로패턴층이 각각 적층되는 것으로서 그 구조는 다음과 같다.Referring to the drawings, in the multilayer circuit board according to the present invention, a plurality of circuit pattern layers are laminated on the metal core serving as the support layer, and the structure thereof is as follows.
상, 하면 사이를 관통하며 측벽이 절연수지로 절연처리된 제1 쑤루홀(11)을 복수개 구비하는 메탈코어(10)의 상, 하면에 절연수지층(12)이 적층되어 있다. 여기서, 상기 메탈코어(10)는 흑화 처리할 수 있는 금속 예컨대, 구리 등이 바람직하다. 또한, 상기 절연수지층(12)은 예컨대, 프리프레그층인 것이 바람직하다. 여기서, 프리프레그는 직물, 매트 등과 같은 연속한 보강재에 열경화성 수지를 함침시킨 적층 성형 재료를 말하며, 이때 열경화성 수지로는 폴리에스테르 수지, 에폭시수지, 페놀수지 등이 사용된다.The insulating resin layer 12 is stacked on the upper and lower surfaces of the metal core 10 having a plurality of first through-holes 11 having sidewalls insulated with the insulating resin and penetrating between the upper and lower surfaces. Here, the metal core 10 is preferably a metal which can be blackened, for example, copper. In addition, the insulating resin layer 12 is preferably a prepreg layer. Here, the prepreg refers to a laminated molding material in which a thermosetting resin is impregnated into a continuous reinforcing material such as a fabric or a mat. In this case, a polyester resin, an epoxy resin, a phenol resin, or the like is used as the thermosetting resin.
상기 절연수지층(12)의 상, 하면에 회로패턴(13a)(13b)이 형성되는 감광성 절연물질층(14a)(14b)과, 상기 제1회로패턴(13a)(13b)이 상호 도통되도록 상기 제1 쑤루홀(11)의 내부에 주입된 전도성 부재(15)가 마련된다. 여기서, 상기 전도성 부재(15)는 전도성 잉크인 것이 바람직하며, 상기 전도성 잉크는 미세 금속분말과, 중합반응물질과, 용매로 구성되며, 미합중국 토라나가(Toranaga)사에서 개발된 제품 등을 이용할 수 있다.The photosensitive insulating material layers 14a and 14b having the circuit patterns 13a and 13b formed on and under the insulating resin layer 12 and the first circuit patterns 13a and 13b are connected to each other. The conductive member 15 injected into the first through-hole 11 is provided. Here, the conductive member 15 is preferably a conductive ink, the conductive ink is composed of a fine metal powder, a polymerization reaction material, a solvent, and can use a product developed by Toranaga, Inc. have.
상기 감광성 절연물질층(14a)(14b)에는 절연층(16a)(16b)이 적층되고, 상기 제1회로패턴(13a)(13b)을 외부 또는 후술하는 제2회로패턴과 상호 도통시키는 전도성 잉크가 내제된 제 2쑤루홀(17)이 상기 절연층(16a)(16b)에 각각 형성된다.Insulating layers 16a and 16b are stacked on the photosensitive insulating material layers 14a and 14b, and conductive ink for mutually conducting the first circuit patterns 13a and 13b with external or second circuit patterns described later. The second through holes 17 formed therein are formed in the insulating layers 16a and 16b, respectively.
그리고, 상기 절연층(16)에는 회로패턴(13)이 형성되는 감광성 절연물질층(14)과 절연층(16)이 교대로 적층되는 복수개의 회로패턴층(100)이 형성될 수 있다.In addition, a plurality of circuit pattern layers 100 in which the photosensitive insulating material layer 14 on which the circuit pattern 13 is formed and the insulating layer 16 are alternately stacked may be formed on the insulating layer 16.
상술한 구조의 다층회로기판은, 기판의 소재인 메탈코어(10)의 양면에 프리프레그층(12)을 형성하여 절연시키고, 감광성 절연물질층(14)을 적층한 후 전도성 잉크로써 회로패턴(13)을 형성하며, 절연층(16)을 적층함으로써, 메탈코어(10)를 중심으로 각각의 층이 대칭구조가 된다. 따라서, 열적변형이 작은 메탈코어(10)가 중심에 있고, 메탈코어(10)의 양측면에 적층된 각각의 층이 서로 대칭의 구조이므로 각각의 대응되는 층의 열팽창계수가 같게 된다.In the multilayer circuit board having the above-described structure, the prepreg layer 12 is formed and insulated on both sides of the metal core 10, which is a material of the substrate, and the photosensitive insulating material layer 14 is laminated, and then the circuit pattern is formed with conductive ink. 13) and by stacking the insulating layer 16, each layer is symmetrical structure around the metal core 10. FIG. Therefore, since the metal core 10 having a small thermal deformation is at the center, and the layers stacked on both sides of the metal core 10 are symmetrical with each other, the thermal expansion coefficient of each corresponding layer becomes the same.
도 2는 본 발명에 따른 다층회로기판 제조방법의 일 실시예를 나타낸 공정흐름도이다.2 is a process flowchart showing an embodiment of a method for manufacturing a multilayer circuit board according to the present invention.
먼저, 기판의 소재 예컨대, 메탈코어(21)를 준비하고, 상기 메탈코어(21)를 식각하거나 타발하여 복수개의 홀(22)을 형성한다. 여기서, 상기 메탈코어(21)는 흑화처리가 가능한 예컨대, 구리 등의 금속인 것이 바람직하다. 이어서, 상기 홀(22)이 형성된 메탈코어(21)를 후술하는 절연수지층(23)과의 접착력을 향상시키기 위해 흑화 처리한 다음, 상기 메탈코어(21)의 상, 하면에 절연수지(23)를 압착법 예컨대, 열압착법에 의해 압착한다. 이때, 상기 절연수지(23)는 상기 메탈코어(21)에 형성되어 있는 홀(22)을 채우게 된다. 여기서, 상기 절연수지층(23)은 프리프레그층인 것이 바람직하다(S100).First, a material of a substrate, for example, the metal core 21 is prepared, and the plurality of holes 22 are formed by etching or punching the metal core 21. Here, the metal core 21 is preferably a metal such as copper, which can be blackened. Subsequently, the metal core 21 on which the holes 22 are formed is blackened to improve adhesion to the insulating resin layer 23 described later, and then the insulating resin 23 is disposed on the upper and lower surfaces of the metal core 21. ) Is pressed by a compression method, for example, a thermocompression method. In this case, the insulating resin 23 fills the hole 22 formed in the metal core 21. Here, the insulating resin layer 23 is preferably a prepreg layer (S100).
다음, 상기 절연수지(23)가 채워진 홀(22)을 드릴링하여 그 내부에 제1 쑤루홀(24)을 형성하는데, 상기 제1 쑤루홀(24)의 직경은 상기 홀(22)의 직경보다 예컨대, 100 내지 200㎛ 작은 것이 바람직하다. 상기 제1 쑤루홀(24)이 형성된 메탈코어(21)의 양면을 도통시키기 위하여 상기 제1 쑤루홀(24)에 전도성 부재(25)를 삽입한다. 이때, 상기 전도성 부재(25)는 전도성 잉크인 것이 바람직하다(S110).Next, the hole 22 filled with the insulating resin 23 is drilled to form a first through hole 24 therein, the diameter of the first through hole 24 being larger than the diameter of the hole 22. For example, 100-200 micrometers small thing is preferable. The conductive member 25 is inserted into the first through hole 24 so as to conduct both surfaces of the metal core 21 on which the first through hole 24 is formed. At this time, the conductive member 25 is preferably conductive ink (S110).
이어서, 상기 결과물의 상면에 감광성 절연물질(26)을 도포하고, 도포된 감광성 절연물질(26)의 상부에 소정 패턴이 형성된 포토마스크(미도시)를 위치시킨 후 노광 및 현상을 통하여 패턴을 형성함으로써, 상기 감광성 절연물질층(26)에 후술하는 회로패턴(28) 형상의 여백(27)이 만들어진다(S120).Subsequently, the photosensitive insulating material 26 is coated on the upper surface of the resultant, a photomask (not shown) having a predetermined pattern is placed on the applied photosensitive insulating material 26, and then a pattern is formed through exposure and development. As a result, a margin 27 having a circuit pattern 28 to be described later is formed in the photosensitive insulating material layer 26 (S120).
다음, 상기 감광성 절연물질(26)층에 형성되어 있는 회로패턴(28) 형상의 여백에 전도성 잉크를 예컨대, 프린팅법으로 삽입한 후 경화함으로써, 기판의 상면에 회로패턴(28)이 형성된다(S130).Next, the conductive pattern is inserted into a margin in the shape of the circuit pattern 28 formed on the photosensitive insulating material 26 layer, for example, by printing and then cured to form a circuit pattern 28 on the upper surface of the substrate ( S130).
다음, 상기 결과물의 상면에 절연층(29)을 도포한 후, 상기 단계 S120 및 단계 S130을 반복 실시하여 상기 회로패턴(28)과 다른층의 회로패턴(미도시) 및 외부로 관통하는 제 2쑤루홀(30)을 형성한 후, 상기 제 2쑤루홀(30)의 내부에 전도성부재 예컨대, 전도성 잉크를 삽입함으로써, 상기 회로패턴(28)과 다른층의 회로패턴 및 외부를 전기적으로 도통시킨다(S140).Next, after applying the insulating layer 29 to the upper surface of the resultant, the steps S120 and S130 are repeatedly performed to form a circuit pattern (not shown) and a second layer penetrating outside of the circuit pattern 28. After the through hole 30 is formed, a conductive member, for example, a conductive ink, is inserted into the second through hole 30 to electrically conduct the circuit pattern 28 and the outside of the circuit pattern 28. (S140).
이어서, 상기 결과물의 하면에 대하여, 상기 단계 S120 내지 단계 S130을 실시함으로써, 즉, 감광성 절연물질층(26')을 형성하고, 상기 감광성 절연물질층(26')에 패턴을 형성한 후, 상기 감광성 절연물질층(26')에 전도성 잉크를 프린팅함으로써, 기판 하면에 회로패턴(28')이 형성된다(S150).Subsequently, by performing the steps S120 to S130 on the lower surface of the resultant, that is, forming the photosensitive insulating material layer 26 'and forming a pattern on the photosensitive insulating material layer 26', By printing the conductive ink on the photosensitive insulating material layer 26 ′, a circuit pattern 28 ′ is formed on the bottom surface of the substrate (S150).
다음, 상기 결과물의 하면에 절연층(29')을 도포한 후, 상기 단계 S120 내지 S130을 실시하여 상기 하면에 형성된 회로패턴(28')과 다른층의 회로패턴(미도시) 및 외부로 관통하는 제 2쑤루홀(30')을 형성한 후, 상기 제 2쑤루홀(30')의 내부에 전도성 부재 예컨대, 전도성 잉크를 삽입함으로써, 상기 하면에 형성된 회로패턴(28')과 다른층의 회로패턴 및 외부를 전기적으로 도통시킨다(S160).Next, after the insulating layer 29 'is applied to the lower surface of the resultant, the steps S120 to S130 are performed to pass through the circuit pattern (not shown) and the outside of the circuit pattern 28' formed on the lower surface. After the second through hole 30 'is formed, a conductive member, for example, a conductive ink is inserted into the second through hole 30' to form a layer different from the circuit pattern 28 'formed on the bottom surface. The circuit pattern and the outside are electrically connected (S160).
상술한 제조방법으로 제조된 회로기판에 대하여 상기 단계 S120 내지 단계 S140을 반복 실시하여 적층함으로써 복수개의 회로패턴이 적층된 구조인 다층회로기판을 제작할 수 있다.By repeating the steps S120 to S140 with respect to the circuit board manufactured by the above-described manufacturing method, a multilayer circuit board having a structure in which a plurality of circuit patterns are stacked may be manufactured.
상술한 구조의 다층회로기판은 감광성 절연물질(26)(26')을 도포하고, 도포된 감광성 절연물질(26)(26')층에 포토마스크를 이용하여 노광 및 현상을하여 패턴을 형성함으로써, 상기 감광성 절연물질층(26)(26')에 회로패턴(28)(28') 형상의 여백(27)을 만든 후 상기 여백(27)에 전도성 잉크(25)를 예컨대, 프린팅법으로 삽입한 후 경화함으로써, 기판의 상, 하면에 회로패턴(28)(28')이 형성된다.The multilayer circuit board having the above-described structure is coated with photosensitive insulating materials 26 and 26 ', and a pattern is formed by exposing and developing the photosensitive insulating materials 26 and 26' using a photomask. After forming the margins 27 of the circuit patterns 28 and 28 'in the photosensitive insulating layers 26 and 26', the conductive ink 25 is inserted into the margins 27 by, for example, printing. After curing, the circuit patterns 28 and 28 'are formed on the upper and lower surfaces of the substrate.
즉, 소재에 감광물질층을 적층하여 패턴을 형성한 후, 식각공정 등의 방법에 의해 회로패턴을 형성한 후, 다시 소재에서 감광물질층을 박리하는 단계를 거치는 종래의 기술과는 달리, 본 발명에 따른 다층회로기판은, 기판에 적층된 감광성 절연물질층(26)(26')에 패턴을 형성한 후, 전도성잉크(25)로써 회로패턴(28)(28')을 형성하여 경화시키고, 상기 회로패턴(28)(28')이 형성된 감광성 절연물질층(26)(26)에 절연층(29)(29')을 적층함으로써 감광성 절연물질층(26)(26')을 제거할 필요가 없게 된다. 또한, 회로패턴(28)(28')을 형성하기 위해 에칭 등의 방법을 사용하지 않으므로, 회로기판의 제조공정이 단순화된다.That is, unlike the conventional technology of forming a pattern by laminating a photosensitive material layer on a material, forming a circuit pattern by a method such as an etching process, and then peeling the photosensitive material layer from the material again, In the multilayer circuit board according to the present invention, after the pattern is formed on the photosensitive insulating material layers 26 and 26 'stacked on the substrate, the circuit patterns 28 and 28' are formed by the conductive ink 25 and cured. The photosensitive insulating material layers 26 and 26 'may be removed by stacking the insulating layers 29 and 29' on the photosensitive insulating material layers 26 and 26 on which the circuit patterns 28 and 28 'are formed. There is no need. In addition, since a method such as etching is not used to form the circuit patterns 28 and 28 ', the manufacturing process of the circuit board is simplified.
본 발명에 따른 다층회로기판은, 기판의 소재인 메탈코어의 양면에 프리프레그층을 형성시키고, 감광성 절연물질층 및 절연층을 적층시킴으로써, 메탈코어가 중심에 있고, 메탈코어의 양측면에 적층된 각각의 층이 서로 대칭의 구조이므로 각각의 대응되는 층의 열팽창계수가 같게 된다. 따라서, 회로기판의 열적변형이 최소화될 수 있다.In the multilayer circuit board according to the present invention, a prepreg layer is formed on both sides of a metal core, which is a material of a substrate, and a photosensitive insulating material layer and an insulating layer are laminated, whereby the metal core is centered and laminated on both sides of the metal core. Since each layer is symmetrical with each other, the coefficient of thermal expansion of each corresponding layer is the same. Therefore, thermal deformation of the circuit board can be minimized.
또한, 본 발명에 따른 다층회로기판의 제조방법은, 감광성 절연물질층에 패턴을 형성한 후, 전도성잉크로써 회로패턴을 형성하여 경화시키고, 상기 회로패턴이 형성된 감광성 절연물질층에 절연층을 적층함으로써, 감광성 절연물질층을 제거할 필요가 없으며, 회로패턴을 형성하기 위해 에칭 등의 공정을 따로 실시하지 않으므로 회로기판의 제조공정이 단순화된다는 장점이 있다.In addition, in the method for manufacturing a multilayer circuit board according to the present invention, after the pattern is formed on the photosensitive insulating material layer, the circuit pattern is formed and cured by conductive ink, and the insulating layer is laminated on the photosensitive insulating material layer on which the circuit pattern is formed. As a result, there is no need to remove the photosensitive insulating material layer, and there is an advantage in that the manufacturing process of the circuit board is simplified because the process such as etching is not separately performed to form the circuit pattern.
Claims (13)
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| KR100787096B1 (en) * | 2005-05-24 | 2007-12-21 | 진은호 | Network structure print method make use design method |
| WO2014104543A1 (en) * | 2012-12-26 | 2014-07-03 | 주식회사 두산 | Resin composition and metal core laminate comprising same |
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| KR100990543B1 (en) | 2008-06-23 | 2010-10-29 | 삼성전기주식회사 | Packaging substrate using metal core and manufacturing method thereof |
| KR100975927B1 (en) * | 2008-08-11 | 2010-08-13 | 삼성전기주식회사 | Method of manufacturing package board |
| KR101382811B1 (en) * | 2012-03-14 | 2014-04-08 | 엘지이노텍 주식회사 | The printed circuit board and the method for manufacturing the same |
| KR102168698B1 (en) | 2018-12-04 | 2020-10-21 | 주식회사 엠디엠 | Method for manufacturing multilayer electronic circuit on a surface of three-dimensional metal substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100787096B1 (en) * | 2005-05-24 | 2007-12-21 | 진은호 | Network structure print method make use design method |
| WO2014104543A1 (en) * | 2012-12-26 | 2014-07-03 | 주식회사 두산 | Resin composition and metal core laminate comprising same |
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