JPH10335831A - Multilayered wiring board and its manufacture - Google Patents

Multilayered wiring board and its manufacture

Info

Publication number
JPH10335831A
JPH10335831A JP10138327A JP13832798A JPH10335831A JP H10335831 A JPH10335831 A JP H10335831A JP 10138327 A JP10138327 A JP 10138327A JP 13832798 A JP13832798 A JP 13832798A JP H10335831 A JPH10335831 A JP H10335831A
Authority
JP
Japan
Prior art keywords
wiring pattern
layer
pattern
material substrate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10138327A
Other languages
Japanese (ja)
Inventor
Jae-Chul Ryu
在▲てつ▼ 柳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hanwha Aerospace Co Ltd
Original Assignee
Samsung Aerospace Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Aerospace Industries Ltd filed Critical Samsung Aerospace Industries Ltd
Publication of JPH10335831A publication Critical patent/JPH10335831A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0023Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0047Drilling of holes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/005Punching of holes

Abstract

PROBLEM TO BE SOLVED: To easily secure flatness and to form the wiring pattern of fine pitches by applying conductor ink to a pattern layer, where through-holes are carved, applying plating catalytic agent to the upper part of a result object which is hardened and stacked after silk screening and executing nonelectrolytic plating. SOLUTION: A photosensitive insulating layer 3 is formed on a metallic substrate 1, where a resin layer 2 is formed and a photo mask is insulated on it. It is exposed and developed, and the pattern layer where through-holes are carved in recessed forms is formed. Then, a conductive ink is applied to the pattern layer, it is silk-screened and hardened. Then, the wiring pattern 5 is formed, the process is repeated, and the layers are stacked. The result object to which plating catalytic agent is applied is non-electrolytically plated, and the wiring pattern 6 of the uppermost layer is formed. As a result, flatness in the uppermost part is superior, and the wiring pattern of fine pitches can be formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は多層プリント配線板
及びその製造方法に係り、更に詳細には、各層毎に貫通
孔(through hole)が形成されていながら
も偏平度が確保され、COB(Chip on Boa
rd)、BGA(Ball Grid Array)、
MCM(Multi Chip Module)などの
高機能化した複合型半導体パッケージのチップキャリア
用に利用できる多層プリント配線板及びその製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board and a method of manufacturing the same. on Boa
rd), BGA (Ball Grid Array),
The present invention relates to a multilayer printed wiring board that can be used for a chip carrier of a highly functional composite semiconductor package such as an MCM (Multi Chip Module) and a method of manufacturing the same.

【0002】[0002]

【従来の技術】半導体パッケージにおいて、チップの多
層化、複合化、高機能化、及び多機能化に従いチップキ
ャリアも多様な材質と構造を有するものが必要になり、
これにより貫通孔が各層毎に形成された多層PCBが製
造されるに至った。
2. Description of the Related Art In a semiconductor package, a chip carrier having various materials and structures is required in accordance with multi-layer, multi-layer, high-performance, and multi-functional chips.
As a result, a multilayer PCB in which a through hole is formed for each layer has been manufactured.

【0003】しかし、かかる多層PCBの製造方法はか
なり高度の技術を必要とする複雑な工程より構成されて
いるだけでなく、信頼性を確保しにくく、製造コストも
高いため、実用性に劣る。
[0003] However, such a method of manufacturing a multilayer PCB is not only composed of complicated steps requiring considerably high technology, but also has a low reliability and a high manufacturing cost, and is therefore inferior in practical use.

【0004】通常の多層PCB製造方法はエッチング手
法により行われる。これは、素材基板上に銅はくを積層
し、これをエッチして貫通孔を形成することにより各層
を製作した後に、これを積層する方法である。しかし、
この方法によれば、作業工数が多くなり、エッチング液
の使い過ぎによる環境汚染の問題も深刻である。また、
信頼性の確保のために高信頼性の素材を選択しなければ
ならないので、製造コストが高くなる。
[0004] The usual method of manufacturing a multilayer PCB is performed by an etching technique. This is a method in which copper foil is laminated on a material substrate, each layer is manufactured by etching the copper foil to form a through hole, and then laminated. But,
According to this method, the number of working steps increases, and the problem of environmental pollution due to excessive use of the etching solution is serious. Also,
Since high-reliability materials must be selected to ensure reliability, manufacturing costs increase.

【0005】もう他の方法は、各層を無電解銅メッキし
て多層PCBを製造する方法である。この方法は、偏平
度の確保やファインピッチの提供面から有用であるが、
製造時間とコストがかかり過ぎるため実用化しにくい。
Another method is to produce a multilayer PCB by plating each layer with electroless copper. This method is useful for securing flatness and providing fine pitch,
It is difficult to put into practical use because it takes too much production time and cost.

【0006】[0006]

【発明が解決しようとする課題】本発明が果たそうとす
る技術的課題は、偏平度の確保が容易で、ファインピッ
チの配線パターンが形成できると共に、製造コストが安
い多層PCBの製造方法を提供することである。
A technical problem to be solved by the present invention is to provide a method of manufacturing a multilayer PCB which can easily secure a flatness, can form a fine pitch wiring pattern, and has a low manufacturing cost. That is.

【0007】本発明が果たそうとする他の技術的課題
は、高機能化の複合型半導体パッケージに適用可能な多
層PCBを提供することである。
Another technical problem to be solved by the present invention is to provide a multi-layer PCB applicable to a highly functional composite semiconductor package.

【0008】[0008]

【課題を解決するための手段】本発明の技術的課題は、
a)素材基板上に感光性絶縁層を形成する段階と、b)
前記感光性絶縁層を露光及び現像し、貫通孔が陰刻され
たパターン層を形成する段階と、c)前記パターン層に
導電性インキを塗布し、シルクスクリーンを行なった後
に硬化させる段階と、d)前記段階a)−c)を繰返
し、所望の層数だけ積層する段階と、e)前記段階d)
の結果物の上部にメッキ触媒剤を塗布する段階と、f)
前記段階e)の結果物を無電解メッキし、最上層の配線
パターンを形成する段階とを含む多層プリント配線板の
製造方法により達成される。
Means for Solving the Problems The technical problems of the present invention are:
a) forming a photosensitive insulating layer on a material substrate; b)
Exposing and developing the photosensitive insulating layer to form a pattern layer in which through holes are inscribed; c) applying a conductive ink to the pattern layer, performing a silk screen, and then curing; d) E) repeating steps a) -c) and laminating the desired number of layers;
Applying a plating catalyst on top of the resulting product; f)
Forming the wiring pattern of the uppermost layer by electroless plating the resulting product of the step e).

【0009】本発明の他の技術的課題は、前記製造方法
に従い製造された多層PCBにより達成される。
Another technical object of the present invention is achieved by a multilayer PCB manufactured according to the above manufacturing method.

【0010】[0010]

【発明の実施の形態】以下に、本発明の内容を詳細に説
明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The contents of the present invention will be described below in detail.

【0011】本発明にかかる多層PCBの製造方法にお
いて、素材基板としては金属、セラミック、樹脂などこ
の分野において使用できるものなら特に制限しない。
In the method of manufacturing a multilayer PCB according to the present invention, the material substrate is not particularly limited as long as it can be used in this field, such as metal, ceramic, and resin.

【0012】なかでも、金属は熱安定性、熱放出性など
が向上するために、信頼性を高め得るとともに、製造コ
ストの節減効果も得ることができ、素材基板として好ま
しいが、金属は導電性も良好であるので、素材基板とし
て使用するには表面を樹脂層形成処理することが要求さ
れる。
Among them, metal is preferable as a material substrate because metal can improve reliability because heat stability, heat release property and the like are improved, and can also reduce production cost. Therefore, in order to use it as a material substrate, it is required to treat the surface with a resin layer.

【0013】また、素材基板をドリルリングまたはパン
チングして貫通孔を形成しても良い。この時、素材基板
が金属基板の場合には、貫通孔の形成後に基板表面はも
とより、貫通孔の内壁まで樹脂層形成処理すべきであ
る。
Further, a through hole may be formed by drilling or punching a material substrate. At this time, when the material substrate is a metal substrate, after the formation of the through hole, the resin layer should be formed not only on the substrate surface but also on the inner wall of the through hole.

【0014】次に、素材基板上に感光性絶縁物質を塗布
し、フォトマスクを利用して露光及び現像して貫通孔が
凹状に刻まれたパターン層を形成する。シルクスクリー
ン印刷法を応用し、陰刻の貫通孔を導電性インキで埋め
込むことにより配線パターンを形成する。
Next, a photosensitive insulating material is coated on the material substrate, and is exposed and developed using a photomask to form a pattern layer in which the through-holes are formed in a concave shape. A wiring pattern is formed by applying a silk screen printing method and embedding an intaglio through hole with conductive ink.

【0015】シルクスクリーン印刷法とは、フォトリソ
グラフィを利用してインキを塗布しようとする部分を陰
刻した上、前記凹部にインキを仕込み、スキージ(sq
ueezee)でインキを加圧しつつ押し出すことによ
りパターンを形成する方法を言う。この方法は、通常の
電気メッキまたは無電解メッキ法に比較して簡単にパタ
ーンを形成できる方法である。
In the silk screen printing method, a portion to be coated with ink is intaglio-printed using photolithography, and then ink is charged into the concave portion to form a squeegee (sq.
a method for forming a pattern by extruding the ink while applying pressure to the ink. This method is a method that can form a pattern more easily than a normal electroplating or electroless plating method.

【0016】このように感光性絶縁層の形成をはじめに
導電性インキをシルクスクリーンするまでの段階を数回
繰返すことにより、所望の層数だけ積層する。
By repeating the steps from forming the photosensitive insulating layer to silk-screening the conductive ink several times, a desired number of layers are laminated.

【0017】しかし、最上部の配線パターンまでシルク
スクリーン法により形成することはない。もしも最上層
の配線パターンを導電性インキを利用するシルクスクリ
ーン手法で形成するならば、導電性インキの粘性により
エッジ(edge)が直角に形成されず丸く形成される
ラウンド現象が生じてしまう。したがって、ワイヤーボ
ンディング時に十分な偏平度が確保できず、これにより
ファインピッチの配線を形成しにくくなるといった問題
点がある。
However, the uppermost wiring pattern is not formed by the silk screen method. If the uppermost wiring pattern is formed by a silk screen method using conductive ink, the viscosity of the conductive ink causes a round phenomenon in which edges are not formed at right angles but rounded. Therefore, there is a problem that a sufficient degree of flatness cannot be secured during wire bonding, which makes it difficult to form a fine-pitch wiring.

【0018】従って、最上部の配線パターンは無電解メ
ッキ法により形成する。すなわち、最上層部にメッキ触
媒剤を塗布し、無電解銅メッキを施すことにより配線パ
ターンを形成する。このように無電解メッキ法を施すと
偏平度を得ることができるから、ファインピッチの配線
パターンを形成するのが容易になる。
Therefore, the uppermost wiring pattern is formed by electroless plating. That is, a wiring pattern is formed by applying a plating catalyst to the uppermost layer and performing electroless copper plating. Since the flatness can be obtained by applying the electroless plating method in this manner, it is easy to form a fine-pitch wiring pattern.

【0019】しかし、無電解メッキは時間及びコストを
大いに必要とする工程であるため、最上部層のパターン
厚さが略1μmを超過する場合には、無電解メッキと電
気メッキとを順次施すことにより配線パターンを形成す
ることができる。つまり、略0.1−0.2μmまでは
無電解メッキを行ない、これにさらに電気メッキを施
し、所望の厚さを得た後に露光、現像し、そしてエッチ
ングすることにより配線パターンを形成する。
However, since the electroless plating is a process which requires much time and cost, if the pattern thickness of the uppermost layer exceeds about 1 μm, the electroless plating and the electroplating should be performed sequentially. Thus, a wiring pattern can be formed. In other words, electroless plating is performed up to about 0.1-0.2 μm, electroplating is further performed, and after obtaining a desired thickness, exposure, development, and etching are performed to form a wiring pattern.

【0020】本発明の方法によれば、扁平度が確保さ
れ、部品またはチップを積載し易く、ファインピッチの
配線パターンを形成できるという利点がある。また、信
頼性に優れ、製造工程面からも容易であり、しかも製造
コストも安い。
According to the method of the present invention, there is an advantage that flatness is ensured, components or chips are easily mounted, and a fine-pitch wiring pattern can be formed. In addition, it has excellent reliability, is easy in the manufacturing process, and has a low manufacturing cost.

【0021】以下、図1乃至図8に基づいて本発明をさ
らに詳細に説明する。
Hereinafter, the present invention will be described in more detail with reference to FIGS.

【0022】図1乃至図8は、本発明の一実施例にかか
る多層PCBの製造方法を段階別に示す断面図であり、
素材基板として金属基板を使用した場合である。
1 to 8 are cross-sectional views showing a method of manufacturing a multilayer PCB according to an embodiment of the present invention step by step.
This is a case where a metal substrate is used as a material substrate.

【0023】最初に、金属基板1上に樹脂層2を形成す
る樹脂層形成処理を施す(図1)。
First, a resin layer forming process for forming a resin layer 2 on a metal substrate 1 is performed (FIG. 1).

【0024】金属基板は熱安定性、熱放出性などに優れ
た高信頼性の基板であるが、導体であるから、表面を樹
脂層形成処理し、絶縁性を与えなければならない。樹脂
層形成処理前に金属基板をドリルリングまたはパンチン
グして、貫通孔を形成することがあるが、この場合に
は、金属基板の表面はもとより、貫通孔の内壁まで樹脂
層形成処理すべきである。
The metal substrate is a highly reliable substrate having excellent heat stability and heat release properties. However, since it is a conductor, its surface must be treated with a resin layer to provide insulation. The through hole may be formed by drilling or punching the metal substrate before the resin layer forming process.In this case, the resin layer forming process should be performed not only on the surface of the metal substrate but also on the inner wall of the through hole. is there.

【0025】次に、前記樹脂層形成処理された金属基板
1上に感光性絶縁層3を形成した後に(図2)、前記感
光性絶縁層3上にフォトマスクを載置し、露光及び現像
を行うことにより貫通孔4が凹状に刻まれたパターン層
を形成する(図3)。
Next, after forming the photosensitive insulating layer 3 on the metal substrate 1 on which the resin layer forming process has been performed (FIG. 2), a photomask is placed on the photosensitive insulating layer 3 and exposed and developed. Is performed to form a pattern layer in which the through holes 4 are cut in a concave shape (FIG. 3).

【0026】続いて、前記パターン層に導電性インキを
仕込み、シルクスクリーンした後に硬化させて、配線パ
ターン5を形成する(図4)。
Subsequently, a conductive ink is charged in the pattern layer, and the screen layer is cured after being silk-screened to form a wiring pattern 5 (FIG. 4).

【0027】上記感光性絶縁層の形成段階より配線パタ
ーン形成段階までの一連の工程を繰返し、所望の層数だ
け積層する(図5及び図6)。
A series of steps from the step of forming the photosensitive insulating layer to the step of forming the wiring pattern are repeated, and a desired number of layers are laminated (FIGS. 5 and 6).

【0028】次に、最上層の配線パターンを形成するた
めに、前記結果物上にメッキ触媒剤を塗布する(図
7)。
Next, in order to form the uppermost wiring pattern, a plating catalyst is applied on the resultant product (FIG. 7).

【0029】次に、メッキ触媒剤が塗布された結果物を
無電解メッキして、最上層の配線パターン6を形成する
(図8)。
Next, the resulting product coated with the plating catalyst is subjected to electroless plating to form the uppermost wiring pattern 6 (FIG. 8).

【0030】しかし、無電解メッキは時間及び費用が相
当量かかる工程であるため、前記最上部層の配線パター
ン6を所定の厚さ、例えば1μmより厚く形成すべき場
合には略0.1−0.2μm以下まで無電解メッキを行
なった後に、電気メッキすることで所望の厚さの配線パ
ターンを得る。これにより製造時間及び製造コストを節
減することができる。
However, since the electroless plating is a process that requires a considerable amount of time and cost, when the wiring pattern 6 of the uppermost layer is to be formed to a predetermined thickness, for example, 1 μm or more, it is approximately 0.1-m. After performing electroless plating to 0.2 μm or less, electroplating is performed to obtain a wiring pattern having a desired thickness. As a result, manufacturing time and manufacturing cost can be reduced.

【0031】[0031]

【発明の効果】本発明による製造方法は製造工程が容易
で、製造コストが安価であり、この方法により得られた
多層PCBは部品やチップが搭載される最上層部の偏平
度に優れるとともに、ファインピッチの配線パターンを
形成できるという利点がある。
According to the manufacturing method of the present invention, the manufacturing process is easy and the manufacturing cost is low. The multilayer PCB obtained by this method has excellent flatness of the uppermost layer on which components and chips are mounted, and There is an advantage that a fine pitch wiring pattern can be formed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例にかかる多層プリント配線板
の製造工程の手順を示す断面図である。
FIG. 1 is a sectional view showing a procedure of a manufacturing process of a multilayer printed wiring board according to one embodiment of the present invention.

【図2】本発明の一実施例にかかる多層プリント配線板
の製造工程の手順を示す断面図である。
FIG. 2 is a sectional view showing a procedure of a manufacturing process of the multilayer printed wiring board according to one embodiment of the present invention.

【図3】本発明の一実施例にかかる多層プリント配線板
の製造工程の手順を示す断面図である。
FIG. 3 is a sectional view showing a procedure of a manufacturing process of the multilayer printed wiring board according to one embodiment of the present invention.

【図4】本発明の一実施例にかかる多層プリント配線板
の製造工程の手順を示す断面図である。
FIG. 4 is a sectional view showing a procedure of a manufacturing process of the multilayer printed wiring board according to one embodiment of the present invention.

【図5】本発明の一実施例にかかる多層プリント配線板
の製造工程の手順を示す断面図である。
FIG. 5 is a sectional view showing a procedure of a manufacturing process of the multilayer printed wiring board according to one embodiment of the present invention.

【図6】本発明の一実施例にかかる多層プリント配線板
の製造工程の手順を示す断面図である。
FIG. 6 is a sectional view showing a procedure of a manufacturing process of the multilayer printed wiring board according to one embodiment of the present invention.

【図7】本発明の一実施例にかかる多層プリント配線板
の製造工程の手順を示す断面図である。
FIG. 7 is a sectional view showing a procedure of a manufacturing process of the multilayer printed wiring board according to one embodiment of the present invention.

【図8】本発明の一実施例にかかる多層プリント配線板
の製造工程の手順を示す断面図である。
FIG. 8 is a sectional view showing a procedure of a manufacturing process of the multilayer printed wiring board according to one embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 金属基板 2 樹脂層 3 感光性絶縁層 4 貫通孔 5 配線パターン 6 最上層の配線パターン DESCRIPTION OF SYMBOLS 1 Metal substrate 2 Resin layer 3 Photosensitive insulating layer 4 Through-hole 5 Wiring pattern 6 Uppermost wiring pattern

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 a)素材基板上に感光性絶縁層を形成
する段階と、 b)前記感光性絶縁層を露光及び現像し、貫通孔が陰刻
されたパターン層を形成する段階と、 c)前記パターン層に導電性インキを塗布し、シルクス
クリーンを行なった後に硬化させる段階と、 d)前記段階a)−c)を繰返し、所望の層数だけ積層
する段階と、 e)前記段階d)の結果物の上部にメッキ触媒剤を塗布
する段階と、 f)前記段階e)の結果物を無電解メッキし、最上層の
配線パターンを形成する段階とを含むことを特徴とする
多層プリント配線板の製造方法。
1. a) forming a photosensitive insulating layer on a material substrate; b) exposing and developing the photosensitive insulating layer to form a pattern layer in which a through hole is engraved; c). Applying a conductive ink to the pattern layer, curing after applying a silk screen, d) repeating the steps a) to c), and laminating a desired number of layers; e) the step d) Applying a plating catalyst to the upper portion of the resulting product; and f) electroless plating the resulting product of step e) to form an uppermost wiring pattern. Plate manufacturing method.
【請求項2】 前記素材基板が、金属基板、樹脂基板
またはセラミック基板の素材基板であることを特徴とす
る請求項1に記載の多層プリント配線板の製造方法。
2. The method according to claim 1, wherein the material substrate is a metal substrate, a resin substrate, or a ceramic substrate.
【請求項3】 前記素材基板が金属基板の場合に、前
記段階a)前に前記素材基板の表面に樹脂層を形成する
樹脂層形成処理を行う段階を更に含むことを特徴とする
請求項2に記載の多層プリント配線板の製造方法。
3. The method according to claim 2, further comprising performing a resin layer forming process for forming a resin layer on the surface of the material substrate before the step a) when the material substrate is a metal substrate. 3. The method for producing a multilayer printed wiring board according to item 1.
【請求項4】 前記段階a)前に、前記素材基板をパ
ンチングまたはドリルリングし、貫通孔を形成する段階
を更に含むことを特徴とする請求項1に記載の多層プリ
ント配線板の製造方法。
4. The method of claim 1, further comprising, before the step a), punching or drilling the material substrate to form a through hole.
【請求項5】 前記素材基板が金属基板の場合、貫通
孔の形成段階後に前記素材基板の表面及び貫通孔の内面
を樹脂層形成処理する段階を更に含むことを特徴とする
請求項3または4に記載の多層プリント配線板の製造方
法。
5. The method according to claim 3, further comprising the step of forming a resin layer on a surface of the material substrate and an inner surface of the through hole after the step of forming the through hole when the material substrate is a metal substrate. 3. The method for producing a multilayer printed wiring board according to item 1.
【請求項6】 前記段階fにおいて、最上層の配線パ
ターンの厚さが1μm以下であることを特徴とする請求
項1に記載の多層プリント配線板の製造方法。
6. The method according to claim 1, wherein in the step (f), the thickness of the uppermost wiring pattern is 1 μm or less.
【請求項7】 前記段階fにおいて最上層の配線パタ
ーンの厚さが1μmを超える場合、前記最上層の配線パ
ターンが0.1μm−0.2μmの厚さで形成されるま
では無電解メッキを行う一方、これを超える厚さの配線
パターンは電気メッキにより形成することを特徴とする
請求項1に記載の多層プリント配線板の製造方法。
7. If the thickness of the uppermost wiring pattern exceeds 1 μm in step f, electroless plating is performed until the uppermost wiring pattern has a thickness of 0.1 μm-0.2 μm. 2. The method according to claim 1, wherein the wiring pattern having a thickness exceeding this is formed by electroplating.
【請求項8】 第1ないし第7に記載の製造方法に従
い製造された多層プリント配線板。
8. A multilayer printed wiring board manufactured according to any one of the first to seventh manufacturing methods.
JP10138327A 1997-05-23 1998-05-20 Multilayered wiring board and its manufacture Pending JPH10335831A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019970020403A KR19980084566A (en) 1997-05-23 1997-05-23 Multilayer printed circuit board and its manufacturing method
KR1997-20403 1997-05-23

Publications (1)

Publication Number Publication Date
JPH10335831A true JPH10335831A (en) 1998-12-18

Family

ID=19506946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10138327A Pending JPH10335831A (en) 1997-05-23 1998-05-20 Multilayered wiring board and its manufacture

Country Status (3)

Country Link
JP (1) JPH10335831A (en)
KR (1) KR19980084566A (en)
CN (1) CN1201367A (en)

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JP2012102365A (en) * 2010-11-10 2012-05-31 Koichi Kugimiya Method for forming functional pattern, and functional device
JP2012102366A (en) * 2010-11-10 2012-05-31 Koichi Kugimiya Method for forming functional pattern, and functional element
CN106937488A (en) * 2017-05-03 2017-07-07 奥士康精密电路(惠州)有限公司 A kind of anti-welding copper-clad plate printing process of electrolyte resistance
CN106982517A (en) * 2017-05-26 2017-07-25 东莞翔国光电科技有限公司 A kind of method that use thermosetting ink prints PCB welding resisting layers

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JP3825746B2 (en) * 2000-06-30 2006-09-27 イー・アイ・デュポン・ドウ・ヌムール・アンド・カンパニー Thick film circuit patterning method
KR100396866B1 (en) * 2001-02-26 2003-09-03 산양전기주식회사 manufacturing method of flexible printed circuit board used photosensitivity insulating material
TW200405786A (en) * 2002-08-06 2004-04-01 Taiyo Ink Mfg Co Ltd Manufacturing method of multi-layer printed circuit board and multi-layer printed circuit board
KR100797716B1 (en) * 2006-03-21 2008-01-23 삼성전기주식회사 Light Emitting Diodes-Backlight Unit without printed circuit boards and Manufacturing method thereof
CN101959374B (en) * 2009-07-15 2013-03-20 三星电子株式会社 Method for manufacturing multilayer printed circuit board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012102365A (en) * 2010-11-10 2012-05-31 Koichi Kugimiya Method for forming functional pattern, and functional device
JP2012102366A (en) * 2010-11-10 2012-05-31 Koichi Kugimiya Method for forming functional pattern, and functional element
CN106937488A (en) * 2017-05-03 2017-07-07 奥士康精密电路(惠州)有限公司 A kind of anti-welding copper-clad plate printing process of electrolyte resistance
CN106982517A (en) * 2017-05-26 2017-07-25 东莞翔国光电科技有限公司 A kind of method that use thermosetting ink prints PCB welding resisting layers

Also Published As

Publication number Publication date
KR19980084566A (en) 1998-12-05
CN1201367A (en) 1998-12-09

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