KR19980073899A - Vijay A semiconductor package and its manufacturing method - Google Patents

Abstract

Disclosed are a semiconductor package and a method of manufacturing the same. According to the present invention, a BG semiconductor package includes a metal substrate on which a semiconductor chip is mounted, and a lead connected to the chip by wire bonding. The lead includes a plurality of conductive inks formed in a spherical shape to be in contact with the bottom surface thereof. It is characterized by including. In addition, the manufacturing method relates to a manufacturing method of a BGA semiconductor package including a substrate on which a semiconductor chip is mounted, and a lead connected to the chip by wire bonding, and a metal by etching and stamping. 1 step of making a lead frame of the material, 2 steps of attaching insulating tape to the lead, 3 steps of applying a plurality of conductive ink to the lower surface of the lead to be electrically conductive with the lead, and the terminal and the lead of the semiconductor chip 4 steps of wire-bonding, 5 steps of molding the leads and the wire-bonded chip with a resin, and 6 steps of cutting the leads and dam bars protruding out of the molding layer. By employing the present invention, there are effects such as cost reduction, reduction in the number of manufacturing steps, effective heat dissipation, and improved strength.

Description

Ball grid array (BGA) semiconductor package and manufacturing method thereof

The present invention relates to a ball grid array (BGA) semiconductor package and a method of manufacturing the same.

In general, a semiconductor package is formed by supporting an integrated circuit chip, which is a memory device, by a lead frame and assembling with other components. In this case, a lead that leads the lead frame to connect the inside and the outside of the semiconductor package. act as a lead.

1 is a schematic cross-sectional view showing a general semiconductor package. As shown in the figure, a semiconductor chip 12, which is a storage element, is mounted on a heat sink 11 (or pad) on a square substrate, and a lead (around the periphery of the heat sink 11, ie, around the semiconductor chip 12) is mounted. 14 is attached, for example, by an adhesive 13 such as a double-sided insulating tape. In addition, the semiconductor chip 12 and the inner lead 14 are bonded by the wire 15, and upper and lower portions thereof are sealed by the molding material 17, and an outer lead (eg, an outer lead) is formed at an end of the inner rib 14. 16) is connected, and a part of it forms the structure which protrudes out of the said molding material.

However, such semiconductor packages are classified into chip on board packages, lead on chip packages, and BGA packages according to their structure or function. In particular, the BG semiconductor package is formed in the lead (solder ball) to form a solder ball (solder ball) in contact with the connecting terminal of the external substrate is configured to be electrically conductive.

The lead frame employed in the conventional Vishay IC package is made using Mitsubishi Gas Chemical's BT resin. The lead frame is made like a thin board made by using a printed circuit board etching method, and the input / output terminal connection in the lead frame is connected to the upper and lower sides by processing a through hole inside the lead frame substrate.

Recently, Fujitsu developed leadframe-type fine-pitch Vishay IC package as lead frame type package, but this method uses half etching of upper and lower parts of lead frame to manufacture terminals. do. In addition, the proposed lead frame type BGA semiconductor package is characterized by fabricating input and output terminals by applying the stamping (stamping) and anti-etching techniques.

However, the conventional semiconductor package described above has a problem in that the price competition rate is low because the substrate uses expensive BT resin, the number of manufacturing processes is high, and the polymer resin is poor in electrical stability and thermal stability. In particular, in the case of a commercially available peelable substrate, the chip is broken into thin pieces by heat generated from the chip and the peripheral device, and cracks easily occur and deformation easily occurs.

In addition, in the case of a lead frame type using a metal, when fabricating a fine pitch, by applying an input-output etching and semi-etching leaving only a minute part, deformation is easy due to stress after etching, and there is a difficulty in processing. If a thick material is used, it is difficult to produce fine pitches, and over-etching often results in lack of dimensional stability.

In addition, when using a coining (coining) manufacturing method it is necessary to double stamping, the deformation of the lead is easy and the technical difficulty is increased, there is a difficulty in processing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a Vishay IC package and a method of manufacturing the same, which improve electrical / thermal stability, have a low strain rate, are easy to process, and have dimensional stability.

1 is a cross-sectional view schematically illustrating a general semiconductor package.

2 is a plan view schematically showing a lead frame employed in a BG semiconductor package according to the present invention.

3 is a plan view schematically illustrating an 'A' portion of FIG. 2 in a lead frame of a semiconductor package according to the present invention.

4 is a cross-sectional view schematically showing an 'B' portion of FIG.

5 is a schematic cross-sectional view of a lead frame after a hardening operation.

6 is a schematic cross-sectional view of a lead frame to which a chip is attached.

7 is a schematic cross-sectional view of a wire bonded leadframe.

8 is a schematic cross-sectional view of a molded semiconductor package.

9 is a cross-sectional view schematically illustrating a semiconductor package in which leads and dam bars are cut.

10 is a schematic cross-sectional view of a semiconductor package employing solder balls.

FIG. 11 is a view schematically illustrating an arrangement of the solder balls illustrated in FIG. 10.

FIG. 12 is a diagram showing a process of uniformizing a nonuniform cross section after molding.

Explanation of symbols for the main parts of the drawings

11 ... heat sink 12, 30 ... semiconductor chip

13.Glue 14 ... Inner Lead

15 ... wire 16 ... external lead

17 Molding material 20 Lead frame

21.Diap 24.Insulating tape

25 ... conductive ink 26 ... adhesive tape

27.Gold wire 28.Solder ball

22, 23 ... lead

In order to achieve the above object, the present invention relates to a BG package including a metal substrate on which a semiconductor chip is mounted, and a lead connected to the chip by wire bonding, wherein the lead is formed in a spherical shape to be in contact with the bottom surface thereof. It characterized in that it contains a conductive ink.

The material of the substrate is made of any one of copper, copper alloy, and nickel-iron alloy, and the lead is further provided with a solder ball attached to a conductive ink and coupled to a terminal of an external substrate.

The conductive inks are then made by cold finishing finishing using a die and punch in cold to maintain mutual flatness.

In another aspect, the present invention is a manufacturing method of a BG semiconductor package comprising a substrate on which a semiconductor chip is mounted, and a lead connected to the chip by wire bonding, wherein the metal material is formed by etching and stamping. 1 step of making a lead frame of the step, 2 steps of attaching insulating tape to the lead, 3 steps of applying a plurality of conductive ink to the lower surface of the inner lead to be electrically conductive with the lead, and the terminal and the lead of the semiconductor chip 4 steps of wire-bonding, 5 steps of molding the leads and the wire-bonded chip with a resin, and 6 steps of cutting the leads and dam bars protruding out of the molding layer.

Preferably, the metal substrate is made of one of copper, a copper alloy and a nickel-iron alloy, and the third step is a finishing processing step in which the conductive inks are cold-pressed by using a die and a punch in cold to maintain mutual flatness. It includes.

The three steps include applying the conductive ink to any one of a screen printing method, a method using a metal mask, a spraying and dispensing method, and a point dropping method, and maintaining flatness of the applied conductive ink by grinding and cutting. It includes.

Hereinafter, exemplary embodiments of a BG semiconductor package and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 2 is a plan view schematically illustrating an 'A' portion of FIG. 1 in a lead frame of a semiconductor package according to the present invention. 3 is a cross-sectional view schematically showing an 'B' portion of FIG. 4 is a schematic cross-sectional view of a lead frame after a hardening operation. 5 is a schematic cross-sectional view of a lead frame to which a chip is attached. 6 is a schematic cross-sectional view of a wire bonded lead frame. 7 is a schematic cross-sectional view of a molded semiconductor package. 8 is a cross-sectional view schematically illustrating a semiconductor package in which leads and dam bars are cut. 9 is a schematic cross-sectional view of a semiconductor package employing a solder ball. FIG. 10 is a view schematically illustrating an arrangement of the solder balls illustrated in FIG. 9. FIG. 11 is a view showing a process for making non-uniform cross section after molding. FIG.

The semiconductor package according to the present invention includes a substrate on which a semiconductor chip is mounted, a lead and a molding part connected to the chip by wire bonding as in the prior art. In this case, the substrate 21 and the leads 22 and 23 are integrally formed as a lead frame 20 and are illustrated in FIG. 2. The lead frame 20 is made using an etching method in a chemical method, or is made of a stamping process, a mechanical method, the lead frame 20 is expensive expensive BT that is generally used polymer resin Use cheap metal instead of resin. Although there are various metals, it is preferable to use copper, a copper alloy, and a nickel-iron alloy.

When the die pad 21 and the leads 22 and 23 of the lead frame 20 are made, as shown in FIG. 3, the insulating tape 24 is adhered to the upper surfaces of the leads 22. The insulating tape 24 is bonded for the purpose of improving the strength of the leads 22 and maintaining the spacing between the leads, and also insulates the leads 22. Although the lead 22 (FIG. 2) and the lead 23 (FIG. 2) generally have two types, separate and integral, the present invention will be described with the integral. In general, the lead and the lead are integrally referred to as an internal lead, and a portion coupled with a terminal of an external device is referred to as an external lead. One conductive ink 25 is applied to each lead so as to be electrically connected to the lead 22 on the surface to which the insulating tape 24 on the upper surface of the leads 22 and 23 is attached. The conductive ink may have a variety of materials, but is preferably any one of copper, silver, gold, palladium, rhodium, and alloys of the above materials.

In FIG. 3, an enlarged view of the 'B' portion of the conductive ink 25 is shown in FIG. 4. The cross section of the lid 22 is quadrangular, and the conductive ink 25 on the upper surface is spherical. The conductive ink 25 is applied to the upper surface of the lid by four methods. The methods include silk screen printing, coating using a metal mask, coating using injection and dispensing, and coating by dotting. . The conductive ink 25 coated in at least one of the four methods is subjected to a cold finishing process using a die and a punch in cold to maintain mutual flatness. The lead frame subjected to this finishing process is shown in FIG. 5. In particular, the height of the conductive ink 25 is preferably the same as the height of the insulating tape 24. The finishing process is performed after the pretreatment and the posttreatment before and after the process, and the conductive ink 24 having the process finished has a substantially rectangular cross section.

When the finishing process is finished such that the conductive ink 25 and the insulating tape 24 maintain the flatness, the adhesive tape 26 is mounted on the upper surface of the die pad 21, and the semiconductor chip is disposed on the upper surface of the adhesive tape 26. 30 is seated.

When the semiconductor chip 30 is placed on the upper surface of the die pad 21, as shown in FIG. 7, a wire bonding process for connecting the terminals and the leads 22 of the semiconductor chip 30 with gold wires is performed. Going through. As a result, the semiconductor chip and the lead are electrically connected to each other to exchange electrical signals with external devices to be connected to the other end.

When the lead 22 of the lead frame and the semiconductor chip 30 are wire-bonded to be electrically conductive, as shown in FIG. 8, the lead 22 and the semiconductor chip 30 are molded over the entire lead frame with a molding resin. When the molding process is completed, the lead frame is locked into the molding resin, and only the lead 23 protrudes out of the molding resin.

In the semiconductor package after the molding process, the lead 23 of the lead frame protruding out of the molding resin is cut out, and the dam bar connecting the leads is also cut out to have a cross section as shown in FIG. 9.

A semiconductor package in which a lead 23 to be connected to a connection terminal of an external device is cut, adheres a solder ball 28 to an upper surface of the conductive ink 25 as shown in FIG. 10. The solder ball 28 is electrically conducting through the semiconductor chip 30, wire-bonded leads, and conductive ink, so that the solder ball 28 is connected to a connection terminal of an external device, and serves as a transmitter for transmitting and receiving an electrical signal.

In addition, the conductive ink 25 placed on the upper surface of the lead 22 and the solder ball 28 placed on the upper surface of the conductive ink 25 are alternately formed for each lead so that the semiconductor package has a surface structure as shown in FIG. Will have Interleaved solder balls are easier to mount than conventional ones because they have space to spare.

On the other hand, the solder ball 28 should be placed in the semiconductor package in contact with the conductive ink 25. As shown in FIG. 12A, when the conductive ink 25 is not uniform and the conductive ink 25 does not come out of the molding resin layer, even when the solder ball 28 is in contact with the upper surface of the molding resin layer, there is no electrical conduction. This is often the case when cutting leads and dam bars after molding. Therefore, after molding, in order to expose the conductive ink out of the molding resin layer, the molding resin layer should be uniformly processed through a grinding process and a cutting process. The semiconductor package after the grinding and cutting processes is shown in FIG. 12B. As a result, the height between the conductive inks 25 becomes uniform, and the insulating tape 24 also maintains a uniform height.

The semiconductor package made by the above-described characteristic manufacturing method and having a characteristic configuration operates as follows.

A semiconductor chip is placed on an upper surface of the die pad of the lead frame, and the semiconductor chip is wire-bonded to electrically conduct with the leads of the lead frame. The conductive ink is coated on the upper surfaces of the leads, and solder balls are placed on the upper surfaces of the conductive ink, and are coupled to the connection terminals of the external device. Therefore, the electrical signal of the external device passes through the conductive ink through the solder ball and is transmitted to the semiconductor chip along the lead, and the electrical signal from the semiconductor chip is transmitted to the connection terminal of the external device. At this time, while the process is repeated, heat is generated by the semiconductor chip and the external device, causing bending and cracking of the semiconductor package. However, in the present invention, since the lead frame substrate is made of metal, the heat dissipation effect is excellent and the heat is effectively released. . In addition, it is easy to fine pitch processing by etching or stamping using the existing material as it is when manufacturing the lead frame. In addition, since the conductive ink is applied to the lead instead of pressing the lead several times, the dimensional stability is maintained and the improved strength is achieved.

The BG semiconductor package according to the present invention has the following effects.

First, raw material costs are reduced.

In the present invention, a low cost BIA lead frame can be manufactured by using an inexpensive metal such as copper, a copper alloy, and a nickel-iron alloy instead of an expensive BT resin, which is a polymer resin generally used.

Second, heat dissipation efficiency is improved.

Conventional peelable leadframes are bent or cracked by heat generated from chips and peripherals, and cracks are generated, but the leadframes employed in the BG semiconductor package according to the present invention are deformed by replacing them with metal materials. It has the advantage of effectively dissipating this source of heat.

Third, the deformation of the lead is small.

Since the lead frame employed in the BG semiconductor package according to the present invention is made of a metal, it is possible to effectively release heat generated from the chip and the peripheral device. In addition, since the input and output terminals connected to the external device are made of conductive ink, deformation caused by bending, vibration, impact, etc. when connecting to the external device can be prevented.

Fourth, strength is improved.

Conventional lead frames are difficult to fine pitch because they are etched using a thick material at the time of fabrication by etching, but in the present invention, etching or stamping is performed using the existing materials as they are without applying semi-etching during lead frame fabrication. Since the fine pitch processing is easy and the strength is improved compared to the conventional.

Fifth, the implementation is easy.

In the BG semiconductor package according to the present invention, the lead, which is an input / output terminal, is replaced with conductive ink and solder balls so that the pitch can be easily increased.

The manufacturing method of the BG semiconductor package according to the present invention has the following effects.

First, manufacturing costs are reduced.

In the present invention, inexpensive metal is used instead of expensive BT resin, which is a polymer resin that is generally used. In addition, the conventional lead frame is made of a peelable substrate, so the manufacturing process is high, and the manufacturing cost is high, such as yield reduction, lamination thickness control, and solder mask cracking. It is easy to control the thickness and does not require a peeling process, a photosolder coating and a drill process, thereby improving yield and reducing leadframe manufacturing costs.

Second, fine pitch production is possible.

Although it is difficult to produce fine pitch because the semi-etched lead frame of the BG semiconductor package is manufactured by etching, in the present invention, the etching is performed by using the existing material as it is without applying the anti-etching during the lead frame fabrication. Or stamping has the advantage of easy fine pitch processing.

Third, there is dimensional stability when solder ball bonding.

The present invention has an advantage of having a dimensional stability because the conductive ink is applied to the lead of the lead frame to make the input and output terminals to connect the solder ball by maintaining the flatness through the stamping process.

Fourth, after molding, no post-treatment is necessary.

In the method for manufacturing a BG semiconductor package according to the present invention, after the lead frame is completed, the conductive ink maintains the smoothness during the resin molding, so that the post-treatment (processing to give flatness) must be performed only after uneven protrusion of the conductive ink after molding. There is an advantage that does not need to be performed.

Although the present invention has been described in terms of the embodiments shown in the drawings, this is merely exemplary, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the appended claims.

Claims (20)

In a BGA semiconductor package including a metal substrate on which a semiconductor chip is mounted, and a lead connected to the chip by wire bonding, And the lead includes a plurality of conductive inks formed in a spherical shape to be in contact with the bottom surface thereof. The method of claim 1, The material of the substrate is a BG semiconductor package, characterized in that made of any one of copper, copper alloy and nickel-iron alloy. The method of claim 1, The conductive ink is a Biei semiconductor package, characterized in that formed by finishing the cold pressing by using a die and punch in cold to maintain mutual flatness. The method of claim 1, And the lead is attached to the conductive ink and further comprises a solder ball (solder ball) coupled to the terminal of the external substrate. The method of claim 1, The material of the conductive ink is a BG semiconductor package, characterized in that any one selected from copper, silver, gold, palladium and rhodium. The method of claim 1, The conductive ink is made of copper, silver, gold, palladium and rhodium alloy of any one of the alloy package, characterized in that the alloy. The method of claim 4, wherein The solder ball is a semiconductor package, characterized in that the contact position crosses each other so as not to contact the solder ball corresponding to the adjacent lead. The method of claim 1, The semiconductor package of claim 2, further comprising an insulating tape to maintain a gap between the leads. In the manufacturing method of a BGA semiconductor package comprising a substrate on which a semiconductor chip is mounted, and a lead connected to the chip by wire bonding, A first step of making a lead frame made of metal by etching and stamping; Attaching an insulating tape to the lead; 3 to apply a plurality of conductive ink to the lower surface of the lead to be electrically conductive with the lead, 4 steps of wire-bonding the terminal and the lead of the semiconductor chip; 5 steps of molding the leads and the wire-bonded chip with a resin, And cutting the leads and the dam bars protruding out of the molding layer. The method of claim 9, And the metal substrate is made of one of copper, a copper alloy, and a nickel-iron alloy. The method of claim 9, Said step 3 is a method of manufacturing a semiconductor package, characterized in that the conductive ink further comprises a finishing processing step of cold pressing by using a die and a punch in cold to maintain mutual flatness. The method of claim 9, And the step 5 further comprises coupling a solder ball coupled to the terminal of an external substrate to the conductive ink. The method of claim 11, The finishing process is performed after the pretreatment and post-treatment before and after the process. The method of claim 9, Said step 3 is a method of manufacturing a semiconductor package, characterized in that it comprises the step of applying a conductive ink using a screen printing method. The method of claim 9, Said step 3 is a method of manufacturing a semiconductor package, characterized in that comprising the step of applying a conductive ink using a metal mask. The method of claim 9, Wherein the step 3 is a method of manufacturing a semiconductor package, characterized in that comprising the step of applying a conductive ink using the injection (dispensing) method. The method of claim 9, Said step 3 is a method of manufacturing a semiconductor package, characterized in that comprising the step of applying a conductive ink by the dotting method (dotting). The method of claim 9, Said step 3 is a method for manufacturing a BG semiconductor package comprising the step of maintaining the flatness of the coated conductive ink in the grinding and cutting process. The method of claim 18, The grinding and cutting process is a Biei semiconductor package manufacturing method comprising the degree of maintaining the flatness of the conductive ink and the insulating tape attached to the lead. The method of claim 9, Said step 3 is a method of manufacturing a semiconductor package, characterized in that to apply the conductive ink cross.