JPH10270597A - Bga semiconductor package and its manufacture - Google Patents
Bga semiconductor package and its manufactureInfo
- Publication number
- JPH10270597A JPH10270597A JP10069676A JP6967698A JPH10270597A JP H10270597 A JPH10270597 A JP H10270597A JP 10069676 A JP10069676 A JP 10069676A JP 6967698 A JP6967698 A JP 6967698A JP H10270597 A JPH10270597 A JP H10270597A
- Authority
- JP
- Japan
- Prior art keywords
- conductive ink
- semiconductor package
- leads
- applying
- bga semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＢＧＡ（Ball Gri
d Array）半導体パッケージ及びその製造方法に関す
る。TECHNICAL FIELD The present invention relates to a BGA (Ball Gri
d Array) semiconductor package and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】半導体チップは、半導体パッケージ内の
リードフレームにより支持され、且つ、前記リードフレ
ームのリードは、前記半導体チップと外部回路とを電気
的に接続する。特に、ＢＧＡ半導体パッケージでは、半
導体チップがリード（lead）に付着されたはんだボール
（solder ball）を介して外部回路と接続される。2. Description of the Related Art A semiconductor chip is supported by a lead frame in a semiconductor package, and leads of the lead frame electrically connect the semiconductor chip to an external circuit. In particular, in a BGA semiconductor package, a semiconductor chip is connected to an external circuit via a solder ball attached to a lead.
【０００３】一方、従来のＢＧＡ半導体パッケージで採
用されているリードフレームは、例えば三菱ガスケミカ
ル社のＢＴ樹脂を使って製造されたものである。このリ
ードフレームは、プリント基板をエッチングする方法に
より作製されると共に、リードフレーム基板の内部の通
孔を介して上部及び下部が電気的に接続される。On the other hand, a lead frame employed in a conventional BGA semiconductor package is manufactured using, for example, BT resin manufactured by Mitsubishi Gas Chemical Company. The lead frame is manufactured by a method of etching a printed board, and the upper and lower parts are electrically connected to each other through a through hole in the lead frame board.
【０００４】しかしながら、従来の半導体パッケージ用
のリードフレーム基板は、高分子樹脂のＢＴ樹脂を使用
するために高価で、工程数が多くなり、しかも電気的及
び熱的な安定性が劣っている。特に、通常使用される剥
離型の基板は、チップ及び周辺機器より生じる熱によっ
て薄いパッチに裂けることがあり、これに加えて、クラ
ックの発生により変形し易くなる。However, the conventional lead frame substrate for a semiconductor package is expensive due to the use of a polymer resin BT resin, requires many steps, and has poor electrical and thermal stability. In particular, a commonly used peeling type substrate may be split into thin patches due to heat generated from the chips and peripheral devices, and in addition, it is easily deformed due to cracks.
【０００５】一方、金属リードフレームは、微細ピッチ
の製作時に所定の部分だけ残しハーフエッチングする方
法を用いて製造される。しかしながら、ハーフエッチン
グ法は、素材が厚い場合は、微細ピッチの製作が難し
く、過剰なエッチングのために寸法の誤差が多くなり、
更に、エッチング後の応力により変形し易く、加工が困
難であるという問題がある。On the other hand, a metal lead frame is manufactured by using a method of half-etching while leaving a predetermined portion when manufacturing a fine pitch. However, in the case of the half etching method, when the material is thick, it is difficult to produce a fine pitch, and the dimensional error increases due to excessive etching,
In addition, there is a problem that it is easily deformed by stress after etching, and processing is difficult.
【０００６】[0006]
【発明が解決しようとする課題】本発明は、以上の問題
点に鑑みて成されたものであり、電気的／熱的安定性が
高く、変形しにくく、加工が容易で、寸法の誤差の少な
いＢＧＡ半導体パッケージとその製造方法を提供するこ
とをその目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has high electrical / thermal stability, is hardly deformed, is easy to process, and has a small dimensional error. An object of the present invention is to provide a small number of BGA semiconductor packages and a method of manufacturing the same.
【０００７】[0007]
【課題を解決するための手段】前記目的を達成するた
め、本発明により、半導体チップとワイヤーボンディン
グにより接続されたリードを有するＢＧＡ半導体パッケ
ージにおいて、前記各リードに設けられる導電性インキ
と、前記導電性インキに付着され、外部基板の端子と接
続されるはんだボールとを有することを特徴とするＢＧ
Ａ半導体パッケージが提供される。In order to achieve the above object, according to the present invention, in a BGA semiconductor package having leads connected to a semiconductor chip by wire bonding, a conductive ink provided on each of the leads; BG having solder balls attached to a conductive ink and connected to terminals of an external substrate
An A semiconductor package is provided.
【０００８】また、本発明により、各リード上に導電性
インキを塗布する過程と、半導体チップの端子とリード
とをワイヤボンディングにより接続し、これらを樹脂で
モールディングする過程と、導電性インキに、外部基板
の端子と接続されるはんだボールを接続させる過程とを
含むことを特徴とするＢＧＡ半導体パッケージの製造方
法が提供される。Further, according to the present invention, a step of applying conductive ink on each lead, a step of connecting terminals of a semiconductor chip and leads by wire bonding and molding these with a resin, Connecting a solder ball to be connected to a terminal of an external substrate.
【０００９】[0009]
【発明の実施の形態】本発明に係るＢＧＡ半導体パッケ
ージに採用されるリードフレーム２０は、図１に示すよ
うに、半導体チップを搭載するパッド２１と、前記半導
体チップの端子と接続され、外部機器の端子と接続され
るリード２２とから構成される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, a lead frame 20 employed in a BGA semiconductor package according to the present invention is connected to pads 21 for mounting a semiconductor chip and terminals of the semiconductor chip. And a lead 22 connected to the terminal.
【００１０】かかるリードフレーム２０は、化学的方法
であるエッチング法を利用するか、あるいは機械的方法
であるスタンピング加工により形成される。リードフレ
ーム２０の材料としては、銅、銅合金及びニッケル−鉄
の合金などの金属を使用する。The lead frame 20 is formed by using a chemical etching method or a mechanical stamping process. As a material of the lead frame 20, a metal such as copper, a copper alloy, and a nickel-iron alloy is used.
【００１１】図２は、図１のＡ部分を拡大して示した図
面である。FIG. 2 is an enlarged view of a portion A in FIG.
【００１２】リードフレーム２０のリード２２の上面に
は、リード２２の強度向上及びリード間の間隔維持を図
るべく、絶縁テープ２４が接着されている。An insulating tape 24 is adhered to the upper surface of the lead 22 of the lead frame 20 in order to improve the strength of the lead 22 and maintain the interval between the leads.
【００１３】前記各リード２２上に１個所ずつ導電性イ
ンキ２５を塗布する。前記導電性インキの材料として
は、例えば、銅、銀、金、パラジウム、ロジウム、ある
いはこれら金属の合金が好適である。A conductive ink 25 is applied on each of the leads 22 one by one. As the material of the conductive ink, for example, copper, silver, gold, palladium, rhodium, or an alloy of these metals is preferable.
【００１４】図３を参照すると、前記リード２２上の導
電性インキ２５は断面が楕円形に近い形状をしている。
前記導電性インキ２５は多様な方法によりリードの上面
に塗布されることができるが、例えば、シルクスクリー
ンプリンティング（silk screen printing）、金属マス
ク（metal mask）を用いた塗布、噴射（injection）及
びディスペンシング（dispensing）法を用いた塗布、ド
ット法（dotting）による塗布などが挙げられる。Referring to FIG. 3, the conductive ink 25 on the lead 22 has a cross section that is almost elliptical.
The conductive ink 25 can be applied to the upper surface of the lead by various methods, for example, silk screen printing, application using a metal mask, injection, and dispensing. Coating using a dispensing method, coating by a dot method, and the like.
【００１５】かかる方法により塗布された導電性インキ
２５は、各インキの上側表面が同一平面上にくるように
圧印加工（coining）する工程を経て、図４に示すよう
に、断面の形状がほぼ矩形となる。この時、導電性イン
キ２５の高さは絶縁テープ２４の高さと等しいか、それ
とも更に高いのが好適である。The conductive ink 25 applied by such a method has a step of coining so that the upper surface of each ink is on the same plane, and as shown in FIG. It becomes a rectangle. At this time, the height of the conductive ink 25 is preferably equal to or higher than the height of the insulating tape 24.
【００１６】前記圧印加工に先立って予備硬化処理（pr
e-curing）を施すことが好ましい。前記予備硬化処理
は、圧印加工の際に導電性インキが変形したり、クラッ
クが生じたりすることを防止するために、液状の導電性
インキを乾燥させる工程である。また、圧印加工後に後
硬化処理を施すことが好ましいが、前記後硬化処理は、
圧印加工後に導電性インキが変形するのを防止するため
の工程である。Prior to the coining, a pre-curing treatment (pr
e-curing) is preferred. The preliminary curing treatment is a step of drying the liquid conductive ink in order to prevent the conductive ink from being deformed or cracked during coining. In addition, it is preferable to perform a post-curing process after the coining process.
This is a step for preventing the conductive ink from being deformed after coining.
【００１７】導電性インキ２５の圧印加工後、図５に示
すように、ダイパッド２１の上面に接着テープ２６を以
て半導体チップ３０を付着する。After stamping the conductive ink 25, the semiconductor chip 30 is attached to the upper surface of the die pad 21 with an adhesive tape 26 as shown in FIG.
【００１８】半導体チップ３０の端子は金のワイヤ２７
によりリード２２と結ばれる。The terminals of the semiconductor chip 30 are gold wires 27.
Is connected to the lead 22.
【００１９】それから、リードフレームはモールディン
グ樹脂２９でモールドされ、モールディング樹脂の外部
にはみ出たリードフレームのリード２２は切り取られ
る。導電性インキ２５の一端面はモールディング樹脂２
９の外部に露出される。Then, the lead frame is molded with a molding resin 29, and the leads 22 of the lead frame which protrude outside the molding resin are cut off. One end surface of the conductive ink 25 is a molding resin 2
9 is exposed outside.
【００２０】この時、図６に示すように、各導電性イン
キ２５の高さが不揃いで、モールディング樹脂の外部に
露出しない導電性インキ２５があると、はんだボール２
８との電気的接続を形成できなくなる。この場合、モー
ルディング樹脂の外部に導電性インキを露出させるため
に、モールディング樹脂層の研磨等の平面加工を行っ
て、導電性インキの端面が均一に露出するようにしなけ
ればならない。At this time, as shown in FIG. 6, if the conductive inks 25 are not uniform in height and are not exposed to the outside of the molding resin, the solder balls 2
8 cannot be formed. In this case, in order to expose the conductive ink to the outside of the molding resin, it is necessary to perform planar processing such as polishing of the molding resin layer so that the end surface of the conductive ink is uniformly exposed.
【００２１】このように、モールディング樹脂２９の外
部に露出された導電性インキ２５の上面にはんだボール
２８を接着する。このはんだボール２８は、半導体チッ
プ３０、ワイヤーボンディングにより接続されたリー
ド、及び導電性インキを介して外部機器の接続端子と電
気的に接続される。As described above, the solder ball 28 is bonded to the upper surface of the conductive ink 25 exposed outside the molding resin 29. The solder ball 28 is electrically connected to a connection terminal of an external device via a semiconductor chip 30, a lead connected by wire bonding, and conductive ink.
【００２２】その結果、リードに形成された導電性イン
キは、１行おきに同一のはんだボール列を有することに
より、狭い領域内に設けられた多くの接続端子と接続結
ばれることが可能になる。As a result, the conductive ink formed on the leads can be connected to many connection terminals provided in a narrow area by having the same solder ball row every other row. .
【００２３】本発明を、図面に示した実施例に基づいて
説明したが、これは単なる例示に過ぎず、当業者は、こ
れより様々な変形及び均等な他の実施例が可能であるこ
とが理解されよう。Although the present invention has been described with reference to the embodiment shown in the drawings, this is merely an example, and those skilled in the art will appreciate that various modifications and other equivalent embodiments are possible. Will be understood.
【００２４】[0024]
【発明の効果】以上のように、本発明によれば、リード
フレームに導電性インキを塗布して使用することから、
電気的／熱的安定性が高く、変形しにくく、加工が容易
で、寸法の誤差の少ない半導体パッケージを容易に製造
でき、更には、製造費用節減をもたらす。As described above, according to the present invention, since conductive ink is applied to a lead frame and used,
A semiconductor package having high electrical / thermal stability, being difficult to deform, being easy to process, and having a small dimensional error can be easily manufactured, and further reduces manufacturing costs.
【図１】本発明によるＢＧＡ半導体パッケージのリード
フレームを概略的に示した平面図である。FIG. 1 is a plan view schematically showing a lead frame of a BGA semiconductor package according to the present invention.
【図２】図１のＡ部分を抜粋して概略的に示した平面図
である。FIG. 2 is a plan view schematically showing a portion A in FIG.
【図３】図２のＢ部分を抜粋して示した断面図である。FIG. 3 is a cross-sectional view showing a portion B of FIG.
【図４】圧印加工された導電性インキが付着されたリー
ドフレームを示す断面図である。FIG. 4 is a cross-sectional view showing a lead frame to which stamped conductive ink is attached.
【図５】モールディングされた半導体パッケージを示す
断面図である。FIG. 5 is a sectional view showing a molded semiconductor package.
【図６】導電性インキの高さが不揃いの半導体パッケー
ジを示す断面図である。FIG. 6 is a cross-sectional view showing a semiconductor package in which conductive inks have different heights.
【図７】モールディング樹脂層を均一に平面加工した半
導体パッケージを示す断面図である。FIG. 7 is a cross-sectional view showing a semiconductor package in which a molding resin layer is uniformly processed in a plane.
【図８】はんだボールを用いた半導体パッケージを示す
断面図である。FIG. 8 is a sectional view showing a semiconductor package using solder balls.
【図９】図８に示したはんだボールの配置を示す底面図
である。FIG. 9 is a bottom view showing the arrangement of the solder balls shown in FIG. 8;
２０ リードフレーム ２１ ダイパッド ２２ リード ２４ 絶縁テープ ２５ 導電性インキ ２６ 接着テープ ２７ ボンディングワイヤ ２８ はんだボール ２９ モールディング樹脂 ３０ 半導体チップ Reference Signs List 20 lead frame 21 die pad 22 lead 24 insulating tape 25 conductive ink 26 adhesive tape 27 bonding wire 28 solder ball 29 molding resin 30 semiconductor chip
Claims (13)
により接続されたリードを有するＢＧＡ半導体パッケー
ジにおいて、 前記各リードに設けられる導電性インキと、 前記導電性インキに付着され、外部基板の端子と接続さ
れるはんだボールとを有することを特徴とするＢＧＡ半
導体パッケージ。1. A BGA semiconductor package having leads connected to a semiconductor chip by wire bonding, a conductive ink provided on each of the leads, and a solder attached to the conductive ink and connected to a terminal of an external substrate. A BGA semiconductor package having a ball.
の端面が同一平面上にくるように圧印加工により形成さ
れることを特徴とする請求項１に記載のＢＧＡ半導体パ
ッケージ。2. The BGA semiconductor package according to claim 1, wherein the conductive ink is formed by coining such that the end faces of the conductive inks are on the same plane.
金、パラジウム、ロジウム、またはこれらの中から選択
された金属の合金であることを特徴とする請求項１に記
載のＢＧＡ半導体パッケージ。3. The material of the conductive ink is copper, silver,
The BGA semiconductor package according to claim 1, wherein the BGA semiconductor package is made of gold, palladium, rhodium, or an alloy of a metal selected from these.
点を単位格子とする斜形格子状に配置されていることを
特徴とする請求項１に記載のＢＧＡ半導体パッケージ。4. The BGA semiconductor package according to claim 1, wherein the solder balls are arranged in an oblique lattice pattern with a vertex of a parallelogram as a unit cell.
の絶縁テープを更に有することを特徴とする請求項１に
記載のＢＧＡ半導体パッケージ。5. The BGA semiconductor package according to claim 1, further comprising an insulating tape for maintaining an interval between the leads.
位格子とする斜形格子状に配置されていることを特徴と
する請求項１に記載のＢＧＡ半導体パッケージ。6. The BGA semiconductor package according to claim 1, wherein the solder balls are arranged in an oblique lattice pattern with a vertex of a diamond as a unit lattice.
過程と、 半導体チップの端子とリードとをワイヤボンディングに
より接続し、これらを樹脂でモールディングする過程
と、 導電性インキに、外部基板の端子と接続されるはんだボ
ールを接続させる過程とを含むことを特徴とするＢＧＡ
半導体パッケージの製造方法。7. A step of applying a conductive ink on each lead, a step of connecting terminals of the semiconductor chip to the leads by wire bonding, and a step of molding them with a resin; Connecting a solder ball connected to the BGA.
A method for manufacturing a semiconductor package.
ッケル−鉄の合金からなることを特徴とする請求項７に
記載のＢＧＡ半導体パッケージの製造方法。8. The method as claimed in claim 7, wherein the metal substrate is made of copper, a copper alloy, or a nickel-iron alloy.
する過程が、 前記導電性インキの端面が同一平面上にくるように前記
導電性インキを圧印加工するする過程を更に含むことを
特徴とする請求項７に記載のＢＧＡ半導体パッケージの
製造方法。9. The method of applying conductive ink on each of the leads, further comprising the step of stamping the conductive ink such that end faces of the conductive ink are on the same plane. The method for manufacturing a BGA semiconductor package according to claim 7.
布する過程が、 スクリーンプリンティング法（screen printing）を用
いて導電性インキを塗布する過程、金属マスクを用いて
導電性インキを塗布する過程、噴射及びディスペンシン
グ法（injection and dispensing）を用いて導電性イン
キを塗布する過程、あるいはドット法（dotting）によ
り導電性インキを塗布する過程の中から選択された何れ
か１つであることを特徴とする請求項７に記載のＢＧＡ
半導体パッケージの製造方法。10. The step of applying conductive ink on each of the leads, the step of applying conductive ink using a screen printing method, the step of applying conductive ink using a metal mask, It is one of a process of applying a conductive ink by using an injection and dispensing method or a process of applying a conductive ink by a dot method. The BGA according to claim 7, wherein
A method for manufacturing a semiconductor package.
布する過程が、 導電性インキがモールディング樹脂の外部に露出される
ようにモールディング樹脂を平面加工する過程を含んで
なることを特徴とする請求項７に記載のＢＧＡ半導体パ
ッケージの製造方法。11. The method of applying a conductive ink on each of the leads, comprising: flattening a molding resin such that the conductive ink is exposed outside the molding resin. Item 8. The method for manufacturing a BGA semiconductor package according to Item 7.
布する過程が、 導電性インキの圧印加工する前に、それぞれ導電性イン
キの変形を防止するために乾燥させる前硬化処理を行う
過程を含むことを特徴とする請求項８に記載のＢＧＡ半
導体パッケージの製造方法。12. The step of applying the conductive ink on each of the leads includes a step of performing a pre-curing process of drying the conductive ink to prevent deformation of the conductive ink before stamping the conductive ink. 9. The method of manufacturing a BGA semiconductor package according to claim 8, wherein:
布する過程が、 導電性インキの圧印加工後に、導電性インキの変形を防
止するための後硬化処理を行う過程を含むことを特徴と
する請求項１２に記載のＢＧＡ半導体パッケージの製造
方法。13. The method according to claim 12, wherein the step of applying the conductive ink on each of the leads includes a step of performing a post-curing process after the stamping of the conductive ink to prevent the conductive ink from being deformed. A method for manufacturing a BGA semiconductor package according to claim 12.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1997-9483 | 1997-03-20 | ||
| KR1019970009483A KR100243375B1 (en) | 1997-03-20 | 1997-03-20 | BGA package and the method of it |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10270597A true JPH10270597A (en) | 1998-10-09 |
Family
ID=19500194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10069676A Pending JPH10270597A (en) | 1997-03-20 | 1998-03-19 | Bga semiconductor package and its manufacture |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH10270597A (en) |
| KR (1) | KR100243375B1 (en) |
| TW (1) | TW419768B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102023100B1 (en) * | 2018-05-15 | 2019-11-04 | 주식회사 네패스 | Semiconductor Package |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2837355B2 (en) * | 1994-09-09 | 1998-12-16 | 川崎製鉄株式会社 | Semiconductor IC chip package, method of manufacturing the same, and lead frame |
-
1997
- 1997-03-20 KR KR1019970009483A patent/KR100243375B1/en not_active IP Right Cessation
-
1998
- 1998-03-18 TW TW087103980A patent/TW419768B/en not_active IP Right Cessation
- 1998-03-19 JP JP10069676A patent/JPH10270597A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| KR100243375B1 (en) | 2000-02-01 |
| TW419768B (en) | 2001-01-21 |
| KR19980073899A (en) | 1998-11-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7507606B2 (en) | Semiconductor device and method of manufacturing the same | |
| US6841414B1 (en) | Saw and etch singulation method for a chip package | |
| US5869905A (en) | Molded packaging for semiconductor device and method of manufacturing the same | |
| JP2002353369A (en) | Semiconductor package and its manufacturing method | |
| JP3046024B1 (en) | Lead frame and method of manufacturing resin-encapsulated semiconductor device using the same | |
| US6642082B2 (en) | Method for manufacturing a resin-sealed semiconductor device | |
| JPH08279591A (en) | Semiconductor device and its manufacture | |
| KR101041228B1 (en) | Test pads on flash memory cards | |
| EP0623954B1 (en) | Molded plastic packaging of electronic devices | |
| JP3478139B2 (en) | Lead frame manufacturing method | |
| JP2000307049A (en) | Lead frame, resin-sealed-type semiconductor device using lead frame, and its manufacturing method | |
| JP4334047B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2001024133A (en) | Lead frame, resin sealed semiconductor device employing it and manufacture thereof | |
| JPH10270597A (en) | Bga semiconductor package and its manufacture | |
| JP3103281B2 (en) | Resin-sealed semiconductor device | |
| JP2001077283A (en) | Lead frame and manufacture of resin-sealed semiconductor device using the same | |
| JPH11260850A (en) | Semiconductor device and its manufacture | |
| JP3293753B2 (en) | Semiconductor package chip support substrate and semiconductor package using the same | |
| JPH03105961A (en) | Resin-sealed semiconductor device | |
| JPH0547954A (en) | Resin sealed semiconductor device | |
| JP2001077275A (en) | Lead frame and manufacture of resin-sealed semiconductor device using the same | |
| KR100231841B1 (en) | B.g.a semiconductor package | |
| JP2001077136A (en) | Manufacture of plastic molded semiconductor device | |
| JPH07106485A (en) | Resin-sealed pin grid array | |
| JPH11195743A (en) | Semiconductor device and manufacture thereof |