KR19980065850A - Motor Drive Icy Pd Limiting Circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Pd limiting circuit of a motor drive ice, and particularly includes a circuit for limiting the increase in Pd of a power transistor under abnormal operation occurring when the motor rotates in a rotational direction, thereby protecting the transistor and reducing heat generation. It relates to a Pd limit circuit for smooth operation.

Description

Motor Drive Icy Pd Limiting Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor drive IC (IC). In particular, the motor drive operation is performed by limiting the increase of the power transistor (Pd) of the power transistor under abnormal operation occurring when the rotational direction of the motor is changed, thereby protecting the transistor and reducing heat generation. The Pd limit circuit of the motor drive Icy smoothly.

1 is a circuit diagram showing an output stage of a three-phase propagation driving method according to the prior art, in which a first output controller 1, a first load 3, a second output controller 5, a second load 7, And a third output control unit 9 and a third load 11.

On the other hand, the first output control unit 1 is a current path between the pair of first and second transistors Q10 and Q7 made of a current mirror, the first power supply voltage VCC and the first node N1. Is connected to the third transistor Q1 in response to the output signal of the second transistor Q7, a reverse diode D1 connecting the collector terminal and the emitter terminal of the third transistor Q1, and the first node. A fourth transistor Q4 connected to a current path between the N1 and the second power supply voltage VSS and responding to a predetermined signal, and a reverse diode connecting the collector terminal and the emitter terminal of the fourth transistor Q4; D4), and the first load 3 is connected between the first node N1 and the fourth node N4.

In addition, the second output controller 5 and the third output controller 9 are configured in the same structure as the first output controller 1, as shown in the same figure, and the first load 3 and The third load 11 is connected in series with each other, the second load 7 is connected in parallel with the first load 3 and the third load 11, the load is made of a coil.

In general, the output stage of the motor drive Icy operates one of the upper and lower sides in the saturation mode, and for this purpose, the current ratio supplied to the base stage of the upper and lower power transistors is different, and the difference in the ratio varies from system to system.

In the case of the same figure, the lower transistors Q4, Q5 and Q6 are operated in the saturation mode, and the upper transistors Q1, Q2 and Q3 are operated in the active mode.

Let us assume a state that can occur during the operation of the motor in the same figure.

First, when transistors Q2 and Q4 are turned on and current flows in the first and second loads 3 and 7, and transistor Q3 is almost off and there is almost no flow of current, in the next state, Q3 eventually becomes As it is completely off and the current at Q4 decreases, the current at Q6 gradually increases, eventually turning Q4 off and Q2, Q6 on, changing the current path of the load from L2 → L1 to L2 → L3.

If Q2 and Q4 are full on and Q3 is off in the first assumption, the emitter voltage of Q2 is

[Equation 1]

That is, R: resistance component of the load, E: counter electromotive force generated in the motor coil.

If the direction is changed to rotate the motor in the opposite direction from the current rotation direction, the emitter voltage of Q2 in the transient state is given by Equation 2 below.

[Equation 2]

In Equation 2 above, the counter voltage is E≥R * In this case, the emitter potential of Q4 falls below the ground voltage (GND) level, and the current supply is made by Q2 and D5.

In addition, the counter voltage is E≤R * If is Is at the potential above ground voltage in the present state, but when transistor Q6 is turned on in the next state (Q4 is operating in saturation mode, the current of Q4 is maintained for a while even if transistor Q6 is turned on. The saturation becomes deep, and the current holding time of Q4 becomes long). At this time, the emitter potential of Q2 is expressed by the following equation.

[Equation 3]

In the above formula, the counter voltage is E≥R * In this case, the lower diode D5 is turned on to supply current to Q4 and Q6 together with Q2. As in the above two cases, the upper transistor Q2 operates at its limit current level during rotation conversion, and the voltage applied to Vce of Q2 also shows a large increase, and Pd of Q2 increases rapidly as the counter voltage increases. .

In the first case of the above two states, Pd of the Q2 transistor is obtained with reference to FIG.

[Equation 4]

In Equation 4 above, to reduce the Pd of the Q2 transistor, We can see that we can increase by and we can get the same conclusion in the second case.

Also, Increasing may weaken the saturation state of the lower transistors, thereby reducing the switching delay caused by deep saturation.

Conventionally, as described above, the transistor is overheated due to an increase in Pd (maximum loss, power loss) of the power transistor, which may cause the transistor to break or malfunction.

An object of the present invention is to solve the problems of the prior art, by limiting the increase of the power transistor Pd under abnormal operation occurring during the rotational direction of the motor to protect the transistor and reduce heat generation smoothly the motor drive operation One is to provide a Pd limit circuit of the motor drive Icy.

In order to achieve the above object, the apparatus of the present invention comprises: a pair of first and second transistors each including a current mirror; A pair of third and fourth transistors connected with a current path between one end of the second transistor and a ground voltage and responsive to the first power supply voltage through a resistor; A fifth transistor connected between one end of the first transistor and a second power supply voltage and responding to a predetermined signal; A sixth transistor connected between an input terminal of the third transistor and a second power supply voltage and responding to a predetermined signal; A seventh transistor connected with a current path between the first node and the second power supply voltage and responsive to a signal of the first node; A pair of tenth and eleventh transistors configured by a current mirror to receive the first power voltage; A twelfth transistor connected with a current path between the first power supply voltage and the second node and responsive to the switching signals of the tenth and eleventh transistors; A thirteenth transistor connected to a first power supply voltage, a predetermined input terminal, and a current path and responsive to switching signals of the tenth and eleventh transistors; A fourteenth transistor coupled to a current path between the first power supply voltage and the third node and responsive to an output signal of the thirteenth transistor; A reverse diode connecting the collector terminal and the emitter terminal of the fourteenth transistor; A fifteenth transistor coupled to a current path between the second node and a second power supply voltage and responsive to a signal of the first node; A sixteenth transistor coupled with a current path between the second node and a second power supply voltage and responsive to a signal from a fourth node; A forward diode coupled between the second node and a second power supply voltage; A seventeenth transistor coupled to a current path between a collector terminal of the eleventh transistor and a third node and responsive to a signal of the second node; An eighteenth transistor connected with a current path between the third node and a second power supply voltage and responsive to a predetermined signal; A reverse diode connecting the collector and the emitter terminal of the eighteenth transistor; And a first load coupled between the third node and the fourth node.

1 is a circuit diagram showing an output stage of a three-phase propagation driving method according to the prior art.

FIG. 2 is a diagram for describing a method for obtaining Pd of FIG. 1.

3 is a circuit diagram showing an output stage of a three-phase propagation driving method according to the present invention.

4 is a diagram illustrating the current sum of the transistors of FIG. 3.

Hereinafter, with reference to the accompanying drawings will be described in more detail the present invention.

3 is a circuit diagram showing an output stage of a three-phase propagation driving method according to the present invention, wherein the output unit 10, the first output control unit 20, the first load 25, the second output control unit 30, The second load 35 includes a third load control unit 40 and a third load 45.

On the other hand, the output unit 10 is connected to a pair of first and second transistors (Q1, Q2) consisting of a current mirror, the current path is connected between the one end of the second transistor (Q2) and the ground voltage (GND) And a pair of third and fourth transistors Q3 and Q4, which respond to the first power supply voltage VCC through the resistors R1 and R2, one end of the first transistor Q1 and the second power supply voltage ( The current path is connected between the VSS and the fifth transistor Q5 responding to the predetermined signal, and the current path is connected between the input terminal of the third transistor Q3 and the second power supply voltage VSS and the predetermined signal. A sixth transistor Q6 in response to the current path, and a current path is connected between the first node Nd1 and the second power supply voltage VSS, and the seventh transistor Q7 responding to the signal of the first node Nd1. Consists of

The first output controller 20 also includes a current path between the pair of tenth and eleventh transistors Q10 and Q11 formed of a current mirror, the first power voltage VCC and the second node Nd2. Is connected to the twelfth transistor Q12 that responds to the switching signal of the current mirror, the first power supply voltage VCC, a predetermined input terminal and a current path is connected to the thirteenth transistor that responds to the switching signal of the current mirror ( A fourteenth transistor Q14 and a fourteenth transistor Q14 connected to a current path between the first power supply voltage VCC and the third node Nd3 and responding to an output signal of the thirteenth transistor Q13; A reverse current diode D3 connecting the collector terminal and the emitter terminal of Q14, a current path is connected between the second node Nd2 and the second power supply voltage VSS, and connected to a signal of the first node Nd1. Between the fifteenth transistor Q15 and the second node Nd2 and the second power supply voltage VSS. A sixteenth transistor Q16 connected to a current path and responding to a signal of a fourth node Nd4, a forward diode D1 connected between the second node Nd2 and the second power supply voltage VSS, and A current path is connected between the collector terminal of the eleventh transistor Q11 and the third node Nd3, and the seventeenth transistor Q17 responding to the signal of the second node Nd2, and the third node Nd3, An eighteenth transistor Q18 connected with a current path between the second power supply voltage VSS and responding to a predetermined signal, a reverse diode D2 connecting the collector and emitter terminal of the eighteenth transistor Q18, and The first load 25 is connected between the third node Nd3 and the fourth node Nd4.

Meanwhile, the second output controller 30 and the third output controller 40 are configured in the same structure as the first output controller 20.

In addition, as shown in the drawing, the first load 25 connected between the first node Nd1 and the fourth node Nd4 and the third load connected between the third node Nd3 and the fourth node Nd4. 45 are connected in series with each other, and the second load 35 connected between the second node Nd2 and the fourth node Nd4 is parallel with the first load 25 and the third load 45, respectively. The loads 25, 35 and 45 are made of coils.

The basic operation is that when the diodes D1 (D1_1, D1_2, and DA_n have the same function as DA, only DA is shown) as shown in the drawing, when the emitter potential of transistor Q14 decreases and Q17 is on, As the current at Q14 increases and the emitter potential rises again, reducing Vce, the current increases but Pd eventually decreases.

Multiple D1's can be connected in series to adjust the Vce voltage of Q14.

Q7 is the sum of the three-phase currents at the upper ends, as shown in FIG.

As shown in FIG. 4, the transistor Q7 represents a constant value as a sum of currents of Q10, Q10_1, and Q10_2. The current of Q15 is adjusted to the area ratio of the transistor to be slightly smaller than the current of Q7 as shown in FIG. 4 and when the current of transistor Q10 is equal to the current of Q15, D1 is on to limit the Vce of Q14 as previously described.

The current difference between transistors Q15 and Q7 provides a margin for the peak range.

The above operation by the transistors Q12 and Q15 is to prevent the limiting operation of Pd in the low current section while the current of Q10 rises.

When transistor Q16 is on, D1 is off and no Pd limit operation is performed.

In this case, the current of the upper power transistor is operated in a range lower than its limit value, and the current flowing through the transistor is small and Pd is low.

VR1 ego

If VR1 <VR2, Q16 is obtained, and accordingly the current for which the Pd limit operation is performed can be freely selected according to the set value of VR2.

In this way, when the upper power transistor is driven by the limit current, if the current of the warmed phase of the upper power transistors of the three phases reaches its limit value, the increase of Vce is suppressed and the transistor is operated in the SOA region, thereby damaging the transistor and causing damage to the PKG. Can solve the fever problem.

Therefore, as described above, the present invention has the effect of limiting the increase of Pd of the power transistor under abnormal operation occurring when the rotational direction of the motor is changed to protect the transistor, and reduce the generation of heat to smooth the motor drive operation. .

Claims (2)

A pair of first and second transistors each including a current mirror; A pair of third and fourth transistors connected with a current path between one end of the second transistor and a ground voltage and responsive to the first power supply voltage through a resistor; A fifth transistor connected between one end of the first transistor and a second power supply voltage and responding to a predetermined signal; A sixth transistor connected between an input terminal of the third transistor and a second power supply voltage and responding to a predetermined signal; A seventh transistor connected with a current path between the first node and the second power supply voltage and responsive to a signal of the first node; A pair of tenth and eleventh transistors configured by a current mirror to receive the first power voltage; A twelfth transistor connected with a current path between the first power supply voltage and the second node and responsive to the switching signals of the tenth and eleventh transistors; A thirteenth transistor connected to a first power supply voltage, a predetermined input terminal, and a current path and responsive to switching signals of the tenth and eleventh transistors; A fourteenth transistor coupled to a current path between the first power supply voltage and the third node and responsive to an output signal of the thirteenth transistor; A reverse diode connecting the collector terminal and the emitter terminal of the fourteenth transistor; A fifteenth transistor coupled to a current path between the second node and a second power supply voltage and responsive to a signal of the first node; A sixteenth transistor coupled with a current path between the second node and a second power supply voltage and responsive to a signal from a fourth node; A forward diode coupled between the second node and a second power supply voltage; A seventeenth transistor coupled to a current path between a collector terminal of the eleventh transistor and a third node and responsive to a signal of the second node; An eighteenth transistor connected with a current path between the third node and a second power supply voltage and responsive to a predetermined signal; A reverse diode connecting the collector and the emitter terminal of the eighteenth transistor; And a first load coupled between said third node and a fourth node. The Pd limit circuit of the motor drive ice according to claim 1, wherein a plurality of configurations from the tenth transistor to the first load can be provided.