KR19980060864A - Power-up Signal Generation Circuit - Google Patents

Abstract

The present invention relates to a power-up signal generating circuit capable of quickly responding to changes in external voltage, and to implement this, first potential level detection means for outputting a signal for detecting a potential level of a first power source voltage source, and a second Second-level level detection means for outputting a signal for detecting a potential level of a power source voltage source, and multi-level for logically combining the output signals of the first and second potential level detection means and inputting the initial value setting of a memory peripheral circuit; Decoding means.

Description

Power-up Signal Generation Circuit

In general, the power-up signal of RAM (hereinafter referred to as 'Pwrup') is used for initializing when the circuits in semiconductor memory are turned on (hereinafter referred to as 'Vcc'). In special cases, it is used as an enable signal and also used to set various signals that must be set before normal operation.

For example, a blown fuse information of a redundant circuit of a RAM may be used as a enable signal for decoding a delayed signal from a signal sensed at turn-on.

Hereinafter, a method of implementing a power-up signal generation circuit in a conventional technology in a semiconductor memory device will be described with reference to FIG. 1.

As shown in FIG. 1, the power-up signal generating circuit includes a substrate potential (hereinafter referred to as 'Vbb') level detection unit 10 and a driver unit 20. The signal pwrup generated is a random access control unit. Memory Control Circir) 30 is a technology for driving.

In the conventional operation configuration, when the power supply voltage Vcc is turned on, the power supply bus inside the chip reaches a predetermined dc value after a predetermined rise time to complete the powder turn-on. If the substrate voltage (Vbb) falls below -2Vt during the rise time (the detailed operation configuration of the Vbb generator will be omitted), the potential of node N1 is initially turned on by the P-MOS transistor MP11. Although the N-MOS transistors MN11 and MN12 connected in series between the nodes N1 and Vbb are turned on, the node N1 is changed to a 'logic low' level.

The driver unit 20 connected between the node N1 and the output signal pwrup is composed of gates G11 to G15 and a transistor MP13, and its operation configuration is simply a buffer connection to set the 'logic low' level of the node N1 to the final output pwrup signal. Create a logic high level to complete the power up operation. The P-MOS transistor MP13 having a source connected to a power supply voltage, a drain connected to a node N2, and a gate connected to a node N3 has a circuit connection structure for preventing floating of the node N2.

On the other hand, when the power supply voltage is turned off, the chip internal power bus reaches a predetermined dc value after a certain fall time to complete the power turn-off. At this time, the discharge and power supply voltage of Vbb are completed. In proportion to the off time of the pwrup signal changes to the disabled state, or logic.

The problem of the conventional power-up signal generation circuit as described above is that the power-up signal (pwrup) mounted on the chip when the power supply voltage is frequently turned on or off is also a state of the power supply voltage ( On or Off repetition) to enable or disable state, this operation process is performed before the operation if the Vcc voltage level is off but the Vbb voltage level is discharged late causing the power-up signal to malfunction There is a problem in the initial value setting required in the control circuit of the RAM that should be performed, and as a result, normal operation cannot be performed. In other words, the power-up signal generated by sensing the Vbb voltage level corresponding to the on / off of the power supply voltage cannot be provided.

Accordingly, an object of the present invention is to provide a power-up signal generation circuit that can respond quickly to external voltage changes.

1 is a conventional power-up signal generation circuit diagram.

2 is a block diagram of a power-up signal generation circuit according to an embodiment of the present invention.

3 is a detailed circuit diagram of a Vcc level detector shown in FIG. 2;

4 is a detailed circuit diagram of a multi-level decoder shown in FIG. 2;

5 is an operation timing diagram of each signal shown in FIG. 2;

* Description of the symbols for the main parts of the drawings *

40: Vbb level detection unit 20: driver unit

30, 70: RAM control circuit 50: Vcc level detector

60: multi-level decoder section

In order to achieve the above object, the power-up signal generating circuit according to the present invention includes a first potential level detecting means for outputting a signal for detecting a potential level of a first power source voltage source, and a potential level of the second power source voltage source. Second potential level detection means for outputting a signal, and multi-level decoding means for logically combining the output signals of the first and second potential level detection means and inputting the initial value setting of the memory peripheral circuit.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a power-up signal generating circuit according to the first embodiment of the present invention, in which 'Vbbdet' and 'Vccdet' are formed from the Vbb voltage level detecting unit 40 and the Vcc voltage level detecting unit 50. The final output power-up signal pwrup generated by the multi-level decoder unit 60, which is generated and operated by the two signals, respectively, is configured to drive the control circuit unit 70 of the RAM.

The Vbb voltage level detection unit 40 has the same configuration and operation as the Vbb voltage level detection unit 40 shown in FIG. 1, and detailed configuration and operation description thereof may be omitted.

The Vcc voltage level detector 50 is shown in FIG. 3, and the multi-level decoder 60 is shown in FIG. 4.

First, referring to FIG. 3, the Vcc voltage level detector 50 includes a resistor R1 connected between Vcc and a node N4, a resistor R2 and an N-MOS transistor MN13 connected in series between the node N4 and Vss. The N-MOS transistor MN13 has Vcc applied to its own gate. And P-MOS transistors MP14 and MP15 connected between Vcc, node N5 and node N6, respectively, having a gate connected to node N6 in common, and N− connected between node N5 and node N7 with a gate connected to node N4. N-MOS transistor MN15 connected between MOS transistor MN14 and node N6 and node N7 and having a reference voltage Vref applied to a gate, and N-MOS connected between node N7 and Vss and applied Vcc to gate 16th to 18th inverters G16 to G18 connected in series between the transistor MN16 and the node N5 and the output terminal.

When the power supply voltage (Vcc) is turned on, the transistor MN13 is turned on so that a current flows between the external voltage (Vcc) and the ground (Vss), and the voltage of the two resistors R1 and R2 distributes the voltage so that the potential of the node N4 becomes the external voltage (Vcc ). The voltage comparator consisting of the transistors MN14, MP14, MN15 and MN16 is a known differential amplifier structure, with a first input connected to the node N4 and a second input connected to the reference voltage Vref. For example, in the case of 'V _N4 V _ref ', the node N4 outputs the logic high voltage and the node N6 outputs the logic low voltage level. In the case of V _N4 V _ref , the node N4 outputs logic low. Node N6 outputs a logic high voltage level. Inverters G16, G17 and G18 between the voltage comparator and the output signal vccdet output the final 'vccdet' to the buffer connection.

FIG. 4 is a detailed circuit diagram of the multi-level decoder 60 shown in FIG. 2, which outputs a NAND logic operation by inputting the output signals of the Vbb level detector 40 and the Vcc level detector 50, respectively. It becomes a pwrup signal which is a final output signal generated through the NAND gate G19 and the inverter G20 connected to the output terminal of the NAND gate G19.

A partial description of the embodiment according to the present invention has been made with the logic configuration as described above, and for convenience of understanding the overall operation configuration, it will be described with reference to the operation timing diagram shown in FIG.

As shown in the operation timing diagram of FIG. 5, when the power supply voltage Vcc is turned on, the internal power Vcc (a) on the chip completes the power-on state for several tens of mSEC to several hundred mSEC in the form of a ramp waveform. In the process, the on-chip substrate bias generator operation causes the Vbb potential (b) to have a negative voltage, and when the potential drops below -2V _T , the output of the Vbb voltage level detector 40, 'vbbdet' (c) Is transitioned from logic low to logic high. Meanwhile, when the condition that the power supply voltage is VccVref is satisfied, the output of the Vcc voltage level detector 50, 'vccdet' transitions from logic low to logic high. When both signals vbbdet and vccdet have a logic high level, the output of the multi-level decoder unit 60, pwrup, transitions to logic high to complete the power-up cycle.

Conversely, when the supply voltage is turned off, the internal power on the chip, Vcc, typically completes the power-off state for several tens of mSEC to hundreds of mSEC in the form of a ramp waveform. As time elapses, the ground potential changes, and the 'vbbdet' signal (d) has a logic low state in proportion to the Vbb and Vcc potentials, and when the condition that the power supply voltage is VccVref is satisfied, The output 'vccdet' transitions from logic high to logic low. The output of the multi-level decoder unit 60, pwrup, is the logic of the two signals (vbbdet and vccdet) that reach the logic low level first ('vccdet' first transitions to logic low in the timing diagram of FIG. 5). Transition to low to complete the power off cycle.

As described above, when the power-up signal generation circuit according to the embodiment of the present invention is used inside the semiconductor memory device, it is possible to design a powder-up signal generation circuit that can respond quickly to changes in external voltage.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims below You will have to look.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-up signal generating circuit of a semiconductor memory device, and more particularly to a power-up signal generating circuit that can respond quickly to changes in external voltage.

Claims (6)

In a semiconductor memory device, First potential level detection means for outputting a signal that senses a potential level of the first power source voltage source; Second potential level detection means for outputting a signal that senses the potential level of the second power source voltage source; And multi-level decoding means for logic-joining the output signals of the first and second potential level detection means to input the initial value setting of the memory peripheral circuit. The method of claim 1, The first power source voltage source is a substrate bias potential, And the second power supply voltage source is a power supply voltage. The method of claim 1, And said first potential level detecting means has a configuration in the form of a voltage divider by a resistive element connected between a power supply voltage and a substrate bias voltage. The method of claim 1, And said second potential level detecting means detects a change in power supply voltage using a differential amplifier structure. The method of claim 1, And said multi-level decoding means is a logical sum circuit. The method of claim 1, And the multi-level decoding means is a AND-circuit circuit.