KR0171941B1 - Back bias voltage generating circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a back bias potential generating circuit of a semiconductor memory device, comprising: a pumping circuit for controlling the operation of a pumping circuit according to an output signal from a potential sensing means for sensing a potential of a data input / output pin and a state of a substrate potential; The control means prevents the chip from malfunctioning due to the negative noise generated in the data output buffer.

Description

Back bias potential generating circuit

1 is a conventional back bias potential generating circuit diagram.

2 is a block diagram of a conventional data output buffer and a data input buffer.

3 is a block diagram of a back bias potential generating circuit according to the present invention.

4 is a circuit diagram of the potential detector shown in FIG.

5 is a circuit diagram of the Vbb pump controller shown in FIG.

6 is an operation timing diagram of the Vbb pump control circuit shown in FIG.

7 is a circuit diagram of the ring oscillator shown in FIG.

8 is a circuit diagram of the Vbb pump shown in FIG.

* Explanation of symbols for main parts of the drawings

11 Vbb potential level detector 12 ring oscillator

13 Vbb potential pumping circuit 14 pull-up driver driving circuit

15 pull-down driver drive circuit 16 input / output pad

17: data input buffer 21: potential detector

22 Vbb Pump Controller 23 Ring Oscillator

24: Vbb potential pumping circuit 30: time delay circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a back bias potential generating circuit of a semiconductor memory device, and more particularly to a back bias potential generating circuit which prevents a chip from malfunctioning due to negative noise generated at an input / output pin.

The present invention relates to a back bias potential generating circuit applied to a P-type substrate. The present invention can be applied to any semiconductor memory device using a P-sub substrate even when the memory device is not a storage device.

It is applied to a well or a substrate for the purpose of separating the general circuit on the semiconductor memory device, and maintains the junction surface of the well or the substrate and the general circuit in a reverse bias state, thereby preventing the general circuit from malfunctioning. It is the role of the back bias (V _BB ) potential generating circuit.

FIG. 1 is a conventional back bias potential generating circuit diagram, which is controlled by a back bias potential level detector 11 for outputting a signal having sensed a back bias potential, and controlled by an output of the back bias potential level detector 11 at a constant period. A ring oscillator 12 for outputting a pulse signal and a back bias potential funnel circuit 13 that is operated by a pulse signal from the ring oscillator 12 to supply electric charges to a back bias voltage node V _BB . It is.

Briefly describing the operation of the circuit, the ring oscillator 12 is driven in a constant manner according to the output state of the back bias potential level detector 11 which senses the potential level of the back bias voltage node V _BB to generate a pulse signal. In response to the output pulse signal, the reverse bias potential pumping circuit 13 operates to extract electric charges from the back bias voltage node V _BB to lower the potential.

2 is a block diagram of a data output buffer and a data input buffer for explaining another problem in the prior art, wherein one input / output pad (between the output terminal N3 of the data output buffer and the input terminal N4 of the data input buffer ( (Hereinafter referred to as I / O PAD) 16 is configured.

Assuming that a negative potential is applied to the I / O PAD 16 (ie, a write operation), the output nodes N1 of the pull-up and pull-down driver driving circuits 14 and 15 are applied. Since N2 has a ground voltage Vss level, both the pull-up driver MN1 and the pull-down driver MN2 are turned off. In this state, when a -2V potential is applied to the I / O PAD 16, the voltage Vgs applied to the gate-source of the pull-up driver MN1 becomes + 2V, and the pull-down driver MN2 The Vgs potential of) also becomes + 2V. Therefore, the current I _U flowing through the pull-up driver MN1 flows from the power supply voltage Vdd to the I / O PAD 16 and the current I _d flowing through the pull-down driver MN2. ) Flows from the ground voltage Vss to the I / O PAD 16 and flows out through the external driver. In this case, the potential difference between the drain-source voltage V _{DS of} the pull-up driver MN1 is V _DD -V ( _{I / O} ), and the drain-source voltage V of the pull-down driver MN2. _Since the potential difference of _DS ) is V _SS -V ( _{I / O} ), the current I _U flowing through the pull-up driver MN1 is greater than the current I _d flowing through the fall-down driver MN2. Big. Therefore, the amount of charge injected into the substrate is increased. As the number of I / O PADs 16 increases, charge injection to the substrate increases proportionally, leading to an increase in the back bias potential level, thereby causing chip malfunction due to latch-up. do.

Accordingly, an object of the present invention is to provide a back bias potential generating circuit which prevents a chip from malfunctioning due to negative noise generated at an input / output pin.

In order to achieve the above object, in the back bias potential generating circuit of the present invention, potential sensing means for outputting a signal sensed by the potential from the input and output pins;

Pumping control means for controlling the charge pumping operation by an output signal from the potential sensing means and a substrate potential;

A ring oscillator for generating a constant pulse signal by an output signal from said back bias pump control means;

And a back bias potential pumping means for pumping charge to the input / output pins by a pulse signal from the ring oscillator.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

3 is a block diagram of a back bias potential generating circuit according to the present invention, which includes a potential detector 21 for outputting a signal sensed by an input / output pin;

A pump controller 22 for controlling the charge pumping operation by the output signal from the potential detector 21 and a ring oscillator 23 which generates a constant pulse signal by the output signal from the pump controller 22. )Wow,

A back bias potential pumping circuit 24 is provided to pump charge to the input / output pins by the pulse signal from the ring oscillator 23.

FIG. 4 is a circuit diagram of the potential detector shown in FIG. 3, which is a PMOS transistor MP1 connected between a power supply voltage Vdd and a node N5 and whose gate is connected to an input / output pin, and the node N5 and An NMOS transistor MN3 connected between a ground voltage Vss and a control signal WRAS applied to a gate, and a PMOS transistor MP2 connected between a power supply voltage and a node N6 and whose gate is connected to the node N6. ), A PMOS transistor MP3 connected between a power supply voltage and a node N7 and a gate connected to the node N6, and connected between the node N6 and a node N8, and a gate connected to the node N5. NMOS transistor (MN4) connected to the N, NMOS transistor (MN5) connected between the node (N7) and node (N8), the reference voltage (Vref) is applied to the gate, and between the node (N8) and ground voltage And an NMOS transistor MN6 connected to the node N5 and connected to a gate thereof. And a PMOS transistor MP4 connected between a power supply voltage and a node N9 and a gate connected to the node N7, and an NMOS connected between the node N9 and a ground voltage and a gate connected to the node N5. A transistor MN7 and an inverter G1 connected between the node N9 and the node N10 are provided. The control signal WRAS is a clock having a logic state during a write cycle. The control signal WRAS is logic low in a read cycle, thereby cutting off current consumption by turning off the NMOS transistor MN3. .

Looking at the operation, when the potential of the input / output pin is lowered, the potential of the node (N5) is increased, the node (N7) is increased by the operation of the current mirror composed of the PMOS transistors (MP2, MP3). do. Therefore, since the driver capability of the PMOS transistor MP4 is reduced and the potential of the node N9 is lowered, the output signal DETi output to the node N10 has a high value.

As described above, the potential detector (Fig. 4A) of the input / output pins is required as many as the number of input / output pins.

FIG. 4B is a device for adding the output signals of the potential detector of FIG. 4A. The PMOS transistor MP5 is connected between the power supply voltage and the node N11 and the control signal WRAS is applied to the gate. The node N11 and The NMOS transistor MN _N is connected between the ground voltages and to which the output signal Deti of the potential detector is applied to the gate.

While the control signal WRAS is 'low', the output signal / det_or output to the node N11 has a high value and any one of the output signals Det0 to Detn of the potential detector. Even if the value is 'high', the output signal / det_or is changed to 'low'.

FIG. 5 is a circuit diagram of the V _BB pump controller shown in FIG. 3, and is connected in series between a node N11 for inputting the output signal / det_or of the potential sensor and the node N11 and a node N12. Inverters G2 to G5 and NAND gates G6 for outputting the NAND-operated values to the node N13 as the inputs of the nodes N11 and N12. And a PMOS transistor MP6 connected between the power supply voltage and the node N14 and to which an inverted signal of the control signal WRAS is applied to the gate, and connected in series between the node N14 and the ground voltage. PMOS transistors MP7 to MP9 to which a potential Vbb is commonly applied, a PMOS transistor MP10 connected between a power supply voltage and a node N15, and a gate thereof connected to the node N15, and the node N15. And a PMOS transistor MP11 connected between the node N16 and a gate connected to the node N14, and an NMOS transistor connected between the node N16 and the node N17 and a gate connected to the node N14. An NMOS transistor MN11 connected between the node M17 and the node N17 and the ground voltage, and having a gate connected to the node N17, is provided. In addition, an inverter G9 connected between the node N16 and the node N18, and a NOR gate for outputting the NOR operation value to the node N19 by inputting the node N13 and the node N18 to the node N19 ( G7).

In operation, when the control signal WRAS is enabled high, the PMOS transistor MP6 is turned on to supply a power potential to the node N14. The potential of the node N14 is determined by the potential level of the substrate potential Vbb applied to the gates of the PMOS transistors MP7 to MP9. If the substrate potential Vbb is higher than the threshold value, the node N14 has a high value, so the NMOS transistors MN10 and MN11 are driven to bring the potential of the node N16 low and the node ( Make the potential of N18) high. Here, referring to the operation timing diagram illustrated in FIG. 6, the output signal / OSCE output from the node N19 has a low output signal / DET_or of the potential detector input to the node N11. Enabled or maintained low when the signal of the node N18 is enabled high. The time delay circuit 30 composed of the inverters G2 to G5 extends the disable time of the input signal det_or, and corresponds to the region? T shown in the timing diagram of FIG.

FIG. 7 is a circuit diagram of the ring oscillator shown in FIG. 3, which shows a ring oscillator conventionally used for operating the Vbb pumping circuit 24. As shown in FIG.

While the output signal (/ osce) from the Vbb pump controller 22 is enabled low, the output signals (BB, / BB) of the ring oscillator are toggled to different polarities so that the Vbb potential pumping circuit (24) Will be driven.

8 is a circuit diagram of the Vdd pumping circuit shown in FIG. 3, which is a conventional Vbb pumping circuit diagram.

Referring to the operation of the Vbb pumping circuit, when the output signal BB of the ring oscillator goes from high to low and the output signal / BB goes from low to high, the NMOS transistor MN12 is turned on and the NMOS transistor is turned on. The MN13 and the PMOS transistor MP16 are turned off. Therefore, as the output signal BB goes from high to low, the potential of the node N20 is lowered to a large negative potential at the ground potential, and the substrate potential Vbb becomes the node N20 through the NMOS transistor MN12. Is discharged). When the output signal BB goes from low to high and the output signal / BB goes from high to low, its operation is reversed.

As described above, if the back bias potential generating circuit of the present invention is implemented in the semiconductor memory device, the chip operates stably even when a negative potential is applied to the data input / output pins, thereby improving reliability. have.

Claims (3)

A back bias potential generating circuit of a semiconductor memory device, comprising: a potential sensing means for outputting a signal sensed by an input / output pin and a charge pumping operation by an output signal from the potential sensing means and a substrate potential; A pump for controlling charge to the input / output pins by a pumping control means, a ring oscillator generating a constant pulse signal by an output signal from the pumping control means, and a pulse signal from the ring oscillator Back bias potential generating circuit comprising a bias potential pumping means. 2. The PMOS transistor (MP1) of claim 1, wherein the potential sensing means is connected between a power supply voltage (Vdd) and a node (N5) and whose gate is connected to an input / output pin. A NMOS transistor MN3 connected between Vss and a control signal WRAS applied to a gate, a PMOS transistor MP2 connected between a power supply voltage and a node N6 and having a gate connected to the node N6; A PMOS transistor MP3 connected between a power supply voltage and node N7 and a gate connected to node N6, and connected between node N6 and node N8, and a gate connected to node N5. An NMOS transistor MN4, connected between the node N7 and the node N8, and connected between an NMOS transistor MN5 to which a reference voltage Vref is applied to a gate, and between the node N8 and a ground voltage. A gate is connected between the NMOS transistor MN6 connected to the node N5, the power supply voltage, and the node N9. A PMOS transistor MP4 having a gate connected to the node N7, a node connected to the node N9 and a ground voltage, and a NMOS transistor MN7 having a gate connected to the node N5, and the node N9. And an inverter G1 connected between the node N10, a PMOS transistor MP5 connected between the power supply voltage and the node N11 and to which a control signal WRAS is applied to a gate, and the node N11 and ground. And an NMOS transistor (MN _N ) connected between voltages and to which an output signal (Deti) of the potential detector is applied to a gate. 2. The pump according to claim 1, wherein the pumping control means comprises: a node (N11) for inputting an output signal (/ det_or) of the potential sensing means, and an inverter (G2) connected in series between the node (N11) and a node (N12). To G5), a NAND gate G6 for outputting the NAND operation value to the node N13 by inputting the nodes N11 and N12 to the node N13, a power supply voltage and a node N14, and a control signal to the gate. PMOS transistor MP6 to which the inverted signal of WRAS is applied, and PMOS transistors MP7 to MP9 connected in series between the node N14 and the ground voltage, and to which the substrate potential Vbb is commonly applied to each gate. And a PMOS transistor MP10 connected between a power supply voltage and a node N15 and a gate connected to the node N15, and connected between the node N15 and a node N16, and a gate connected to the node N14. A PMOS transistor MP11 connected to the node N16 and a node N17, the gate of which is connected to the NMOS transistor MN10 connected to node N14, NMOS transistor MN11 connected between the node N17 and the ground voltage and whose gate is connected to node N17, and the node N16 and node N18. A back bias comprising: an inverter G9 connected between the NOR gate G7 and a node N13, which is connected to the node N13 and the node N18 and outputs a NOR operation value to the node N19; Potential generating circuit.