KR19980060728A - Gate electrode formation method of semiconductor device - Google Patents
Gate electrode formation method of semiconductor device Download PDFInfo
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- KR19980060728A KR19980060728A KR1019960080094A KR19960080094A KR19980060728A KR 19980060728 A KR19980060728 A KR 19980060728A KR 1019960080094 A KR1019960080094 A KR 1019960080094A KR 19960080094 A KR19960080094 A KR 19960080094A KR 19980060728 A KR19980060728 A KR 19980060728A
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- gate electrode
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 230000003647 oxidation Effects 0.000 claims abstract description 26
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 26
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 11
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 238000001020 plasma etching Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 7
- 238000005546 reactive sputtering Methods 0.000 claims description 7
- 239000012298 atmosphere Substances 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 229910004200 TaSiN Inorganic materials 0.000 claims description 4
- 229910008482 TiSiN Inorganic materials 0.000 claims description 3
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 claims description 3
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910000487 osmium oxide Inorganic materials 0.000 claims description 3
- JIWAALDUIFCBLV-UHFFFAOYSA-N oxoosmium Chemical compound [Os]=O JIWAALDUIFCBLV-UHFFFAOYSA-N 0.000 claims description 3
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- WXBOMIKEWRRKBB-UHFFFAOYSA-N rhenium(iv) oxide Chemical compound O=[Re]=O WXBOMIKEWRRKBB-UHFFFAOYSA-N 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 6
- 238000001312 dry etching Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 229910021332 silicide Inorganic materials 0.000 description 7
- 229910021341 titanium silicide Inorganic materials 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 229910008486 TiSix Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910003449 rhenium oxide Inorganic materials 0.000 description 2
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910052762 osmium Inorganic materials 0.000 description 1
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 description 1
- DYIZHKNUQPHNJY-UHFFFAOYSA-N oxorhenium Chemical compound [Re]=O DYIZHKNUQPHNJY-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
게이트 도전층의 산화를 방지하고 게이트 산화막의 손상을 회복시킬 수 있는 반도체장치의 게이트전극 형성방법에 관하여 개시하고 있다. 이를 위하여 본 발명은 반도체 기판 상에 게이트 산화막을 형성하는 단계와, 상기 게이트 산화막 상에 제1 도전층을 형성하는 단계와, 상기 제1 도전층의 상부에 장벽층을 형성하는 단계와, 상기 장벽층의 상부에 제2 도전층을 형성하는 단계와, 상기 제2 도전층의 상부에 제1 절연층 패턴을 형성하는 단계와, 상기 제1 절연층을 식각마스크로 패터닝을 진행하여 게이트전극을 형성하는 단계와, 상기 게이트전극이 패터닝된 결과물 상에 산화공정을 진행하여 제2 절연층을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체장치의 게이트전극 형성방법을 제공한다. 따라서, 게이트전극의 도전물질로서 내산화성이 강한 산화금속을 사용함으로써 게이트전극의 형태 불량 및 게이트전극의 면저항의 증가를 방지할 수 있다.A method of forming a gate electrode of a semiconductor device capable of preventing oxidation of the gate conductive layer and restoring damage to the gate oxide film is disclosed. To this end, the present invention comprises the steps of forming a gate oxide film on the semiconductor substrate, forming a first conductive layer on the gate oxide film, forming a barrier layer on top of the first conductive layer, the barrier Forming a second conductive layer over the layer, forming a first insulating layer pattern over the second conductive layer, and patterning the first insulating layer with an etch mask to form a gate electrode And forming a second insulating layer by performing an oxidation process on the resultant patterned gate electrode. Therefore, by using a metal oxide having strong oxidation resistance as the conductive material of the gate electrode, it is possible to prevent a shape defect of the gate electrode and an increase in the sheet resistance of the gate electrode.
Description
본 발명은 반도체장치의 제조공정에 관한 것으로, 특히 게이트 도전층의 산화를 방지하고 게이트 산화막의 손상을 회복시킬 수 있는 반도체장치의 게이트전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to a method of forming a gate electrode of a semiconductor device capable of preventing oxidation of a gate conductive layer and restoring damage to a gate oxide film.
반도체장치의 집적도가 증가함에 따라 저저항 배선의 중요성이 증대되고 있으며, 최근에는 폴리실리콘막을 대체하는 저저항 배선 구조로서 폴리실리콘막 상에 고융점 금속 실리사이드(Refractory Metal Silicide)막, 특히 텅스텐 실리사이드, 티타늄 실리사이드, 코발트 실리사이드, 몰리브덴 실리사이드(MoSi2) 및 탄탈륨 실리사이드 등을 적층시킨 폴리사이드 구조를 널리 사용하고 있다. 이에 따라, 반도체장치의 게이트전극도 종래에는 폴리실리콘에 인(Phosphorus)을 도핑(doping)하여 저항을 낮춘 것을 사용하였다. 하지만, 최근에는 소자의 고집적화에 따라 한층 더 낮은 저항을 갖는 게이트 도전층을 요구하게 되어 폴리실리콘 막위에 텅스텐 실리사이드(WSi) 또는 티타늄 실리사이드(TiSi)등을 적층시킨 이중구조의 폴리사이드가 그 대체 물질로 사용되고 있다. 이중에서 특히, 티타늄 실리사이드는 텅스텐 실리사이드(WSi)보다 낮은 저항을 갖는 배선 물질로서 널리 사용되어 왔으며, 질화 처리(Nitridation)로 확산 장벽층을 형성시켜 티타늄 실리사이드와 알루미늄 금속 사이의 접촉을 매우 안정되게 할 수 있는 장점으로 인해 주목을 받고 있다.As the degree of integration of semiconductor devices increases, the importance of low-resistance wiring is increasing, and recently, as a low-resistance wiring structure replacing the polysilicon film, a high melting point metal silicide film, particularly tungsten silicide, Polysilicon structures in which titanium silicide, cobalt silicide, molybdenum silicide (MoSi2) and tantalum silicide are laminated are widely used. Accordingly, the gate electrode of the semiconductor device is also conventionally used to lower the resistance by doping (Phosphorus) to the polysilicon. However, in recent years, as the device is highly integrated, a gate conductive layer having a lower resistance is required, and a polystructure having a double structure in which tungsten silicide (WSi) or titanium silicide (TiSi) is laminated on a polysilicon film is replaced. Is being used. In particular, titanium silicide has been widely used as a wiring material having a lower resistance than tungsten silicide (WSi), and nitriding forms a diffusion barrier layer to make the contact between titanium silicide and aluminum metal very stable. It is attracting attention because of its advantages.
반도체 제조공정에서 티타늄 실리사이드를 갖는 게이트전극의 제조공정은 통상, 플라즈마 식각이나 반응성 이온 식각(RIE: Reactive Ion Etching, 이하 'RIE'라 칭함) 등의 건식식각 방법을 이용한다. 이러한 건식식각 방법으로 게이트전극을 식각하면 하부의 게이트 산화막의 가장자리가 손상을 받게 되는 문제점이 있다. 이러한 게이트 산화막의 가장자리의 손상은 게이트 산화막의 절연 파괴 전압에 영향을 주어서 소자의 신뢰성을 저해하는 요소로 작용하게 된다. 따라서, 게이트전극의 형성 후에 게이트 산화막의 손상을 없애기 위한 후속 공정이 필수적으로 수행되어야 한다. 이러한 후속 공정으로 일반적으로 사용되는 방법은 게이트전극을 형성한 후, 추가적으로 산화공정을 실시하여 게이트 산화막의 가장자리에 손상된 부분을 회복시켜 주는 방법이 사용되고 있다.In the semiconductor manufacturing process, a gate electrode having titanium silicide is usually manufactured by dry etching such as plasma etching or reactive ion etching (RIE). When the gate electrode is etched by the dry etching method, the edge of the lower gate oxide layer may be damaged. The damage of the edge of the gate oxide film affects the dielectric breakdown voltage of the gate oxide film, thereby acting as a factor that hinders the reliability of the device. Therefore, a subsequent process for eliminating damage to the gate oxide film after the formation of the gate electrode must be essentially performed. As a method generally used in such a subsequent process, after the gate electrode is formed, an additional oxidation process is performed to recover a damaged portion at the edge of the gate oxide film.
도 1 내지 도 3은 종래기술에 의한 반도체장치의 게이트전극 형성방법을 설명하기 위하여 공정의 순서에 따라 도시한 단면도들이다.1 to 3 are cross-sectional views in order of a process for explaining a gate electrode forming method of a semiconductor device according to the prior art.
도 1을 참조하면, 소자 분리 공정에 의한 필드 산화막(도시되지 않음)이 형성된 반도체 기판(1)의 전면에 게이트 산화막(3)과, 폴리실리콘으로 형성된 제1 도전층(5)과, 티타늄 실리사이드와 같은 내산화성이 약한 물질로 형성된 제2 도전층(7) 및 후속되는 식각공정에서 식각마스크로 사용될 제1 절연층(9)을 순차적으로 적층한다.Referring to FIG. 1, a gate oxide film 3 is formed on the entire surface of a semiconductor substrate 1 on which a field oxide film (not shown) is formed by an element isolation process, a first conductive layer 5 formed of polysilicon, and titanium silicide. The second conductive layer 7 formed of a material having a weak oxidation resistance, such as, and the first insulating layer 9 to be used as an etching mask in the subsequent etching process are sequentially stacked.
도 2를 참조하면, 상기 게이트 산화막(3), 제1 도전층(5), 제2 도전층(7) 및 제1 절연층(9)이 순차적으로 적층된 반도체 기판의 전면에 플라즈마 또는 RIE에 의한 이방성 건식식각 공정을 진행하여 게이트전극을 패터닝한다. 이때, 상술한 바와 같이 건식식각 진행시에 게이트 산화막의 가장자리 부분(11)이 손상을 받게 된다.Referring to FIG. 2, the gate oxide film 3, the first conductive layer 5, the second conductive layer 7, and the first insulating layer 9 are sequentially stacked on a plasma or RIE on a front surface of the semiconductor substrate. The gate electrode is patterned by performing an anisotropic dry etching process. At this time, as described above, the edge portion 11 of the gate oxide film is damaged during the dry etching process.
도 3을 참조하면, 상기 게이트 산화막의 가장자리 부분(11)에 손상을 회복시키기 위한 산화공정을 반도체 기판의 전면에 진행하여 손상된 게이트 산화막(3)의 가장자리 부분(9)을 원상 회복시키는 제2 절연층(13)을 형성한다. 하지만, 상기 제2 도전층이 내산화성에 약하고 쉽게 산화가 되는 금속물질이기 때문에 제2 도전층의 양측벽(15)이 과도하게 산화되어 게이트전극의 형태불량 및 면저항이 증가하는 문제를 가져오고 있다.Referring to FIG. 3, a second insulation for restoring the edge portion 9 of the damaged gate oxide film 3 by performing an oxidation process for recovering damage to the edge portion 11 of the gate oxide film on the entire surface of the semiconductor substrate. Form layer 13. However, since the second conductive layer is a metal material that is weak in oxidation resistance and easily oxidized, both side walls 15 of the second conductive layer are excessively oxidized, which causes a problem of increase in shape defects and sheet resistance of the gate electrode. .
상술한 종래기술에 의한 반도체장치의 게이트전극 형성방법의 문제점은, 제2 도전층인 티타늄 실리사이드가 내산화성에 약한 금속 물질이기 때문에 게이트 산화막(3)의 가장자리(11)에 있는 손상을 회복시키기 위한 산화공정 중에 티타늄 실리사이드 자체가 빠른 속도로 산화됨으로써 게이트전극의 형태 불량 및 게이트도전층의 저항이 크게 증가하여 소자의 신뢰도가 떨어지는 문제가 있다.The problem of the gate electrode forming method of the semiconductor device according to the prior art described above is to recover damage at the edge 11 of the gate oxide film 3 because titanium silicide as the second conductive layer is a metal material that is poor in oxidation resistance. Titanium silicide itself is oxidized at a high speed during the oxidation process, resulting in a problem of poor shape of the gate electrode and resistance of the gate conductive layer.
본 발명이 이루고자 하는 기술적 과제는 게이트전극의 도전물질로서 내산화성이 강한 산화금속을 사용하여 게이트전극의 형태 불량 및 게이트전극의 면저항의 증가를 방지할 수 있는 반도체장치의 게이트전극 형성방법을 제공하는데 있다.The technical problem to be achieved by the present invention is to provide a gate electrode forming method of a semiconductor device that can prevent the shape defect of the gate electrode and the increase in the sheet resistance of the gate electrode by using a metal oxide having a strong oxidation resistance as a conductive material of the gate electrode. have.
도 1 내지 도 3은 종래기술에 의한 반도체장치의 게이트전극 형성방법을 설명하기 위하여 도시한 단면도들이다.1 to 3 are cross-sectional views illustrating a gate electrode forming method of a semiconductor device according to the prior art.
도 4 내지 도 6은 본 발명의 따른 반도체장치의 게이트전극 형성방법을 설명하기 위하여 도시한 단면도들이다.4 to 6 are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device according to the present invention.
*도면의 주요 부호에 대한 설명** Description of Major Symbols in Drawings *
100: 반도체 기판,102: 게이트 산화막,100: semiconductor substrate, 102: gate oxide film,
104: 제1 도전층,106: 장벽층,104: first conductive layer, 106: barrier layer,
108: 제2 도전층,110: 제1 절연층,108: second conductive layer, 110: first insulating layer,
112: 게이트 산화막의 가장자리,114: 제2 절연층.112: edge of the gate oxide film, 114: second insulating layer.
상기의 기술적 과제를 달성하기 위하여 본 발명은, 반도체 기판 상에 게이트 산화막을 형성하는 단계와, 상기 게이트 산화막 상에 제1 도전층을 형성하는 단계와, 상기 제1 도전층의 상부에 장벽층을 형성하는 단계와, 상기 장벽층의 상부에 제2 도전층을 형성하는 단계와, 상기 제2 도전층의 상부에 제1 절연층 패턴을 형성하는 단계와, 상기 제1 절연층을 식각마스크로 패터닝을 진행하여 게이트전극을 형성하는 단계와, 상기 게이트전극이 패터닝된 결과물 상에 산화공정을 진행하여 제2 절연층을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체장치의 게이트전극 형성방법을 제공한다.In order to achieve the above technical problem, the present invention, forming a gate oxide film on a semiconductor substrate, forming a first conductive layer on the gate oxide film, a barrier layer on top of the first conductive layer Forming a second conductive layer on the barrier layer, forming a first insulating layer pattern on the second conductive layer, and patterning the first insulating layer as an etch mask. Forming a gate electrode, and forming a second insulating layer by performing an oxidation process on the resultant patterned gate electrode, thereby forming a gate electrode of the semiconductor device. .
본 발명의 바람직한 실시예에 의하면, 상기 장벽층은 비정질층으로서 TiSiN 또는 TaSiN중에 하나인 물질을 사용하여 형성하고, 형성하는 방법은 질소의 분위기에서 반응성 스퍼터링(Reactive sputtering) 방식으로 형성하는 것이 적합하다.According to a preferred embodiment of the present invention, the barrier layer is formed using a material of one of TiSiN or TaSiN as an amorphous layer, the forming method is preferably formed by a reactive sputtering (Reactive sputtering) method in the atmosphere of nitrogen .
본 발명의 바람직한 실시예에 의하면, 상기 제2 도전층은 내열성 및 내산화성에 강한 산화금속(metal oxide) 도전체로서 산화루테늄(RuO2), 산화이리듐(IrO2), 산화레늄(ReO2) 및 산화오스뮴(OsO2) 중에서 선택된 하나를 사용하고, 형성방법은 산소의 분위기에서 반응성 스퍼터링 방식으로 형성하는 것이 적합하다.According to a preferred embodiment of the present invention, the second conductive layer is a metal oxide conductor resistant to heat resistance and oxidation resistance, such as ruthenium oxide (RuO 2 ), iridium oxide (IrO 2 ), and rhenium oxide (ReO 2 ). And osmium oxide (OsO 2 ), and the formation method is preferably formed by reactive sputtering in an oxygen atmosphere.
바람직하게는, 상기 제1 절연층은 패터닝을 위한 식각마스크로서 질화막(SiN) 또는 산화막을 사용하는 것이 적합하다.Preferably, the first insulating layer is suitable to use a nitride film (SiN) or an oxide film as an etching mask for patterning.
본 발명의 바람직한 실시예에 의하면, 상기 게이트전극을 패터닝하는 방법은 플라즈마 또는 반응성 이온 식각(RIE) 방식을 사용하여 이방성 식각을 수행하는 것이 적합하다.According to a preferred embodiment of the present invention, the method for patterning the gate electrode is suitable to perform anisotropic etching using a plasma or reactive ion etching (RIE) method.
본 발명에 따르면, 게이트전극의 도전물질로서 내산화성이 강한 산화금속을 사용하여 게이트전극의 형태 불량 및 게이트전극의 면저항의 증가를 방지할수 있다.According to the present invention, it is possible to prevent the shape defect of the gate electrode and the increase in the sheet resistance of the gate electrode by using a metal oxide having strong oxidation resistance as the conductive material of the gate electrode.
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 4 내지 도 6은 본 발명의 따른 반도체장치의 게이트전극 형성방법을 설명하기 위하여 도시한 단면도들이다.4 to 6 are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device according to the present invention.
도 4는 게이트전극을 형성하기 위한 물질층을 형성하는 방법을 나타낸 단면도이다. 상세히 설명하면, 소자 분리 공정에 의하여 활성영역이 정의된 반도체 기판(100)의 전면에 게이트 산화막(102), 불순물이 도핑되어 도전성을 갖는 폴리실리콘으로 구성된 제1 도전층(104)을 순차적으로 적층한다. 이어서, 상기 제1 도전층(104)이 적층된 반도체 기판의 전면에 TiSiN, TiSix 및 TaSix등을 타겟(Target)을 이용하여 질소 분위기에서 반응성 스퍼터링(reactive sputtering)을 실시하여 TaSiN 또는 TaSiN과 같은 비정질층으로 구성된 장벽층(106)을 형성한다.4 is a cross-sectional view illustrating a method of forming a material layer for forming a gate electrode. In detail, the gate oxide film 102 and the first conductive layer 104 made of polysilicon having dopants doped with impurities are sequentially stacked on the entire surface of the semiconductor substrate 100 in which the active region is defined by the device isolation process. do. Subsequently, TiSiN, TiSix, TaSix, etc. are applied to the entire surface of the semiconductor substrate on which the first conductive layer 104 is stacked using reactive sputtering in a nitrogen atmosphere in an amorphous atmosphere such as TaSiN or TaSiN. A barrier layer 106 composed of layers is formed.
여기서, 상기 장벽층(106)의 역할은, ①내열성 및 내산화성이 우수하여 후속되는 산화공정에서 산소가 상부의 제2 도전층(108)으로 침투하는 것을 방지하며, ②고온 열처리시 폴리실리콘으로 구성된 제1 도전층(104)과 제2 도전층(108)사이에 면저항의 증가를 초래하는 산화막(SiO2)이 형성되는 것을 방지하며, ③후속공정에서 장벽층(106)의 상부에 형성되는 제2 도전층(108)으로부터 루테늄(Ru), 이리듐(Ir), 레늄(Re) 및 오스뮴(Os) 등의 금속 이온이 게이트 산화막(102)에 침투하여 트랜지스터의 특성을 저해하는 문제점을 방지하는 기능을 수행한다.Here, the role of the barrier layer 106, ① excellent heat resistance and oxidation resistance to prevent oxygen from penetrating into the upper second conductive layer 108 in the subsequent oxidation process, ② as a polysilicon during high temperature heat treatment An oxide film (SiO 2 ) that prevents an increase in sheet resistance is formed between the first conductive layer 104 and the second conductive layer 108, which is formed on the barrier layer 106 in a subsequent process. Metal ions such as ruthenium (Ru), iridium (Ir), rhenium (Re), and osmium (Os) from the second conductive layer 108 penetrate the gate oxide layer 102 to prevent the problem of impairing the transistor characteristics. Perform the function.
연속해서, 상기 장벽층(106)이 형성된 결과물의 전면에 제2 도전층(108)인 산화금속(metal oxide) 도전체로서 산화루테늄(RuO2), 산화이리듐(IrO2), 산화레늄(ReO2) 및 산화오스뮴(OsO2) 중에서 선택된 하나를 산소의 분위기에서 반응성 스퍼터링 방식으로 형성한다. 이러한 산화금속 도전체는 내열성 및 내산화성에 강한 특성을 갖는다. 종래에는 산화금속 대신에 산소와 쉽게 반응하여 산화되는 금속 실리사이드를 사용함으로써 게이트전극의 형태가 불량해지거나 면저항이 높아지는 문제점이 발생하였으나, 본 발명에서는 산화금속을 게이트 전극의 제2 도전층(108)으로 사용함으로써 후속되는 산화공정에서 산소와의 반응으로 인한 문제점을 해결할 수 있다. 연속해서, 상기 제2 도전층(108)의 상부에 질화막 또는 산화막 중에 하나를 사용하여 제1 절연층(110)을 형성한다.Subsequently, ruthenium oxide (RuO 2 ), iridium oxide (IrO 2 ), and rhenium oxide (ReO) as a metal oxide conductor, which is the second conductive layer 108, on the entire surface of the resultant layer on which the barrier layer 106 is formed. 2 ) and osmium oxide (OsO 2 ) are formed by reactive sputtering in an atmosphere of oxygen. Such metal oxide conductors have characteristics that are strong in heat resistance and oxidation resistance. Conventionally, the use of metal silicides that easily react with oxygen to oxidize in place of metal oxides causes a problem in that the shape of the gate electrode is poor or the sheet resistance is increased. However, in the present invention, the metal oxide is used as the second conductive layer 108 of the gate electrode. By using it as a problem can be solved by the reaction with oxygen in the subsequent oxidation process. Subsequently, the first insulating layer 110 is formed on the second conductive layer 108 by using either a nitride film or an oxide film.
도 5를 참조하면, 상기 게이트전극의 물질층들이 적층된 결과물 상에 플라즈마 또는 반응성 이온 식각(RIE)과 같은 이방성의 건식식각을 진행한다. 이때, 최상부에 위치한 제1 절연층(110)이 식각마스크로 활용된다. 상기 건식식각의 결과물로, 제1 절연층(110), 제2 도전층(108), 장벽층(106), 제1 도전층(104), 게이트 산화막(102)으로 구성된 게이트전극이 패터닝 되게 된다. 하지만 게이트 산화막(102)의 가장자리 부분(112)에는 건식식각 도중에 양측벽이 손상을 받게 되는 문제점은 그대로 존재한다.Referring to FIG. 5, anisotropic dry etching such as plasma or reactive ion etching (RIE) is performed on the resultant material layer of the gate electrode. In this case, the first insulating layer 110 located at the top is used as an etching mask. As a result of the dry etching, the gate electrode composed of the first insulating layer 110, the second conductive layer 108, the barrier layer 106, the first conductive layer 104, and the gate oxide layer 102 is patterned. . However, the problem that both side walls are damaged during dry etching remains at the edge 112 of the gate oxide film 102.
도 6을 참조하면, 상기 게이트전극이 패터닝된 결과물의 전면에 손상을 받은 게이트 산화막의 가장자리 부분(112)을 회복시키기 위한 산화공정을 진행한다. 이러한 산화공정에 의하여 형성된 제2 절연층(114)은 제1 절연층(110), 제2 도전층(108) 및 장벽층(16)과는 크게 산화가 일어나지 않으면서, 손상된 게이트 산화막의 가장자리 부분(112)과 제1 도전층 및 게이트 전극 이외의 게이트 산화막(102)의 상부를 덮는 구조로 형성되게 된다. 여기서 제2 도전층은 이미 산화가 되어 있는 산화금속으로 구성되었기 때문에 과도한 산화로 인한 면저항의 증가 및 게이트 전극의 형태 불량 문제가 더 이상 일어나지 않는다.Referring to FIG. 6, an oxidation process is performed to recover the edge portion 112 of the gate oxide film that is damaged on the entire surface of the resultant patterned gate electrode. The second insulating layer 114 formed by the oxidation process does not significantly oxidize with the first insulating layer 110, the second conductive layer 108, and the barrier layer 16, and the edge portion of the damaged gate oxide film is formed. The upper portion of the gate oxide film 102 other than the 112 and the first conductive layer and the gate electrode is formed. Since the second conductive layer is made of a metal oxide which is already oxidized, an increase in sheet resistance due to excessive oxidation and a shape defect of the gate electrode no longer occur.
결국, 종래의 금속 실리사이드를 대신한 도전물질인 TiSix와 RuO2는, 비저항이 25μΩ/㎝와 50μΩ/㎝으로 금속 실리사이드의 비저항보다는 다소 높은 편이지만, 산화공정에서 금속 실리사이드의 과도한 산화로 인해서 유발되는 면저항의 증가보다는 훨씬 작은 영향을 게이트전극에 끼치게 된다.As a result, TiSix and RuO 2, which are conductive materials instead of the conventional metal silicides, have a specific resistance of 25 µΩ / cm and 50 µΩ / cm, which are somewhat higher than those of metal silicide, but are caused by excessive oxidation of the metal silicide in the oxidation process. The influence on the gate electrode is much smaller than the increase in sheet resistance.
본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함은 명백하다.The present invention is not limited to the above-described embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit to which the present invention belongs.
따라서, 상술한 본 발명에 따르면, 게이트전극의 도전물질로서 내산화성이 강한 산화금속을 사용함으로써 게이트전극의 형태 불량 및 게이트전극의 면저항의 증가를 방지할 수 있는 반도체장치의 게이트전극 형성방법을 구현할 수 있다.Accordingly, according to the present invention described above, a method of forming a gate electrode of a semiconductor device capable of preventing a shape defect of a gate electrode and an increase in sheet resistance of the gate electrode by using a metal oxide having strong oxidation resistance as a conductive material of the gate electrode can be realized. Can be.
Claims (7)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960080094A KR100219515B1 (en) | 1996-12-31 | 1996-12-31 | Method of fabricating a gate electrode in semiconductor device |
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| KR1019960080094A KR100219515B1 (en) | 1996-12-31 | 1996-12-31 | Method of fabricating a gate electrode in semiconductor device |
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| KR19980060728A true KR19980060728A (en) | 1998-10-07 |
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| US11723189B2 (en) | 2020-12-01 | 2023-08-08 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11723189B2 (en) | 2020-12-01 | 2023-08-08 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
| US12016175B2 (en) | 2020-12-01 | 2024-06-18 | Samsung Electronics Co., Ltd. | Semiconductor device |
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