KR19980060007A - Power consumption reduction circuit of liquid crystal display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power consumption reduction circuit of a liquid crystal display device, and compares a buffer for temporarily storing RGB data input from a graphics card with the nth and n-1th RGB data stored in the buffer, and the two data are the same. In this case, a logic gate that emits a signal, a counter that counts an output signal of the logic gate, and outputs a signal when a predetermined number of signals are counted, and a clock of 65 MHz and 32.5 MHz data is received as a frequency selection input. It includes an interface circuit for performing an interface by selecting one of the frequencies, the power consumption reduction circuit for reducing power consumption by reducing and adjusting the data clock in the still image when implementing the display using digital data in the liquid crystal display device It is about.

Description

Power consumption reduction circuit of liquid crystal display

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power consumption reduction circuit of a liquid crystal display, and more particularly, a power consumption reduction circuit for reducing power consumption by reducing and adjusting a data clock in a still image when implementing a display using digital data in a liquid crystal display. It is about.

The thin film transistor liquid crystal display (TFT LCD) is a high resolution display device driven at a high frequency of 65 MHz (XGA level). This means that the data clock for displaying the image 60 times per second becomes 65 MHz.

However, these high frequency data clocks have been a cause of increasing the total power consumption of the liquid crystal display.

Accordingly, an object of the present invention is to solve the above problems, and provides a power consumption reduction circuit for reducing power consumption by reducing and adjusting the data clock in still images when implementing a display using digital data in a liquid crystal display device. It is in

1 is a block diagram of a power consumption reduction circuit according to a first embodiment of the present invention;

2 is a block diagram of a power consumption reduction circuit according to a second embodiment of this invention.

The present invention for achieving the above object is a buffer for temporarily storing the RGB data input from the graphics card; A logic gate comparing the nth and n-1th RGB data stored in the buffer and outputting a signal when the two data are the same; A counter for counting an output signal of the logic gate and for outputting a signal when a predetermined number of signals are counted; And an interface circuit for receiving an output signal of the counter as a frequency selection input and selecting one of a data clock frequency of 65 MHz and 32.5 MHz to perform an interface.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention in detail.

In the power consumption reduction circuit according to the first embodiment of the present invention shown in FIG. 1, first, the buffer 10 temporarily stores RGB data input from the graphics card. The logic gate 20 compares the nth and n-1th RGB data (RGB_data (n), RGB_data (n-1)) stored in the buffer 10 and emits a signal when the two data are the same.

The counter 30 that counts the output signal of the logic gate 20 emits a signal fs when a predetermined number of signals are counted.

Finally, the interface circuit 40 receives the output signal fs of the counter 30 as a frequency selection input, and selects one of 65 MHz and a data clock frequency of 32.5 MHz to perform an interface.

When a display using digital data is implemented in a liquid crystal display device, the user does not feel any inconvenience when the still image is displayed only 30 times per second.

And if the image display is reduced from 60 to 30 times in one second, the data clock can be reduced from 65 MHz to 32.5 MHz.

Therefore, the power consumption reduction circuit according to the embodiment of the present invention reduces power consumption by reducing and adjusting the data clock in the still image when implementing a display using RGB data.

In order to implement this, 6 bits x 3 RGB data are continuously stored in the buffer 10 shown in FIG. 1, and the n-th and n-th data (RGB_data (n), RGB_data ( n-1)) is compared and a signal is output when the two data are the same.

This output signal is counted by the counter 30. When the predetermined number of signals is counted, it is recognized that it is a still image, and the frequency selection signal fs is output to the interface circuit 40 so that the data clock frequency changes from 65 MHz to 32.5 MHz.

In the case of FIG. 2, the output of the counter 30 becomes an input signal of the graphics card 5 so that the data clock frequency is changed by adjusting the register value of the graphics card 5.

Therefore, the effect of the power consumption reduction circuit according to the embodiment of the present invention is that power consumption can be reduced by reducing and adjusting the data clock frequency in the still image.

Claims (1)

A buffer for temporarily storing RGB data input from the graphics card, and a logic gate comparing the nth and n-1th RGB data stored in the buffer and outputting a signal when the two data are the same; A counter for counting an output signal of the logic gate and for outputting a signal when a predetermined number of signals are counted; And an interface circuit which receives the output signal of the counter as a frequency selection input and selects one of clock frequencies of 65 MHz and 32.5 MHz to perform an interface.