KR100469350B1 - Timing controller of liquid crystal display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing controller for liquid crystal display that can effectively reduce electromagnetic interference (EMI), and evenly inputs image data of red (R), green (G), and blue (B). And a liquid crystal display timing controller for dividing the odd data into data and outputting a signal for driving the data to the data driving circuit. The red, green, and blue data used in the previous frame are divided into even and odd data. Each of the first to sixth memory units, each of the seventh to twelfth memory units storing the red, green, and blue data to be used in the current frame in even and odd numbers, and the data driving in the current frame. When outputting the data to the circuit unit, the data stored in the first to sixth memory units and the seventh to twelfth memory units are compared with each other for data transitions between red, green, and blue data. It characterized by including the first to sixth comparator for outputting data.

Description

Timing controller for liquid crystal display {TIMING CONTROLLER OF LIQUID CRYSTAL DISPLAY}

The present invention relates to a timing controller for a liquid crystal display, and more particularly to a timing controller for a liquid crystal display that can effectively reduce electromagnetic interference (Electro Magnetic Interference).

In the case of displaying a screen in a display device, especially a liquid crystal display (LCD), the electromagnetic radiation amount is limited as a regulation related to EMI to eliminate electrical interference between systems.

Since the electromagnetic wave appears larger as the potential of the transmitted data signal is higher, the potential of the data signal must be lowered to reduce the radiation amount of the electromagnetic wave.

In particular, in recent years, as liquid crystal displays increasingly require larger sizes and higher resolutions, the amount of data signals has increased, and since the operating frequency has been increased to process many data signals, radiation doses of electromagnetic waves have increased. In addition, the main part of the radiation of the electromagnetic waves is the interface (Interface) between the system, the main integrated circuit (IC) and the connection portion of the integrated circuit.

Hereinafter, a block diagram of a general configuration of a conventional liquid crystal display device will be described.

As shown in FIG. 1, a low voltage differential signaling (LVDS) 10 that receives image data input to an LCD module and outputs a data enable signal, a vertical horizontal synchronization signal, and a system clock, and the LVDS 10. A timing controller 13 and a timing controller 13 for outputting signals required for data driving and gate driving of the LCD module by a data enable signal, a horizontal vertical synchronization signal, and a system clock outputted from the The data driver 18 driving the pixels of the LCD panel 17 by receiving the signals output from the signal, and the signals required to drive the gate output from the timing controller 13 to receive the signals of the LCD panel 17. And a gate driver 19 for driving the pixel.

Here, the timing controller 13 receives the R, G, and B image data from the LVDS 10, and outputs a signal necessary for driving the data to be divided into even and odd numbers, respectively, and outputs the divided signals. 2, which has a first memory portion 15A for storing data transmitted in the previous frame and a second memory portion 15B for storing data to be transmitted in the current frame, as shown in FIG. In addition, by comparing the data of the first memory unit 15A and the second memory unit 15B, the data driver 18 outputs a control signal REV for determining whether or not a large amount of transition occurs between the data. Comparator 16 is included.

The operation description for this is as follows.

A total of 36 pieces of data each of 6 bits each of even and odd numbers of R, G, and B are compared with the data to be transmitted at the present time and the previously transmitted data, and when the transition between the data occurs a lot, the current data is reversed. The control signal REV is transmitted to the data driver 18 at a "high" level voltage. At this time, if the control signal REV is a "high" level voltage, the data driver 18 inverts and recognizes the input data.

On the other hand, if less transition occurs, the data is transmitted to the data driver 18 as it is, and the control signal REV is transmitted to the data driver 18 as a 'low' level voltage. At this time, the data driver 18 recognizes the input data as it is if the control signal REV is a "low" level voltage.

That is, a total of 36 data are compared to transmit data and control signals according to whether or not 18 or more transitions occur between the data and the data driver 18.

Accordingly, rather than directly transmitting the data of the current frame to the data driver, the data of the previous frame is inverted and transmitted when the data transition of the current frame is compared with the data of the current frame. We have improved the EMI by reducing the number of data transitions.

However, the improvement of EMI as described above has been limited in recent liquid crystal displays due to the trend toward larger size and higher resolution.

Accordingly, an object of the present invention is to provide a liquid crystal display timing controller capable of effectively improving EMI.

1 is a block diagram of a conventional liquid crystal display device.

FIG. 2 is a configuration diagram of the timing controller of FIG. 1.

3 is a block diagram for explaining a liquid crystal display timing controller according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: timing controller 110: data driver

M1 to M12: first to twelfth memory parts

C1 to C6: first to sixth comparators

The timing controller for a liquid crystal display according to the present invention for achieving the above object is to drive the data by dividing the input red (R), green (G), blue (B) image data into even (Even) and odd (Odd) data A timing controller for liquid crystal display for outputting a signal required for a data driving circuit section, comprising: first to sixth memory sections each storing red, green, and blue data used in all frames separately and evenly; Each of the seventh to twelfth memory units for storing red, green, and blue data to be used in the current frame divided into even and odd numbers, and the first to second data units when outputting data from the current frame to the data driving circuit unit. And a first to sixth comparators configured to compare data transitions between red, green, and blue data stored in the sixth memory unit and the seventh through twelfth memory units, and output corresponding data. And that is characterized.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Here, since the general components constituting the liquid crystal display device are the same as those of the conventional liquid crystal display device, a description of the overall configuration of the liquid crystal display device is omitted, and a description of the timing controller which is a feature of the present invention is shown in FIG. 3. It demonstrates with reference.

3 is an internal configuration diagram illustrating a timing controller for liquid crystal display.

As shown, the timing controller 100 receives 6-bit image data of red (R), green (G), and blue (B) in a system interface (not shown), and receives even and odd numbers. A memory unit for dividing the data into data and outputting a signal for data driving to the data driver 110 is included.

The memory unit stores first, sixth, and sixth memory units M1 to M6, each of which is divided into even and odd numbers of red, green, and blue data used in the previous frame, and red, green, and blue used in the current frame. Each of the seventh to twelfth memory parts M7 to M12 for storing each data evenly and oddly, and for outputting data from the current frame to the data driving circuit part. Comparing data transitions between red, green, and blue data of data stored in M1 to M6 and the seventh to twelfth memory units M7 to M12, and corresponding data (R data, G data, and B data) It includes a first to sixth comparators (C1 to C6) for outputting.

In this case, the first to sixth comparators C1 to C6 control data REV_1 to REV_6 for displaying the compared data between the respective data and the information of the compared data R data, G data, and B data. Outputs

The first to sixth comparators C1 to C6 compare the transitions between the data, and when three or more transitions occur, invert the data stored in the current frame and output the inverted data to the data driver 110. REV_1 to REV_6 output a 'high' level voltage.

In addition, the first to sixth comparators C1 to C6 compare the data transitions, and if less than three data transitions occur, output the data stored in the current frame to the data driver 110 as it is. The control signals REV_1 to REV_6 output a 'low' level voltage.

A detailed description of the operation is as follows.

6-bit data for each of the even and odd numbers of R, G, and B are compared with the data to be transmitted at the present time and the previously transmitted data in the comparators C1 to C6, respectively. Is reversed, and the control signals REV_1 to REV_6 are transmitted to the data driver 110 with the "high" level voltage. In this case, if the control signals REV_1 to REV_6 are "high" level voltages, the data driver 110 inverts and recognizes the input data.

On the other hand, the comparators C1 to C6 compare the data to be transmitted at the present time with the data of 6 bits each of even and odd numbers of R, G, and B in the comparators C1 to C6, respectively. The current data is transmitted to the data driver 110 as it is, and the control signals REV_1 to REV_6 at this time are transmitted to the data driver 110 with the "low" level voltage. The data driver 110 recognizes the input data as it is if the control signals REV_1 to REV_6 are "low" level voltages.

For example, when the data R6 to R1 of the first memory unit M1 used in the previous frame is 110011 and the data R6 to R1 of the seventh memory unit M7 in which the current frame is used are 111010, then the transition is made. Since the number of bits is two, the data 111010 is transmitted to the data driver 110 as it is, and the control signal REV_1 at this time is transmitted to the data driver 110 at a "low" level voltage.

In addition, if the data R6 to R1 of the first memory unit M1 used in the previous frame is 110011 and the data R6 to R1 of the seventh memory unit M7 using the current frame are 001010, then the transition is made. Since the number of bits is four, the comparator C1 transmits the inverted data 110101 of 001010 to the data driver 110. This is because there is a lot of data corresponding to 110011 used in the previous frame, so that data transition can be reduced by that much. At this time, the control signal REV_1 is transmitted to the data driver 110 at a "high" level voltage.

The data driver 110 recognizes the input data 110101 as 001010 data because the control signal REV1 is a “high” level voltage.

In this manner, the stored data of the first to sixth memory units M1 to M6 and the seventh to twelfth memory units M7 to M12 are compared, respectively, and the corresponding data voltages R data, G data, and B data. ) And the control signals REV_1 to REV_6 to the data driver 110, it is possible to effectively improve the EMI by reducing the data transition by the corresponding bit value of the data of the previous frame and the data of the current frame.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

According to the timing controller for liquid crystal display of the present invention described above, each of the first to sixth memory units M1 to M6 for storing the red, green, and blue data used in the previous frame by dividing the data evenly and evenly And each of the seventh to twelfth memory parts M7 to M12 for storing the red, green, and blue data to be used in the current frame by dividing the data evenly and oddly. The stored data of the first to sixth memory units M1 to M6 and the seventh to twelfth memory units M7 to M12 are compared, respectively, and the corresponding data voltages (R data, G data, B data) and control signals ( By transmitting REV_1 to REV_6 to the data driver 110, EMI can be effectively improved by reducing data transition by a corresponding bit value of data of the previous frame and data of the current frame.

Claims (4)

The red (R), green (G), and blue (B) input image data are divided into even (even) and odd (odd) signals to a liquid crystal display timing controller that outputs the signals required for data driving to the data driving circuit unit. In First to sixth memory units for storing red, green, and blue data used in the previous frame by dividing the data evenly and oddly; A seventh to twelfth memory unit for storing red, green, and blue data to be used in the current frame by dividing the data evenly and oddly; When data is output from the current frame to the data driving circuit unit, the data stored in the first to sixth memory units and the seventh to twelfth memory units are compared with respective data transitions between red, green, and blue data. And a first to sixth comparators for outputting data. The method of claim 1, And the first to sixth comparators output a control signal for displaying the compared data between the data and the information of the compared data. The method of claim 2, The first to sixth comparators compare the transitions between the data, and when three or more transitions occur, the data stored in the current frame is inverted and output to the data driver, and the control signal outputs a 'high' level voltage. A timing controller for liquid crystal display, characterized in that. The method of claim 2, The first to sixth comparators compare the transitions between the data and output the data stored in the current frame to the data driver as it is, when less than three data transitions occur, and the control signal outputs a 'low' level voltage. A timing controller for liquid crystal display, characterized in that.