KR19980059990A - Panel structure and its driving circuit designed to implement dot inversion in low voltage driving - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a panel structure of a liquid crystal display device and a driving circuit thereof. The present invention relates to a shift register for receiving and shifting RGB data corresponding to one horizontal line according to an input clock signal, and a parallel output signal of the shift register. A first latch for temporarily storing the second latch for temporarily storing even-numbered pixel data among the RGB data components stored in the first latch and an odd number of pixel data among the RGB data components stored in the first latch for the temporary storage And a digital-analog converter for selecting an analog gray voltage corresponding to the output digital pixel data when the pixel data stored in the third latch is output by the load signal. Panel to implement dot reversal to reduce crosstalk in It relates to a structure and a driving circuit thereof.

Description

Panel structure and its driving circuit designed to implement dot inversion in low voltage driving

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a panel structure and a driving circuit thereof in a liquid crystal display device, and more particularly, to a panel structure and a driving circuit thereof designed to implement dot inversion in low voltage driving.

BACKGROUND ART A conventional active matrix liquid crystal display device displays an image by controlling a gray voltage applied to a liquid crystal capacitor using a switching element such as a thin film transistor.

Such a driving method of the liquid crystal display includes a low voltage driving method having a low voltage of 5 V or less, and a high voltage driving method having a high voltage of 10 V or more.

In general, in a low voltage driving method, a line inversion driving method in which the polarity of the gray voltage is inverted in a horizontal line period is used. In the high voltage driving method, a dot inversion in which the polarity of the gray voltage is inverted in one pixel period is used. (dot inversion) driving method is used.

Next, the data driver using the line inversion driving method in the low voltage driving mentioned above will be described in more detail.

As shown in Fig. 1, the conventional low voltage driving data driver is composed of a shift register 10, latches 21 and 22 and a digital-analog converter 40.

First, the shift register 10 starts to receive the pixel data by the carry_in signal, which is a carry_in. The shift register 10 receives the RGB data RGB_data (s) corresponding to one horizontal line in series and shifts the clock signal. The input and shift operations are repeated in the cycle of MCLK). When one shift register is filled with the input pixel data, a carry_out signal is output to the second data driver, and the shift register of the second data driver repeats the above input and shift operations.

In this manner, the RGB data RGB_data filled in all the shift registers is temporarily stored in the first and second latches 21 and 22, and when a load signal is input, the RGB data RGB_data stored in the second latch 22 ( RGB_data) is output to the digital-analog converter 40, and the analog gray level voltage corresponding to the digital pixel data RGB_data is selected and output. 2 shows a timing diagram for implementing line inversion through the above process.

However, unlike the dot inversion driving, the line inversion driving implemented at the low voltage has some problems. That is, distortion of the counter electrode voltage Vcom occurs due to coupling capacitance existing between the data line and the counter electrode during line inversion, and such distortion causes a difference in gradation. As a result of the gray level difference, crosstalk (interference phenomenon between pixel data) is generated, resulting in deterioration of image quality.

Accordingly, an object of the present invention is to provide a panel structure for implementing dot inversion that can reduce crosstalk in a low voltage driving method, and a driving circuit thereof.

1 is a block diagram of a conventional low voltage driving data driver (Data Driver),

2 is a timing diagram of a conventional low voltage driving data driver,

3 is a structural diagram of a panel according to an embodiment of the present invention;

4 is a configuration diagram of a data driver according to an embodiment of the present invention;

5 is a timing diagram of a data driver according to an embodiment of this invention.

According to an aspect of the present invention, there is provided a panel comprising: n gate lines arranged in a horizontal direction of the panel; M data lines arranged in the vertical direction of the panel; A first pixel portion formed at a point where the first to (n-1) th gate lines and the odd (or even) data line cross each other; The second pixel portion includes a second pixel portion formed at a point where the second to nth gate lines and the even (or odd) data line cross each other.

In the above panel structure, only the odd pixel of the first horizontal line is driven when a signal is applied to the first gate line, and the odd pixel of the second horizontal line and the first pixel of the second horizontal line is applied when a signal is applied to the second gate line. The even-numbered pixels of the first horizontal line are simultaneously driven, and the polarity of the gray voltage applied in the horizontal line period is inverted, thereby enabling dot inversion driving.

In this dot inversion driving, since a gray voltage of opposite polarity is always applied around one pixel, the crosstalk is fundamentally eliminated since the current flowing into the counter electrode and the current flowing out of each other cancel each other out so that almost no voltage distortion occurs. can do.

However, in order to completely display each horizontal line in the panel having the pixel structure as described above, the attribute of pixel data applied at one time is an odd number of even-numbered pixel data of the previous horizontal line and the current horizontal line. The first pixel data must be included.

Therefore, a driving circuit according to the present invention for realizing this includes: a shift register for receiving and shifting RGB data corresponding to one horizontal line according to an input clock signal; A first latch for temporarily storing a parallel output signal of the shift register; A second latch for temporarily storing even-numbered pixel data of the RGB data components stored in the first latch; A third latch for temporarily storing odd pixel data among the RGB data components stored in the first latch; When the pixel data stored in the third latch is output by the load signal, a digital-to-analog converter for selecting an analog gray voltage corresponding to the output digital pixel data is included.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention in detail.

First, in the structure of the panel according to the embodiment of the present invention shown in FIG. 3, the first pixel portion is the first to (n-1) th gate lines gate1 to gate (n-1) and odd-numbered data. It is formed at the point where the lines so1, so3 ... cross, and the second pixel portion intersects the second to nth gate lines gate2 to gaten and the even-numbered data lines so2, so4 ... It is formed at the point.

Next, in the data driver for driving the panel having such a pixel structure, the shift register 10 has the RGB data corresponding to one horizontal line in accordance with the input clock signal MCLK as shown in FIG. RGB_data (s)) is serially input and shifted.

The first latch 31 temporarily stores the parallel output signal RGB_data of the shift register 10, wherein the even-numbered pixel data RGB_data of the RGB data elements RGB_data stored in the first latch 31 is temporarily stored. even) is stored in the second latch 32 again, and the odd-numbered pixel data RGB_data (odd) is stored in the third latch 33.

When the pixel data stored in the third latch 33 is output by the load signal, the digital-analog converter 40 selects and outputs an analog gray voltage corresponding to the output digital pixel data.

The data driver according to the embodiment of the present invention shown in FIG. 4 includes a latch of 31 stages, 32, and 33 in total by adding a latch of one stage to a conventional data driver having a latch of two stages. It is designed to separate each odd data and even data of the previous line and the current line. Accordingly, the data output at one time through the latch 33 may include even-numbered pixel data of a previous horizontal line and odd-numbered pixel data of a current horizontal line.

In other words, when pixel data corresponding to the current horizontal line is output from the first latch 31, even-numbered data RGB_data (even) is temporarily stored in the second latch 32 and only odd-numbered data RGB_data (odd)) is output to the digital-analog converter 40 through the third latch 33.

Next, when the pixel data corresponding to the next horizontal line is output again from the first latch 31, the odd-numbered pixel data and the immediately previous horizontal stored in the second latch 32 are generated. The even-numbered pixel data of a line is summed and output from the third latch 33. The period of the output timing of the third latch 33 is determined by a load signal, and the period of the signal is the same as the period of the gate driving signal.

When the panel having the pixel structure as shown in FIG. 3 is driven through the data driver as shown in FIG. 4, the application process of the gray scale voltage is as follows.

First, when the gate signal is supplied to the first gate line gate1 shown in FIG. 3, only the odd numbered pixels of the first horizontal line are driven. When the gate signal is supplied to the second gate line gate2, the second horizontal line is provided. The odd pixels of and the even pixels of the first horizontal line are driven simultaneously.

Even when image data of the same polarity is simultaneously supplied through the data line, since the odd-numbered pixels and even-numbered pixels of the horizontal lines adjacent to each other are actually driven, consequently, gray level voltages of different polarities are applied to adjacent pixels of the same horizontal line. . 5 is a timing diagram illustrating a process of outputting the pixel data as described above.

Therefore, the effect of the panel structure and the driving circuit thereof according to the embodiment of the present invention is that it is possible to provide a good image by implementing dot inversion in the low voltage driving method to reduce crosstalk.

Claims (2)

N gate lines arranged in the horizontal direction of the panel; M data lines arranged in the vertical direction of the panel; A first pixel portion formed at a point where the first to (n-1) th gate lines and the odd (or even) data line cross each other; And a second pixel portion formed at a point where the second to nth gate lines and the even (or odd) data line cross each other. A shift register for receiving and shifting RGB data corresponding to one horizontal line according to an input clock signal; A first latch for temporarily storing a parallel output signal of the shift register; A second latch for temporarily storing even-numbered pixel data of the RGB data components stored in the first latch; A third latch for temporarily storing odd pixel data among the RGB data components stored in the first latch; And a digital-analog converter for selecting an analog gray voltage corresponding to the output digital pixel data when the pixel data stored in the third latch is output by the load signal.