KR19980057025A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- KR19980057025A KR19980057025A KR1019960076295A KR19960076295A KR19980057025A KR 19980057025 A KR19980057025 A KR 19980057025A KR 1019960076295 A KR1019960076295 A KR 1019960076295A KR 19960076295 A KR19960076295 A KR 19960076295A KR 19980057025 A KR19980057025 A KR 19980057025A
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- Prior art keywords
- source
- drain
- channel stop
- ion implantation
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims 2
- -1 gallium ions Chemical class 0.000 claims 2
- 239000012535 impurity Substances 0.000 abstract description 8
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 230000008859 change Effects 0.000 abstract description 3
- 230000005465 channeling Effects 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 분야1. Fields to which the invention described in the claims belong
반도체 소자 제조.Semiconductor device manufacturing.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
채널 스톱영역 및 P+소오스 및 드레인 형성을 위해 BF2 +또는 B+를 사용할 경우, 문턱전압이 천이되고 B+의 채널링 현상으로 얕은 접합을 형성하기 어려운 문제를 해결하기 위함.When BF 2 + or B + is used to form the channel stop region and P + source and drain, the threshold voltage is shifted and the channeling phenomenon of B + makes it difficult to form a shallow junction.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
MOSFET의 채널스톱영역 및 소오스/드레인을 Ga+를 이용하여 형성함으로써 채널스톱영역의 불순물의 확산으로 인한 문턱전압의 변화를 방지하고 얕은 접합구조의 소오스 및 드레인을 실현함.The channel stop region and source / drain of the MOSFET are formed by using Ga + to prevent the change of the threshold voltage due to diffusion of impurities in the channel stop region and to realize the source and drain of the shallow junction structure.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 소자의 제조에 이용됨.Used in the manufacture of semiconductor devices.
Description
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 채널스톱(channel stop) 영역의 불순물의 확산으로 인한 문턱전압의 변화를 방지하고 얕은 접합구조의 소오스 및 드레인을 실현할 수 있는 MOSFET 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a MOSFET capable of preventing a change in threshold voltage due to diffusion of impurities in a channel stop region and realizing a source and a drain having a shallow junction structure.
MOSFET의 제조에 있어서, 종래에는 채널 스톱영역 형성을 위한 불순물로서 BF2 +또는 B+를 사용해 왔는데, 이는 원자량이 가벼워 불순물 주입후 어닐링 공정을 거치게 되면 불순물이 활성영역으로 확산되어 MOSFET의 문턱전압을 천이시키는 문제를 유발하였다.In the manufacture of MOSFETs, conventionally, BF 2 + or B + has been used as an impurity for forming a channel stop region, which is light in atomic weight, and when an annealing process is performed after impurity injection, impurities diffuse into the active region to reduce the threshold voltage of the MOSFET. It caused a problem of transition.
또한, P+소오스 및 드레인 형성시에도 BF2 +또는 B+를 사용해 왔다. 그러나 B+를 사용할 경우에는 B+의 채널링 현상으로 얕은 접합(shallow junction)을 형성하기 어렵다. BF2 +이온을 이용하게 되면 채널링 현상은 다소 감소시킬 수 있으나, 잔류하는 F이온이 후속 열처리공정에서 분리(segregation)되어 표면에 결함(stacking fault)를 형성하고 또한 접합영역에 침투하여 소자의 성능을 저하시키는 문제가 있었다.In addition, BF 2 + or B + has been used to form P + sources and drains. However, when B + is used, it is difficult to form a shallow junction due to the channeling phenomenon of B + . The use of BF 2 + ions can reduce the channeling phenomena, but the remaining F ions are segregated in the subsequent heat treatment process, forming stacking faults on the surface and penetrating into the junction area. There was a problem of lowering.
본 발명은 MOSFET의 채널스톱영역 및 소오스/드레인을 Ga+를 이용하여 형성함으로써 채널스톱영역의 불순물의 확산으로 인한 문턱전압의 변화를 방지하고 얕은 접합구조의 소오스 및 드레인을 실현할 수 있도록 하는 반도체소자의 제조방법을제공하는 것을 그 목적으로 한다.The present invention provides a semiconductor device for forming a channel stop region and a source / drain of a MOSFET using Ga + to prevent a change in threshold voltage due to diffusion of impurities in the channel stop region and to realize a source and a drain having a shallow junction structure. To provide a method for the production of
상기 목적을 달성하기 위한 본 발명의 반도체소자 제조방법은 반도제기판의 소정영역상에 게이트산화막을 개재하여 게이트전극을 형성하는 단계와, Ga+을 이온주입하여 상기 게이트전극 양단의 기판부위에 얕은 접합의 소오스 및 드레인영역을 형성하는 단계를 포함한다.The semiconductor device manufacturing method of the present invention for achieving the above object is a step of forming a gate electrode via a gate oxide film on a predetermined region of the semiconductor substrate, and implanted Ga + to shallow the substrate region across the gate electrode Forming a source and drain region of the junction.
도 1a 및 도 1b는 본 발명에 의한 MOSFET 제조방법을 도시한 도면.1A and 1B illustrate a method for manufacturing a MOSFET according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 패드산화막1 semiconductor substrate 2 pad oxide film
3 : 질화막 4 : 포토레지스트패턴3: nitride film 4: photoresist pattern
5 : 필드산화막 6 : 게이트전극5: field oxide film 6: gate electrode
7 : 소오스 및 드레인7: source and drain
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1a 및 도 1b에 본 발명에 의한 MOSFET 제조방법을 도시하였다.1A and 1B show a MOSFET manufacturing method according to the present invention.
즉, 반도체기판(1)상에 패드산화막(2)과 질화막(3)을 차례로 형성하고, 이위에 소자분리영역 형성을 위한 소정의 포토레지스트패턴(4)을 형성한 후, 포토레지스트패턴을 마스크로 하여 상기 질화막(3)과 패드산화막(2)을 식각하여 반도체기판소정부위의 소자분리영역을 노출시킨다. 이어서 채널스톱 이온주입을 행하는바, AMU(atomic mass unit)가 큰 Ga+이온을 60-80keV의 이온주입에너지에 의해 1.0E11-1.0E13의 도우즈로 기판에 주입하여 채널스톱영역을 형성한다.That is, the pad oxide film 2 and the nitride film 3 are sequentially formed on the semiconductor substrate 1, and a predetermined photoresist pattern 4 for forming an isolation region is formed thereon, and then the photoresist pattern is masked. The nitride film 3 and the pad oxide film 2 are etched to expose the device isolation region on the semiconductor substrate. Subsequently, channel stop ion implantation is performed, and Ga + ions having a large AMU (atomic mass unit) are implanted into the substrate with a dose of 1.0E11-1.0E13 at 60-80 keV ion implantation energy to form a channel stop region.
이어서 도 1b에 도시된 바와 같이 상기 포토레지스트패턴을 제거한 후, 필드산화공정을 행하여 소자분리영역상에 필드산화막(5)을 형성한다. 이때, 필드산화시 그 온도가 높기 때문에 종래와 같이 AMU가 작은 BF2 +또는 B+를 사용하여 채널스톱영역을 형성할 경우에는 측면확산이 일어나게 되나, 상기와 같이 AMU가 큰 Ga+주입하여 채널스톱영역을 형성함으로써 이러한 측면확산을 방지할 수 있고 따라서 문턱전압이 천이되는 것을 방지할 수 있게 된다.Subsequently, after removing the photoresist pattern as shown in FIG. 1B, a field oxidation process is performed to form the field oxide film 5 on the device isolation region. At this time, since the temperature is high during field oxidation, when the channel stop region is formed by using BF 2 + or B + with small AMU, lateral diffusion occurs. However, Ga + is injected with a large AMU as described above. By forming the stop region, such side diffusion can be prevented and thus the threshold voltage can be prevented from transitioning.
다음에 상기 필드산화막(5)에 의해 한정된 활성영역상에 게이트산화막을 개재하여 게이트전극(6)을 형성한 후, P+ 소오스 및 드레인(7) 형성을 위하여 Ga+이온을 60-80keV의 이온주입에너지에 의해 1.0E14-1.0E16의 도우즈로 주입한 다음, RTP(rapid thermal process)에 의해 700-1050℃로 30-180초간 어닐링을 행한다. 이때, 주입되는 Ga+이온은 불순물을 포함하고 있지 않으므로 높은 에너지에 의해 분리(segregation)가 일어나지 않아 얕은 접합의 소오스 및 드레인(7)을 형성할 수 있다.Next, the gate electrode 6 is formed through the gate oxide film on the active region defined by the field oxide film 5, and Ga + ions are implanted at 60-80 keV in order to form the P + source and drain 7. Inject by energy into doses of 1.0E14-1.0E16 and then anneal at 700-1050 ° C. for 30-180 seconds by rapid thermal process (RTP). In this case, since the implanted Ga + ions do not contain impurities, segregation is not caused by high energy, so that the source and drain 7 of the shallow junction can be formed.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
본 발명에 의하면, 채널스톱 불순물의 확산을 억제할 수 있어 문턱전압 천이 및 전류감소를 방지할 수 있으며, 얕은 접합구조의 소오스 및 드레인을 형성할 수 있어 MOSFET의 성능을 향상시킬 수 있다.According to the present invention, diffusion of channel stop impurities can be suppressed to prevent threshold voltage transition and current reduction, and a source and a drain having a shallow junction structure can be formed, thereby improving the performance of the MOSFET.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960076295A KR100251989B1 (en) | 1996-12-30 | 1996-12-30 | Method for manufacturing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960076295A KR100251989B1 (en) | 1996-12-30 | 1996-12-30 | Method for manufacturing semiconductor device |
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| Publication Number | Publication Date |
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| KR19980057025A true KR19980057025A (en) | 1998-09-25 |
| KR100251989B1 KR100251989B1 (en) | 2000-04-15 |
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| KR1019960076295A KR100251989B1 (en) | 1996-12-30 | 1996-12-30 | Method for manufacturing semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100674943B1 (en) * | 2005-01-15 | 2007-01-26 | 삼성전자주식회사 | Sb, Ga or Bi doped Semiconductor Device and Manufacturing Method for the Same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100217899B1 (en) * | 1996-04-18 | 1999-09-01 | 김영환 | Method of manufacturing transistor of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100674943B1 (en) * | 2005-01-15 | 2007-01-26 | 삼성전자주식회사 | Sb, Ga or Bi doped Semiconductor Device and Manufacturing Method for the Same |
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