KR19980056984A - Phase locked loop circuit - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Adjustable Phase Locked Loop

2. Technical problem to be solved by the invention

As a general semiconductor circuit, a phase-locked loop circuit is often unable to obtain a desired output signal as a result of a decrease in reliability of an analog circuit part after designing. In this case, if a desired output signal cannot be obtained, it is necessary to design again. The time and economic losses of repetition were inevitable.

3. Summary of the Solution of the Invention

Even after the circuit is completed after the semiconductor design process, the present invention aims to provide a phase-locked loop circuit that can adjust the output of the phase-locked loop from the outside to the output result that satisfies the specification.

4. Important uses of the invention

Phase locked loop

Description

Phase locked loop circuit

The present invention relates to a phase locked loop capable of obtaining a stable frequency applied to all fields using the phase locked loop.

1 is a diagram illustrating a phase locked loop circuit according to the prior art. As shown in the drawing, a loop filter (consisting of a register and a capacitor) is determined by a value determined at the time of design, and the layout is determined when designing a semiconductor. In the post-process, the loop filter circuit part, which is the circuit part of the analog part, is very unlikely to produce an output signal of a desired result due to the amount of change caused by various parameters in the process.

As described above, a phase-locked loop circuit as a general semiconductor circuit is often unable to obtain a desired output signal due to the result that the reliability of the analog circuit portion is degraded after design.

In this case, if the desired output signal is not obtained, it is necessary to redesign, thus saving time and economical loss due to the repetition of the process.

In the semiconductor field, when the phase fixed loop is designed and processed in the process of production, it is difficult to accurately implement the desired values for the analog circuit according to various conditions in the production process. In response, a response was required.

The present invention devised to solve the problems of the prior art can adjust the output of the phase-locked loop from the outside even after the circuit is completed through a post-semiconductor design process, even if the design is slightly out of specification, The aim is to provide a phase locked loop circuit that can be tuned to the output result.

In order to achieve the above object, the present invention provides a phase frequency detecting means for inputting a feedback signal of a reference input frequency and a divided output, and switching control means for selecting a path for transmitting a value of the output signal of the phase frequency detecting means. And the output frequency of the loop filtering means connected to the switching control means, the charge pumping means and the loop filtering means, and the output frequency of the voltage adjusting oscillator are divided into the reference input frequency to detect the phase frequency. And a dispensing means provided as means, wherein the switching control means receives a corresponding value according to the path selection of the switch / control unit and the switch / control unit to allow the output signal of the phase frequency detector to select the respective paths. A plurality of charge pump output to the loop filtering means Characterized in that high.

1 is a circuit diagram of a conventional phase locked loop,

2 is a circuit diagram of a phase locked loop according to the present invention;

3 is a configuration diagram of a switching controller.

* Explanation of symbols for main parts of the drawings

1: phase frequency detector 2: switching controller

3: loop filter 4: voltage adjusting oscillator

5: divider

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 2.

2 is a phase locked loop circuit diagram according to the present invention, in which 1 represents a phase frequency detector, 2 represents a switching controller, 3 represents a loop filter, 4 represents a voltage adjusting oscillator, and 5 represents a divider.

As shown in the figure, the phase frequency detector (PFD) 1 inputs a signal fed back with a reference input frequency and an output of a voltage adjusting oscillator (VCO) 4 to be described later, and sets two signals as frequency and phase. Compare and output the difference of the signal fed back compared to the reference signal as a result of the comparison detection result.

The switching controller is composed of a circuit that separates the charge pump circuit into three paths and selectively outputs three paths.

The output signal of the phase frequency detector 1 is applied to the corresponding charge pump group along the path determined by the switching controller 2. The charge pump group used here is determined by an arbitrary specification so that the dynamic range of the output (swing width of the output) differs depending on the size of each transistor.

Therefore, the size of the capacitor, which is difficult for semiconductor layout design, is fixed, and the signal input to the loop filter 3 is changed from the charge pump group in the preceding stage, thereby changing the output signal at the final output stage of the phase locked loop circuit. The frequency can be adjusted and can have improved functionality, especially as a jitter compensation circuit.

The circuit which becomes the main point of this invention is the switching control part 2, The detail about this circuit is shown in FIG.

First, the register 6 is used to set a flag as many as the number of charge pumps (in the preferred embodiment, three charge pumps are used). Each flag has control data for making three switch control signals. That is, when '1' is set in the flag, the corresponding switch is turned on, and when it is '0', it is turned off.

The circuits that make up the switching block are routed using a universal tri-state buffer, and the enable state of the tri-state takes the place of the switch. There are two tri-state buffers per switching path, and the enable signal of the pair of buffers required to make one switching path must be the same.

As described above, the present invention relates to a product that is designed as a semiconductor by inserting an adjustable design adjustment factor to obtain a desired result even after completion of manufacturing. It has the advantage of increasing reliability and being able to cope with some of the risks that may occur during production.

Claims (2)

Phase frequency detection means for inputting a feedback signal of a divided frequency and a reference input frequency, switching control means for selecting a path for transmitting a value of an output signal of the phase frequency detection means, and loop filtering connected to the switching control means Means, a voltage adjusting oscillator (VCO) connected to the charge pumping means and the loop filtering means, and a divider means for dividing an output frequency of the voltage adjusting oscillator to the reference input frequency to provide the phase frequency detecting means, The switching control means may include a plurality of charges for receiving a corresponding value according to the path selection of the switch / control unit and the switch / control unit to allow the output signal of the phase frequency detector to select respective corresponding paths. Phase synchronization comprising a pump Program circuit. The method of claim 1, wherein the switch / control unit sets a flag configured by a register as many as the number of the charge pumps, and each flag is configured as a tri-state buffer to have control data for generating a corresponding switch control signal. A phase locked loop circuit.