KR19980055917A - Plug Formation Method for Semiconductor Devices - Google Patents
Plug Formation Method for Semiconductor Devices Download PDFInfo
- Publication number
- KR19980055917A KR19980055917A KR1019960075154A KR19960075154A KR19980055917A KR 19980055917 A KR19980055917 A KR 19980055917A KR 1019960075154 A KR1019960075154 A KR 1019960075154A KR 19960075154 A KR19960075154 A KR 19960075154A KR 19980055917 A KR19980055917 A KR 19980055917A
- Authority
- KR
- South Korea
- Prior art keywords
- metal layer
- plug
- forming
- etching
- insulating film
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
Abstract
본 발명은 반도체 소자의 플러그 형성방법에 관한 것으로, 소정의 공정을 거친 실리콘 기판 상에 절연막 및 금속층을 순차적으로 형성한 후 금속층을 소정두께 식각하여 플러그를 형성하고, 절연막이 노출되도록 남아 있는 금속층을 식각하여 금속층 패턴을 형성함으로써 공정이 감소되고, 금속층 패턴 및 플러그를 동일 재질로 형성함으로써 접촉저항을 감소시킬 수 있는 효과가 있다.The present invention relates to a method for forming a plug of a semiconductor device, and sequentially forming an insulating film and a metal layer on a silicon substrate that have been subjected to a predetermined process, and then etching the metal layer to a predetermined thickness to form a plug, and the remaining metal layer to expose the insulating film. The process is reduced by etching the metal layer pattern, and the contact resistance is reduced by forming the metal layer pattern and the plug using the same material.
Description
본 발명은 플러그 형성방법에 관한 것으로 특히, 금속층 형성후 식각공정에 의해 플러그를 형성할 수 있는 반도체 소자의 플러그 형성방법에 관한 것이다.The present invention relates to a method for forming a plug, and more particularly, to a method for forming a plug of a semiconductor device capable of forming a plug by an etching process after forming a metal layer.
일반적으로 텅스텐 플러그는 금속배선 형성 공정시 서브마이크론 이하의 미세한 비아홀(또는 콘택홀)을 알루미늄으로 충분히 채울 수 없을 경우에 도 1a 내지 1e에 도시된 바와 같이 비아홀을 포함한 전체구조 상에 텅스텐을 증착하고, 전면 식각 공정으로 텅스텐을 식각함으로써 비아홀 내부에 형성된다. 도 1a는 소정의 공정을 거쳐 실리콘 기판(1) 상에 절연막(2)을 형성하고, 절연막(2) 상에 금속층 패턴(3)을 형성한 후 층간 절연막(4)을 형성한 상태를 도시한다. 도 1b는 금속층 패턴(3)이 노출되도록 층간 절연막(4)을 식각하여 비아홀(10)을 형성한 상태를 도시한다. 도 1c는 실리콘 기판(1)의 표면에 CMP(Chemical Mechanical Polishing) 공정을 실시하여 평탄화시킨 상태를 도시하며 도 1d는 실리콘 기판(1)의 전체 상부면에 텅스텐층(5)을 형성한 상태를 도시한다. 도 1e는 텅스텐층(5)을 전면식각하여 텅스텐 플러그(5A)를 형성한 상태를 도시한다. 그러나 상기와 같은 종래 방법은 층간 절연막(4)의 식각을 통해 비아홀(10)을 형성하는 과정에서 산화막 및 평탄화막이 다층으로 적층 되어야 하고, 식각공정시 층간 절연막(4)의 특성에 따라 비아홀(10)의 정확한 형성이 어려우며 저항을 증가시키는 점 등이 있다. 또한, 금속층 패턴(3)은 알루미늄으로 이루어지고, 텅스텐 플러그(5A)는 텅스텐을 사용하기 때문에 상/하부의 서로 다른 금속층간 접촉저항이 증가하여 소자의 특성을 악화시키는 등의 문제점이 발생된다.In general, tungsten plugs deposit tungsten on the entire structure including via holes as shown in FIGS. 1A to 1E when the metal via formation process cannot fill the sub-micron fine via holes (or contact holes) with aluminum. The inner surface of the via hole is formed by etching tungsten by the front etching process. FIG. 1A shows a state in which the insulating film 2 is formed on the silicon substrate 1 through a predetermined process, the metal layer pattern 3 is formed on the insulating film 2, and then the interlayer insulating film 4 is formed. . FIG. 1B illustrates a state in which the via hole 10 is formed by etching the interlayer insulating film 4 so that the metal layer pattern 3 is exposed. FIG. 1C illustrates a planarized state by performing a chemical mechanical polishing (CMP) process on the surface of the silicon substrate 1, and FIG. 1D illustrates a state in which a tungsten layer 5 is formed on the entire upper surface of the silicon substrate 1. Illustrated. FIG. 1E shows a state in which the tungsten layer 5 is etched entirely to form the tungsten plug 5A. However, in the conventional method as described above, an oxide film and a planarization film should be stacked in a multi-layer in the process of forming the via hole 10 by etching the interlayer insulating film 4, and the via hole 10 may be changed according to the characteristics of the interlayer insulating film 4 during the etching process. ) Is difficult to form correctly and increases resistance. In addition, since the metal layer pattern 3 is made of aluminum, and the tungsten plug 5A uses tungsten, problems such as deterioration of characteristics of the device due to an increase in contact resistance between the upper and lower metal layers.
따라서 본 발명은 소정의 공정을 거친 실리콘 기판 상에 절연막 및 금속층을 순차적으로 형성한 후 금속층을 소정두께 식각하여 플러그를 형성하고, 절연막이 노출되도록 금속층을 식각하여 금속층 패턴을 형성할 수 있는 반도체 소자의 플러그 형성방법을 제공하는 것을 그 목적으로 한다.Accordingly, the present invention sequentially forms an insulating film and a metal layer on a silicon substrate that has been subjected to a predetermined process, and then forms a plug by etching the metal layer by a predetermined thickness, and forming a metal layer pattern by etching the metal layer to expose the insulating layer. It is an object of the present invention to provide a method for forming a plug.
상기한 목적을 달성하기 위한 본 발명에 따른 플러그 형성방법은 소정의 공정을 거친 실리콘 기판 상에 절연막 및 금속층을 순차적으로 형성하는 단계와, 상기 금속층을 소정두께 식각하여 플러그를 형성하는 단계와, 플러그가 형성된 금속층을 절연막이 노출되도록 식각하여 금속층 패턴을 형성하는 단계로 이루어지며 상기 금속층은 알루미늄을 사용하여 식각공정에 의해 형성되는 금속층 패턴 및 플러그가 합해진 두께로 형성된다.The plug forming method according to the present invention for achieving the above object comprises the steps of sequentially forming an insulating film and a metal layer on a silicon substrate, a predetermined process, forming a plug by etching the metal layer a predetermined thickness, and the plug The metal layer is etched to expose the insulating layer is formed to form a metal layer pattern, the metal layer is formed to the thickness of the metal layer pattern and the plug formed by the etching process using aluminum.
도 1a 내지 1e는 종래 반도체 소자의 플러그 형성방법을 설명하기 위한 소자의 단면도.1A to 1E are cross-sectional views of a device for explaining a plug forming method of a conventional semiconductor device.
도 2a 내지 2d는 본 발명에 따른 반도체 소자의 플러그 형성방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of a device for explaining a plug forming method of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 및 11 : 실리콘 기판2 및 12 : 절연막1 and 11: silicon substrate 2 and 12: insulating film
3 및 13 : 금속층 패턴4 : 층간 절연막3 and 13: metal layer pattern 4: interlayer insulating film
5 : 텅스텐층5A : 텅스텐 플러그5: tungsten layer 5A: tungsten plug
15 : 플러그16 : 금속층15 plug 16: metal layer
17A 및 17B : 제 1 및 제 2 감광막 패턴17A and 17B: first and second photosensitive film pattern
이하, 첨부된 도면을 참조하여 본 발명에 따른 플러그 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a plug according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 2d는 반도체 소자의 플러그 형성방법을 설명하기 위한 소자의 단면도로서, 도 2a는 실리콘 기판(11) 상에 절연막(12) 및 금속층(16)을 순차적으로 형성한 후 플러그가 형성될 부분의 상부에만 남도록 제 1 감광막 패턴(17A)을 형성한 상태를 도시한다. 상기 금속층(16)은 알루미늄으로 이루어지며 금속층 패턴 및 플러그가 합해진 두께 만큼 형성된다.2A to 2D are cross-sectional views of devices for describing a method of forming a plug of a semiconductor device. FIG. 2A is a portion in which an insulating film 12 and a metal layer 16 are sequentially formed on a silicon substrate 11, and then a plug is formed. A state in which the first photosensitive film pattern 17A is formed so as to remain only at the upper portion of is shown. The metal layer 16 is made of aluminum and is formed by the thickness of the metal layer pattern and the plug.
도 2b는 제 1 감광막 패턴(17A)을 마스크로 이용하여 금속층(16)을 소정깊이 식각함으로써 플러그(15)를 형성한 후 제 1 감광막 패턴(17A)을 제거한 상태를 도시한다. 상기 플러그(15)를 형성하기 위한 금속층(16)의 식각 깊이는 금속층 패턴이 형성될 두께가 남도록 실시된다.FIG. 2B illustrates a state in which the first photosensitive film pattern 17A is removed after the plug 15 is formed by etching the metal layer 16 by a predetermined depth using the first photosensitive film pattern 17A as a mask. The etching depth of the metal layer 16 for forming the plug 15 is performed so that a thickness in which the metal layer pattern is to be formed remains.
도 2c는 플러그(15)가 형성된 금속층(16) 상에 제 2 감광막 패턴을 형성한 상태를 도시하며 도 2d는 절연막(12)이 노출되도록 남아 있는 금속층(16)을 식각하여 금속층 패턴(13)을 형성한 상태를 도시한다.FIG. 2C illustrates a state in which a second photoresist pattern is formed on the metal layer 16 on which the plug 15 is formed. FIG. 2D illustrates the metal layer pattern 13 by etching the remaining metal layer 16 to expose the insulating layer 12. The state which formed the is shown.
상술한 바와 같이 본 발명에 의하면 소정의 공정을 거친 실리콘 기판 상에 절연막 및 금속층을 순차적으로 형성한 후 금속층을 소정두께 식각하여 플러그를 형성하고, 절연막이 노출되도록 남아 있는 금속층을 식각하여 금속층 패턴을 형성함으로써 다음과 같은 효과가 있다.As described above, according to the present invention, an insulating film and a metal layer are sequentially formed on a silicon substrate that has been subjected to a predetermined process, and then a plug is formed by etching the metal layer to a predetermined thickness, and the metal layer pattern is etched by etching the remaining metal layer to expose the insulating film. Formation has the following effects.
첫째, 단차 완화 및 층간 절연을 위한 다층의 층간 절연막을 형성하지 않음으로써 공정이 감소된다.First, the process is reduced by not forming a multilayer interlayer insulating film for step relaxation and interlayer insulation.
둘째, 비아홀을 사용하지 않고 형성됨으로써 층간 절연막 형성시 용이하다.Second, it is easy to form an interlayer insulating film by being formed without using a via hole.
마지막으로, 하부 금속층과 동일 재질로 형성함으로써 접촉저항을 대폭 감소시킬 수 있다.Finally, the contact resistance can be greatly reduced by forming the same material as the lower metal layer.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960075154A KR100414951B1 (en) | 1996-12-28 | 1996-12-28 | Method for forming plug of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960075154A KR100414951B1 (en) | 1996-12-28 | 1996-12-28 | Method for forming plug of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980055917A true KR19980055917A (en) | 1998-09-25 |
| KR100414951B1 KR100414951B1 (en) | 2004-04-13 |
Family
ID=37423084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960075154A KR100414951B1 (en) | 1996-12-28 | 1996-12-28 | Method for forming plug of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100414951B1 (en) |
-
1996
- 1996-12-28 KR KR1019960075154A patent/KR100414951B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR100414951B1 (en) | 2004-04-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6268283B1 (en) | Method for forming dual damascene structure | |
| US7119006B2 (en) | Via formation for damascene metal conductors in an integrated circuit | |
| KR100460771B1 (en) | Method of fabricating multi-level interconnects by dual damascene process | |
| US20030060037A1 (en) | Method of manufacturing trench conductor line | |
| KR100640430B1 (en) | Dual damascene method and method of fabricating the copper interconnection layer using the same | |
| CN111211095A (en) | Method for manufacturing conductive interconnection line | |
| KR100528070B1 (en) | Method for fabricating contact hole and stack via | |
| KR19980055917A (en) | Plug Formation Method for Semiconductor Devices | |
| JPH11186274A (en) | Dual damascene technique | |
| US20020081840A1 (en) | Method of manufacturing a semiconductor device including dual-damascene process | |
| KR100613384B1 (en) | Method of forming interconnection line for semiconductor device | |
| KR100422912B1 (en) | Method for forming contact or via hole of semiconductor devices | |
| KR100243739B1 (en) | Method of forming via hole for semiconductor device | |
| KR100393966B1 (en) | method for forming dual damascene of semiconductor device | |
| KR100470390B1 (en) | Method for minimizing space of local interconnection using damascene in fabricating SRAM device | |
| KR100678008B1 (en) | Method for fabricating metal line of semiconductor | |
| KR100480591B1 (en) | A manufacturing method of a semiconductor device having a multilayer wiring structure flattened by a damascene process | |
| KR19980058406A (en) | Method of forming multi-layered metal wiring of semiconductor device | |
| KR19990057891A (en) | Stack contact formation method of semiconductor device | |
| KR20060002405A (en) | Metal interconnection structure in semiconductor device and method for manufacturing the same | |
| JPH09172075A (en) | Manufacture for interlayer connection hole in multilayer wiring of semiconductor device | |
| KR20030018746A (en) | Method for forming metal wiring of semiconductor device | |
| KR19980058439A (en) | Via hole formation method of semiconductor device | |
| KR20020002931A (en) | Method for forming metal line of semiconductor device | |
| KR20020086098A (en) | a contact structure for interconnecting multi-level wires and a method for forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| LAPS | Lapse due to unpaid annual fee |