KR19980055842A - Frequency detection circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency detection circuit. In the conventional frequency detection circuit, the differential amplifier output stage of the positive feedback circuit portion is driven with a voltage, which requires a large number of current mirror stages and current source transistors, thereby reducing economic efficiency. .

Accordingly, the present invention provides a positive feedback means for performing a positive feedback on an input square wave signal by providing a single current mirror at each of the current driving amplifying output stages so that the current driving amplifier is driven with a current, and receiving a control signal from the positive feedback means. A frequency detecting circuit comprising a current driving logic means for generating a signal and a sawtooth wave generating means for receiving a logic signal generated by the current driving logic means and generating a sawtooth wave, the present invention provides a differential amplifier of a positive feedback means. Instead of driving the output stage with a voltage to drive current, a large number of devices can be reduced, and the current driving logic means is also driven using this current, thereby simplifying the circuit configuration.

Therefore, it is possible to reduce a large number of devices, thereby increasing the economics.

Description

Frequency detection circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency detection circuit, and more particularly, to a frequency detection circuit for simplifying the configuration of the frequency detection circuit.

Frequency detector refers to a square wave frequency that is input to generate a direct current (DC) level in proportional or inverse proportion to the magnitude of the frequency.

As shown in Fig. 1, the conventional frequency detection circuit includes a positive feedback circuit portion 1 for performing positive feedback on an input square wave signal, a current driving logic circuit portion 2 for generating a current driving logic signal, and the current driving. It consists of a sawtooth wave generation section 3 for receiving a logic signal generated by the logic circuit section 2 to generate a sawtooth wave.

The positive feedback circuit unit 1 includes a differential amplifier for amplifying and outputting a current with respect to an input signal Vin and a reference voltage Vref by including a current mirror of transistors Q1 and Q2 at an output terminal, and the differential amplifier. Transistor Q15 at the output stage, a current mirror composed of transistors Q16 and Q17 operated by the output signal of the transistor Q15, a current mirror composed of transistors Q12 and Q19, and a transistor Q13. A current mirror of Q14, a current mirror of transistors Q5 and Q6 for supplying a reference current Iref, a current source transistor Q7 and Q8 connected in common with the transistor Q6, It consists of one resistor (R1).

The current driving logic circuit 2 includes four current mirrors of transistors Q20 to Q27, current source transistors Q9 to Q11 connected in common to the transistor Q8, and transistors Q29 and Q30. Differential amplifier and resistors R2 to R4.

The sawtooth wave generating section 3 includes a current mirror composed of transistors Q32 and Q33, transistors Q31 and Q34 for receiving a logic signal generated by the current driving logic circuit section 2, and the transistor Q31. A capacitor C1 is charged and discharged according to the on / off state of Q34 to generate a sawtooth wave, and resistors R5 to R7.

The operation of the conventional frequency detection circuit configured as described above is as follows.

First, when the input signal Vin is high, the transistor Q3 is turned on, the transistor Q4 is turned off, and the transistor Q15 is turned off.

Accordingly, the transistors Q13 and Q14 are turned on, the reference current Iref flows through the collector of the transistor Q13, and 1/3 * 3Iref flows through the collector of the transistor Q12.

Accordingly, the current flowing through the resistor R1 flows 2/3 * Iref toward the base of the transistor Q4 from the reference voltage Vref side, so that the base potential of the transistor Q4 is further lowered. Is caught.

Further, when the transistors Q17 to Q18 are turned on as the transistor Q15 is turned off, and the collector current of the transistor Q14 flows by 4Iref, the current flowing to the collector of the transistor Q20 is Since it is 3/2 * Iref, transistors Q26 and Q29 are in a saturation state, and transistor Q30 is turned off.

Thus, transistor Q31 is turned off.

When the transistor Q31 is turned off in this manner, the transistor Q34 is turned off to become the charger between the capacitors C1, and the time constant thereof becomes R7 × C1.

On the other hand, when the input signal Vin is low, the transistors Q15 are saturated and the transistors Q16 to Q18 are turned off, thereby turning off all the transistors Q13 and Q14.

Therefore, the current flowing through the resistor R1 flows by 1/3 * Iref from the base side of the transistor Q4 toward the reference voltage Iref and the base potential of the transistor Q4 is further increased to provide positive feedback ( positive feedback)

In addition, since the transistor 18 is turned off as the transistor Q15 becomes saturated, the transistors Q26 and Q29 are also turned off.

At this time, since the base potential of the transistor Q30 is designed to be Iref x R3, the transistor Q30 is saturated and the transistor Q31 is turned off.

However, since the state of the transistor Q30 occurs later than the transistor Q29, as shown in FIG. 3, when the input signal Vin changes from high to low, both transistors Q29 and Q30 may be turned off at the same time.

When the two transistors Q29 and Q30 are turned off at the same time, the transistor Q31 is turned on and the transistor Q34 is saturated.

Therefore, the discharge period of the capacitor C1 becomes, where the discharge time is considerably short because the saturation period of the transistor Q31 is short.

As such, when the input signal Vin falls from high to low, the battery is completely discharged as shown in FIG. 2 and subsequently charged continuously.

In addition, the maximum potential of the sawtooth wave is inversely proportional to the frequency since the magnitude of the sawtooth wave is proportional to the period T since the charging time constant R7C1 is the same.

However, since the conventional frequency detection circuit as described above drives the differential amplifier output stage of the positive feedback circuit 10 with a voltage, a large number of current mirror stages and current source transistors are required, thereby degrading economic efficiency.

Accordingly, the present invention provides a frequency detection circuit for driving the amplifier output terminal of the positive feedback circuit section with a current and using the current to operate the current driving logic circuit section to reduce the number of devices and increase the economic efficiency. There is a purpose.

1 is a block diagram of a conventional frequency detection circuit.

2 is an input / output relationship waveform diagram of a frequency detection circuit.

3 is a diagram showing a state change of the transistor Q29 30 with respect to the input signal Vin in FIG.

4 is a block diagram of a frequency detection circuit of the present invention.

* Description of the symbols for the main parts of the drawings *

10: positive feedback circuit portion 20: current driving logic circuit portion

30: Sawtooth generator stage Q1-Q34: Transistor

R1 to R11: Resistor C1, C2: Capacitor

According to an aspect of the present invention, there is provided a frequency detection circuit including a positive feedback circuit unit having a single current mirror at each of the current driving amplifying output stages to drive a current driving amplifier with current to perform positive feedback on an input square wave signal. 10); A current driving logic circuit 20 receiving a control signal of the positive feedback circuit 10 to generate a logic signal; The sawtooth wave generator 30 receives the logic signal generated by the current driving logic circuit 20 to generate the sawtooth wave.

The positive feedback circuit unit 10 includes current mirrors of transistors Q4, Q5, and Q7, Q8 at the output terminals, respectively, and amplifies the current by the difference between the two input signals Vin (Vref). A differential amplifier comprising output transistors Q10 and Q11, and a transistor for controlling the reference current Iref according to the output signal of the differential amplifier so that the positive feedback is applied to the differential amplifier together with the resistance of the reference voltage Vref stage. And a current mirror of (Q12) and (Q13) and a current mirror of transistors (Q1) and (Q2) for generating a reference current (Iref).

The current driving logic circuit 20 is configured to generate a current driving logic signal according to a current mirror including transistors Q14 and Q15 for supplying a reference current Iref, and a control signal of the positive feedback circuit unit 10. A current source transistor Q3 for supplying current to the amplifier and the differential amplifier, and a resistor R10 for holding the base potential of the transistor Q17 of the differential amplifier high.

The sawtooth wave generator 30 is charged / discharged according to an on / off state of the transistor 18 for receiving a logic signal generated by the current driving logic circuit 20 and the transistor Q18 to generate a sawtooth wave. Capacitor C2 and a resistor R11 at the output terminal.

The operation and effects of the frequency detection circuit of the present invention configured as described above will be described in more detail as follows.

First, when the input signal Vin is high, the transistors Q4 to Q6 are turned on and the transistors Q7 to Q9 are turned off.

Accordingly, since the transistors Q12 and Q13 are turned on, Iref flows in the collector of the transistor Q12, and the current flowing through the resistor R8 is the base of the transistor Q11 at the reference voltage Vref. Flows toward the base, the base potential of the transistor Q11 falls further and further into positive feedback.

In addition, since the transistor Q6 is on, the transistor Q16 is in a saturation state, and the transistor Q17 is off because the transistor Q9 is off.

As a result, the transistor Q18 is turned off to become the charger between the capacitors C2, and the time constant thereof is R11 × C2.

On the other hand, when the input signal Vin is low, the transistors Q4 to Q6 are turned off and the transistors Q7 to Q9 are turned on.

Accordingly, since the transistors Q12 and Q13 are turned off, the Iref flows from the base side of the transistor Q11 toward the reference voltage Vref, so that the base potential of the transistor Q11 is further increased to give positive feedback. (positive feedback).

In addition, since the transistor Q6 is off, the transistor Q16 is turned off. Since the transistor Q9 is on, the base potential of the transistor Q17 is saturated by the resistor R10. do.

At this time, since the state of the transistor Q16 occurs later than the state of the transistor Q17 as in the prior art, when the input signal Vin changes from high to low, both transistors Q16 and Q17 are simultaneously turned off. The transistor 18 is in a saturation state.

Therefore, the discharge period of the capacitor C2 becomes.

That is, when the input square wave changes from high to low, it discharges completely. After that, the operation is repeated to generate a sawtooth wave.

As described above, the present invention can reduce the number of elements by driving the differential amplifier output stage of the positive feedback means constituting the frequency detection circuit with current instead of driving with voltage, and using this current, current driving logic means In addition, because it is driven, the circuit can be configured simply. Therefore, it is possible to reduce a large number of devices, thereby increasing the economics.

Claims (3)

Each of the current driving amplifying output stages has a single current mirror so that the current driving amplifier is driven with a current to perform positive feedback on the input square wave signal, and receives a control signal from the positive feedback means to generate a logic signal. And a sawtooth wave generating means for receiving a logic signal generated by the current driving logic means and generating a sawtooth wave. The method of claim 1, The positive feedback means comprises a current mirror comprising transistors Q4, Q5 and Q7, Q8 at its output stage, and amplifies and outputs a current equal to the difference between the two input signals Vin (Vref). A differential amplifier of Q10 and Q11 and a transistor Q12 for controlling the reference current Iref according to the output signal of the differential amplifier so that positive feedback is applied to the differential amplifier together with the resistance of the reference voltage Vref stage. A frequency detection circuit comprising a current mirror of (Q13) and a current mirror of transistors (Q1) and (Q2) for generating a reference current (Iref). 2. The current driving logic means according to claim 1, wherein the current driving logic means performs a current driving logic signal according to a current mirror made of transistors Q14 and Q15 for supplying a reference current Iref and a control signal of the positive feedback circuit portion 10. A differential amplifier to generate, a current source transistor Q3 for supplying current to the differential amplifier, and a resistor R10 for keeping the base potential of the transistor Q17 of the differential amplifier high. Frequency detection circuit.