KR19980055017A - Folding Cascode Differential Amplifier - Google Patents

Abstract

The present invention relates to a folding cascode differential amplifier which simplifies the circuit by using the necessary bias according to the folding cascode structure as a bias using the potential generated in the operation of the differential amplifier.

Therefore, in the present invention, the circuit can be simplified by not using a circuit that generates a necessary bias by basically having a folding cascode, thereby increasing the operating range of the output stage, When used as a working buffer amplifier, there is a big advantage.

Description

Folding Cascode Differential Amplifier

The present invention relates to a differential amplifier, and more particularly, to a folding cascode differential amplifier which simplifies the circuit by using a bias required according to the folding cascode structure as a bias using a potential generated in the operation of the differential amplifier.

In general, in the implementation of a differential amplifier using CMOS, the folding cascode structure has a low amplification, but the in-phase input has a wide operating range, strong against power supply noise, and a -dB pole depending on the output load. Because it is determined, it can have a wide frequency band, so it has been widely used as an amplifier for low voltage operation and high frequency processing.

1 is a diagram illustrating a basic cascode amplifier, in which current paths of first, second, and third NMOS transistors are connected in series between a power supply voltage VDD and a ground voltage GND, and input values different from each other. It is configured to respond to (VIN, VB1, VB2).

The cascode amplifier is used as an input terminal of a differential amplifier, and its characteristics increase the output impedance at the output terminal, have a large gain, and have a good power supply rejection ratio (PSRR) with respect to a power supply voltage. It is designed to reduce the effects of parasitic capacitance between the input and output stages of the amplifier for high frequency operation. However, a disadvantage with the use of this circuit is that the lower operating area of the output signal is limited.

FIG. 2 is a diagram illustrating a folding cascode amplifier in which the cascode amplifier of FIG. 1 is modified, in which a current path is connected between a power supply voltage VDD and a ground voltage GND and responds to an input signal VIN. It is composed of a MOS transistor M1, a PMOS transistor M2, and an NMOS transistor M3, in which a current path is connected in series between the power supply voltage and the ground voltage and responds to different input signals VB1 and VB2. have.

FIG. 3 is an application example of a differential amplifier using the folding cascode amplifier of FIG. 2 according to the prior art, and a current path is connected between a power supply voltage VDD and a first node N1, and the first node N1. A first transistor MP1 responsive to a signal of < RTI ID = 0.0 > and < / RTI > a second path MP2 connected to a current path between the power supply voltage VDD and the IS output terminal IS and responsive to a signal of the IS output terminal IS. A third transistor MP3 connected to a current path between the power supply voltage VDD and the second node N2 and responding to a signal of the IS output terminal IS; and the power supply voltage and the third node N3. A current path is connected therebetween and a fourth transistor MP4 responding to the signal of the IS output terminal IS, and a current path is connected between the power supply voltage and the output terminal VO and the signal of the first node N1. And a current path between the fifth transistor MP5 and the first node N1 and the fourth node N4. Is connected and a current path is connected between the sixth transistor MN6 and the fourth node N4 and the ground voltage VSS connected to the VB input signal VB to the signal of the second node N2. A seventh transistor MN7 that responds; an eighth transistor MN8 that connects a current path between the second node N2 and a ground voltage; and responds to a signal of the second node N2; A current path is connected between the node N3 and the fourth node N4 and is connected between the ninth transistor MP9 and the third node N3 and the fifth node N5 in response to the VP input signal VP. A current path is coupled to the tenth transistor MP10 in response to the VN input signal VN, and a current path is connected between the output terminal VO and the fifth node N5, and is connected to the VB input signal VB. A current path is connected between the eleventh transistor MN11 and the fifth node N5 and the ground voltage VSS, and responds to the signal of the second node N2. Claim 12 is composed of the transistor (MN12).

When the folding cascode amplifier of FIG. 2 is applied and used in the same drawing, the limitation of the operation region of the lower end of the output signal is the same as that of the conventional structure, and the input commom mode rage is widened. The advantage is added.

It is an object of the present invention to simplify the bias circuit of the folding cascode differential amplifier and to increase the operating range of the output stage.

In order to achieve the above object, the device of the present invention includes a first transistor connected to a power supply voltage and a first node and responding to a signal of the first node, and a current path between the power supply voltage and an IS output terminal. A second transistor coupled and responsive to a signal at the IS output stage, a third transistor coupled to a current path between the power supply voltage and a second node and responsive to a signal at the IS output stage, and between the power supply voltage and a third node. A folding cascode differential having a fourth transistor coupled to a current path and responding to a signal at the IS output stage, and a fifth transistor coupled to a current path between the power supply voltage and the output stage and responding to a signal at the first node. An amplifier, comprising: a sixth transistor coupled to a current path between the first node and a fourth node and responsive to a signal from the third node; A seventh transistor connected with a current path between the fourth node and a ground voltage and responsive to a signal of the second node; An eighth transistor connected to a current path between the second node and a ground voltage and responsive to a signal of the second node; A ninth transistor coupled with a current path between the third and fourth nodes and responsive to a VP input signal; A tenth transistor connected with a current path between the third node and a fifth node and responsive to a VN input signal; An eleventh transistor connected between the output terminal and a fifth node and responsive to a signal of the third node; And a twelfth transistor connected to a current path between the fifth node and the ground voltage and responsive to a signal of the second node.

1 is a circuit diagram illustrating a basic cascode amplifier.

FIG. 2 is a circuit diagram illustrating a folding cascode amplifier modified from the cascode amplifier of FIG. 1.

3 is a circuit diagram illustrating an application example of a differential amplifier using the folding cascode amplifier of FIG. 2 according to the related art.

4 is a circuit diagram illustrating an embodiment of a cascode differential amplifier according to the present invention.

FIG. 5 is a graph showing signal characteristics relating to an AC characteristic curve and an input and an output difference according to FIG. 4.

Hereinafter, with reference to the accompanying drawings will be described in more detail the present invention.

4 is a circuit diagram illustrating an embodiment of a cascode differential amplifier according to the present invention, in which a current path is connected between a power supply voltage VDD and a first node Nd1 and responds to a signal of the first node Nd1. A second transistor MP2 connected to the first transistor MP1, the power supply voltage and the IS output terminal IS, and responding to a signal of the IS output terminal IS, and the power supply voltage and the second transistor MP2. A current path is connected between the node Nd2 and a third transistor MP3 responding to the signal of the IS output terminal IS, and a current path is connected between the power supply voltage and the third node Nd3, and the IS output terminal is connected. A fourth transistor MP4 responsive to the signal of the IS, a fifth transistor MP5 responsive to the signal of the first node Nd1, and a current path connected between the power supply voltage and the output terminal VO; And a current path is connected between the first node Nd1 and the fourth node Nd4. A current path is connected between the sixth transistor MN6 and the fourth node Nd4 and the ground voltage VSS in response to the signal of the third node Nd3 and responds to the signal of the second node Nd2. A seventh transistor MN7, an eighth transistor MN8 connected to a current path between the second node Nd2 and the ground voltage, and responding to a signal of the second node Nd2; A current path is connected between Nd3 and the fourth node Nd4 and a current is connected between the ninth transistor MP9 and the third node Nd3 and the fifth node Nd5 that respond to the VP input signal VP. A passage is connected and a current path is connected between the tenth transistor MP10 and the output terminal VO and the fifth node Nd5 in response to the VN input signal VN and connected to the signal of the third node Nd3. A current path is connected between the eleventh transistor MN11 and the fifth node Nd5 and the ground voltage VSS, and responds to the signal of the second node Nd2. The answer is composed of the twelfth transistor MN12.

That is, a bias circuit is additionally required for the sixth transistor MN6 and the eleventh transistor MN11 to be folded in the circuit of the present invention configured as described above. The source terminal of the tenth transistors MP9 and MP10, that is, the third node Nd3, is used as the bias of the sixth and eleventh transistors MN6 and MN11.

FIG. 5 is a graph illustrating signal characteristics relating to an AC characteristic curve and an input and an output difference according to FIG. 4, which will be described with reference to FIGS. 4 and 5. In the present invention, when the third node Nd3 is used as the bias of the sixth and eleventh transistors MN6 and MN11, the AC gain is somewhat reduced depending on the operating voltage of the third node Nd3. Although there is a disadvantage, the graph of the AC gain characteristic of FIG. 5A shows that the overall DC gain is somewhat attenuated but is not a problem.

FIG. 5B shows a comparison of output characteristics when the output terminal and the negative input of the differential amplifier are connected to each other and the DC voltage is swept to the positive input, that is, when operating as a buffer. FIG. 5C is a characteristic graph, and in order to more clearly understand the difference of FIG. 5B, the difference between the output value and the input signal is immediately drawn. 5B and 5C can be interpreted from the same point of view, and it can be seen that almost the same characteristics are obtained.

FIG. 5D illustrates a voltage used as a bias voltage at the folding cascode terminal while operating the voltage of the third node Nd3 according to the present invention. In fact, the bias at the folding cascode terminal of FIG. Is to use any one point in FIG. 5B.

Therefore, as described above, in the present invention, the circuit can be simplified by not using a circuit that generates a necessary bias by basically having a folding cascode, thereby increasing the operating range of the output stage. This has the great advantage of being used as a buffer amplifier operating at high frequencies.

Claims (1)

A first transistor connected between a power supply voltage and a first node and responsive to a signal of the first node, and a second current path connected between the power supply voltage and an IS output terminal and responsive to a signal at the IS output terminal; A third transistor connected between a transistor, the power supply voltage and the second node and responding to a signal at the IS output terminal, and a current path connected between the power supply voltage and the third node and connected to a signal at the IS output terminal. A folding cascode differential amplifier having a fourth transistor in response and a current path connected between the power supply voltage and an output terminal and having a fifth transistor in response to a signal of the first node. A sixth transistor coupled between a current path and responsive to a signal of the third node; A seventh transistor connected with a current path between the fourth node and a ground voltage and responsive to a signal of the second node; An eighth transistor connected to a current path between the second node and a ground voltage and responsive to a signal of the second node; A ninth transistor coupled with a current path between the third node and a fourth node and responsive to a VP input signal; A tenth transistor connected with a current path between the third node and a fifth node and responsive to a VN input signal; An eleventh transistor connected between the output terminal and a fifth node and responsive to a signal of the third node; And a twelfth transistor coupled with a current path between the fifth node and a ground voltage and responsive to a signal of the second node.