JPH07221561A - Bias circuit and amplifier using the same - Google Patents

Abstract

PURPOSE:To achieve a high gain of an amplifier body and a wide input/output dynamic range by inserting a transistor (TR) with a high transconductance into a cascade circuit of a bias circuit so as to shift a voltage. CONSTITUTION:The bias circuit has a 1st circuit in cascade connection of N- channel transistors (TRs) TRB2 and TRB4 and a 2nd circuit in cascade connection of P-channel TRs TRB5 and TRB7 and TRs B3, B6 with high trans- conductance are inserted respectively into the 1st and 2nd circuits. Then bias voltages VB3, VB4 and VB2, VB2 are applied to them. Thus, it is possible to decrease the voltages VB3, VB2 by the TRB3, TRB6 of the 1st and 2nd circuits. Thus, a gate-source voltage of an output stage TR of cascade connection of the amplifier circuit is reduced and the saturation region in the static characteristic of the TRs is extended and a wide input dynamic range is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias circuit and an amplifier using the bias circuit, and more particularly to a bias circuit and an amplifier using the bias circuit which can achieve a wide input / output dynamic range.

[0002]

2. Description of the Related Art FIG. 12 is a schematic diagram for explaining a general subscriber system device. In the figure, 1 is a subscriber side device, and 2 is a station side device. The subscriber side device 1 is connected to a telephone terminal or the like, has a network terminating circuit 10, and is connected to a communication cable. On the other hand, the station side device 2 has an exchange 20 and a plurality of network termination circuits 21 and 22, and each of the network termination circuits 21 and 22 similarly corresponds to the subscriber side 1
Is connected to the communication cable to connect with.

Here, the distance between the subscriber-side device 1 and the station-side device 2 is very wide, ranging from 0 to several Km (7 Km on average). This also means a wide range of the amplitude of the signal transmitted through the communication cable.

Therefore, in order to deal with this, widening of the input dynamic range of the network terminating circuits 10, 21, 22 is required. Further, the network termination circuits 10, 21 and 22 perform equalization of the transmission waveform. This equalization is performed by the network termination circuit 1.
In the A / D converter provided in 0, 21, and 22,
It is performed by processing the A / D converted digital signal.

Therefore, the network termination circuits 10, 21, 22
In order to increase the input dynamic range of
It is necessary to widen the input dynamic range of the amplifier (hereinafter referred to as amplifier) mounted on the converter.

FIG. 13 shows an example of an amplifier main circuit mounted in such an A / D converter, which is a drain side balanced current output of a differential pair composed of transistors TR11 and TR12 having a common source side. Is configured to obtain a high gain voltage and an output by using a cascode type output stage as a load.

In this cascode type output stage, each of the transistors TR1 to TR4 and TR6 to TR9 is cascode connected. Furthermore, transistors TR5 and TR10
Form a differential pair, and their gates output OM and O.
It is connected to P to form common mode feedback.

In FIG. 13, VD and VS are power supplies on the drain side and the source side, respectively. VB1 to VB4 are
It is a bias voltage and VR is a fixed voltage. The bias voltages VB1 to VB4 are supplied by the conventional bias circuit shown in FIG.

Further, IM (-) and IP (+) are inputs to the amplifier body circuit, and OM and OP are outputs from the amplifier body circuit.

The conventional bias circuit shown in FIG. 14 is an N-channel transistor T formed between power supplies VD and VS.
Cascode circuit of RB2, TRB4 and P channel transistor TRB1 and P channel transistors TRB5, TRB7, T
It is composed of the cascode circuit of RB8 and TRB10.

Now, let us consider the cascode transistor circuit which constitutes the cascode type output stage of the amplifier body circuit of FIG. The cascode transistor circuit includes transistors TR1 to TR2, TR3 to TR4, TR6 to TR7.
And TR8 to TR9.

The static characteristics of the transistors used in these cascode transistor circuits are as shown in FIG. In FIG. 15, the horizontal axis represents the drain of the transistor −
The source-to-source voltage VDS and the vertical axis represent the drain current ID. Further, (i) is the gate-source voltage VGS≈900.
It is a characteristic at the time of mV. Similarly, (ii) is the characteristic when the gate-source voltage VGS ≈ 200 mV, and (ii)
i) is the characteristic when the gate-source voltage VGS≈0 mV, and thus ID≈0.

As is clear from the figure, in the saturation region of each characteristic, it is understood that VDS greatly changes with a slight change in ID.

Utilizing this characteristic, in the amplifier body circuit of FIG. 13, the current ID controlled by the input differential pair of the transistors TR11 and TR12 becomes a high gain voltage by the cascode type output stage, and the output terminal Output to OM and OP.
That is, a slight change in ID causes a large change in VDS.

However, what is important here is a high output voltage gain and a wide input / output dynamic corresponding to a case where a wide input dynamic range such as a termination network circuit is required as described with reference to FIG. It is a range.

The wide input / output dynamic range is equivalent to the wide VDS width in the saturation region in the static characteristic of FIG. The VDS width can be increased by setting VGS to a small value, as can be understood from FIG.

[0017]

The structure of the conventional bias circuit shown in FIG. 14 will be described again. Transistor TR3 of the cascode output stage of the amplifier main circuit of FIG.
Pay attention to the cascode circuit of the transistors TR4 and TR4 and the transistors TR8 and TR9, the bias voltage VB3
, VB4 are supplied from the circuit surrounded by the solid line in FIG. 14, that is, the cascode circuit of the transistors TRB2 and TRB4.

Each of the transistors TRB2 and TRB4 has a gate and a drain connected to each other, and by utilizing the voltage drop between the drain and the source, bias voltages VB3 and VB4 are supplied from the respective drains to the transistors TR3 and TR8 of the amplifier main circuit. And to the gates of transistors TR4 and TR9.

However, in order to prevent the transistor from being cut off, the voltage VDS between the drain and the source is
It is necessary to be larger than Vt + ΔV (Vt is the threshold voltage of the transistor). Therefore, when the bias voltages VB3 and VB4 are supplied from such a circuit, the transistors TR3 and TR8 and the transistors TR4 and TR9 are supplied.
It was difficult to reduce VGS of.

Further, as a result, there is a problem that the saturation region cannot be widened and therefore the dynamic range cannot be widened. In view of such a point, the present invention has an object to provide a bias circuit and an amplifier using the bias circuit, which solves the conventional problems.

[0021]

A basic configuration of a bias circuit according to the present invention has a cascode circuit in which a plurality of transistors are connected to a cascode between power supplies, and a source of a required transistor among the plurality of transistors is provided. Alternatively, it is a circuit that outputs a drain voltage as a bias voltage, and a transistor having high transconductance is inserted and connected in the cascode circuit to perform voltage shift.

In a specific mode, a cascode circuit in which a plurality of transistors are connected in cascode between the power supplies is a first circuit having a cascode connection of a plurality of N-channel transistors (TRB2, TRB4) and a plurality of P-channel transistors. A second circuit having a cascode connection of (TRB5, TRB7). Transistors (TRB3, TRB5) having high transconductance are inserted and connected in the first and second circuits, respectively.

The amplifier according to the present invention includes a differential pair of transistors (TR11, TR1) to which a balanced signal is input.
2) and this differential pair of transistors (TR11, TR12)
Of the transistors (TR1 to TR4, TR6 to T) connected to the cascode in which the drain current changes according to the output of the output and the drain-source voltage (VDS) changes correspondingly.
R9) is provided, and the bias voltage from the bias circuit, which is the basis of the present invention, is included in the cascode output stage transistors (TR1 to TR4, TR6).
~ TR9) gate.

[0024]

In the present invention, a transistor having a high transconductance is inserted in the bias voltage circuit which supplies the transistor in the cascode output stage of the amplifier circuit.

As a result, a low voltage shift is possible.
Therefore, VGS of the transistor in the cascode output stage of the amplifier circuit can be reduced. This allows
It is possible to widen the saturation region in the static characteristics of the transistor and obtain a wide input dynamic range.

[0026]

1 is a bias circuit according to a first embodiment of the present invention. This bias circuit is a circuit that supplies the corresponding bias voltage of the amplifier main body circuit described in FIG. 13. In comparison with the conventional circuit of FIG. 14, FIG. 1 is characterized by the circuit surrounded by a solid line.

That is, in FIG. 1, the transistor TRB2
A transistor TRB3 is provided between the transistors TRB4 and TRB4, and a transistor TRB6 is provided between the transistors TRB5 and TRB7. Transistors TRB2-TRB4 and TRB5-T
RB7 is different between the N-channel type and the P-channel type and has bias voltages VB3, VB4 and VB3, VB4, respectively.
To supply.

Further, the transistors TRB3 and TRB6 are
It is a high-conductance transistor. This equivalent circuit has a resistance R0 and a transfer conductance g as shown in FIG.
It is represented by the parallel connection of ds.

Further focusing on the circuit including the transistors TRB3 and TRB6, in FIG. 2, VB3−VB4 = Iref
From x (R0 / R0.gds + 1), Vt is not affected, and a low voltage shift (200 mV) can be realized by selecting a high gate voltage, gate length and width.

Therefore, the transistors TR B2 and TR
Assuming that VDS of B4 is about 1V as in the conventional circuit shown in FIG. 14, the bias voltage VB3 is lowered by about 800 mV by the transistor TRB3.

Therefore, in the amplifier main body circuit of FIG. 3, since VGS of the transistors TR3 and TR8 can be made small, the saturation region can be widened as described with reference to FIG. Therefore, it is possible to widen the dynamic range of the amplifier.

Further, in the P-channel type transistors TRB5 to TRB7 surrounded by the solid line in FIG. 1, the bias voltage VB2 can be similarly reduced by the transistor TRB6. As a result, the transistors TR2 and TR of the cascode output stage of the amplifier main circuit of FIG.
Since VGS of 7 can be made small, it is possible to widen these saturation regions.

FIG. 3 shows a second embodiment circuit of the present invention, and the same symbols as in FIG. 1 indicate the same or similar. The circuit of FIG. 3 is used as a bias circuit of the amplifier body circuit of FIG. The amplifier main circuit of FIG. 5 is characterized in that it has a differential pair of P-channel transistors TR18 and TR19 relative to the differential pair of N-channel transistors TR11 and TR12, as compared with the circuit of FIG.

On the other hand, in the bias circuit of FIG. 3, transistors TRV1 and TRV2 are inserted, and the number of stages of the transistors is adjusted to eliminate the variation in bias potential.

Further, in FIG. 3, the transistor TRP1
.About.TRP4, and these are clipped to a predetermined polarity by the power down signal (PD) so that the current of the amplifier main circuit does not flow. As a result, it is possible to obtain the effect of reducing the parasitic capacitance without providing the transistor controlled by the power down signal (PD) in the amplifier body circuit.

FIG. 4 shows a third embodiment of the present invention. In the circuit of FIG. 3, the transistor TRB1 can be eliminated by applying the potential of VPR to the transistor TRB1 and using it as a current source. is there. Further, in FIG. 4, the transistor TRB1 which determines the bias current can be replaced with a resistor.

FIG. 6 shows a bias circuit according to the fourth embodiment of the present invention. The circuit of FIG. 6 is different from the circuit of FIG. 1 in that transistors TRB11 to TRB16 are provided in parallel so that the bias voltages VB5 and VB6 can be newly supplied.

That is, the circuit of FIG. 6 has a configuration in which a large number of bias voltages need to be supplied. As shown in the figure, transistors TRB2, TRB4 and transistors TRB8, TRB10
And the transistors TRB5, TRB7 and the transistors TRB11, TRB13 are associated with each other, so that the P-channel type transistor and the P-channel type transistor and the N-channel type transistor and the N-channel type transistor are paired and folded back in multiple stages. As a result, it is possible to supply a large number of bias voltages.

FIG. 7 shows a fifth embodiment of the bias circuit of the present invention, and FIG. 8 shows an embodiment of an amplifier main circuit to which the bias circuit is connected.

In the amplifier main body circuit of FIG. 8, especially in FIG.
In comparison with the amplifier body circuit of
1 to TCM6 are further provided, and common mode feedback is applied to both the N and P channels independently of the output stage and the input stage.

That is, common mode feedback is also applied to the P channel side of the output stage by the differential pair of the transistors TCM1 and TCM2. Furthermore, the transistor TCM5
Common mode feedback is applied to both the N and P channels of the input stage by the differential pair of TCM6 and TCM6 and the differential pair of TCM3 and TCM4.

Therefore, in response to this structure, the bias circuit of FIG. 7 is provided with a transistor TRV3 in addition to the transistors TRV1 and TRV2 in comparison with FIG. In the circuits of FIGS. 7 and 8, the output common-mode potential is improved by improving the common mode feedback gain, and the design is facilitated by the input / output stage independent common mode feedback.

FIG. 9 is an application example of the present invention, and is a configuration example of the A / D converter mounted in the network terminating circuits 10, 21, and 22 described with reference to FIG. It is composed of a ΔΣ modulator 30 and a moving average filter (digital filter) 40. The bias circuit of the present invention is used for this ΔΣ modulator 30.

More specifically, the ΔΣ modulator 30 is similar to that shown in FIG.
0, an analog subtractor 31, an integrator 32 having a bias circuit of the present invention and an amplifier using the bias circuit,
It is composed of a comparator 33 and a 1-bit D / A converter 34.

With respect to the signal for each bit output as the modulation output, the difference between the output of the 1-bit D / A converter 34 and the input analog signal is output from the analog subtractor 31. This difference output is integrated by an integrator 32 having a bias circuit of the present invention and an amplifier using the bias circuit, and compared with a predetermined value by a comparator 33. Then, when the integrated output from the integrator 32 exceeds a predetermined value, a 1-bit output is sent out as the modulation result.

FIG. 11 is a block diagram showing the configuration of the integrator 32 according to the bias circuit of the present invention in FIG. 10 in more detail. In FIG. 11, 320 is a bias circuit of the present invention, and 321 is an operational amplifier composed of an amplifier main circuit to which a bias voltage is supplied by this bias circuit.

Reference numerals 322 and 323 denote capacitors. The analog switches 324 and 325, 326 and 327 are on / off controlled in pairs, and the analog input of the difference signal is sampled and stored in the capacitor 323 while being fed back to the operational amplifier 321. It is accumulated in the capacitor 322 as an integrated value. As a result, the integrated value is output from the operational amplifier 321.

Since the wide input dynamic range of the amplifier main circuit 321 can be obtained by using the bias circuit 320 of the present invention, an accurate analog integrated output can be obtained.

[0049]

As described above according to the embodiments,
With the bias circuit of the present invention, it is possible to secure the operating range of the transistor in the cascode output stage in the amplifier main body circuit in a wide saturation region. This provides an amplifier that enables high gain and a wide input / output dynamic range.

Further, by using such an amplifier in the network terminating circuit of the subscriber system device, it is possible to easily cope with variations in the distance between the subscriber side device and the station side device.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of TRB3 in FIG.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration example of an amplifier main body circuit connected to the second or third embodiment of the present invention.

FIG. 6 is a circuit diagram of a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram of a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration example of an amplifier main body circuit connected to the fifth embodiment of the present invention.

FIG. 9 is a block diagram showing an application example of the present invention.

10 is a block diagram showing a configuration example of a ΔΣ modulator of FIG. 9.

11 is a block diagram showing a configuration example of an integrator in FIG.

FIG. 12 is a schematic diagram of a subscriber system device explaining the necessity of the present invention.

FIG. 13 is a configuration example of an amplifier main circuit.

FIG. 14 is a circuit diagram showing a configuration example of a conventional vise circuit.

FIG. 15 is a static characteristic of a transistor for explaining a conventional problem.

[Explanation of symbols]

1 subscriber side device 2 station side device 20 switch 10, 21, 22 network terminating device TRB1 to TRB16 Bias circuit constituent transistors TR1 to TR19 amplifier body circuit constituent transistors VB1 to VB4 bias voltage VS source voltage VD drain voltage

Claims (9)

[Claims] 1. A bias circuit having a cascode circuit in which a plurality of transistors are connected to a cascode between power supplies, and which outputs a source or drain voltage of a required transistor among the plurality of transistors as a bias voltage. A bias circuit characterized in that a transistor having high transconductance is inserted and connected in the circuit to perform voltage shift. 2. The cascode circuit according to claim 1, wherein a plurality of transistors are connected in cascode between the power supplies, a first circuit having cascode connections of a plurality of N-channel transistors (TRB2, TRB4), and a plurality of P-channel transistors. A second circuit having a cascode connection of channel transistors (TRB5, TRB7), wherein high transconductance transistors (TRB3, TRB6) are respectively inserted and connected in the first and second circuits. Characteristic bias circuit. 3. The P-channel transistor (TRB) according to claim 2, further comprising:
1), A bias circuit characterized in that N-channel transistors (TRB8 to TRB10) are further connected to the second circuit. 4. The bias circuit according to claim 3, wherein in the first circuit, the P-channel transistor (TRB1) is replaced with a resistor. 5. The bias circuit according to claim 3, wherein in the first circuit, a predetermined gate potential is applied to the P-channel transistor (TRB1) to serve as a current source. 6. A differential pair of transistors (TR11, TR12) to which a balanced signal is input, and a drain current changes due to the outputs of the differential pair of transistors (TR11, TR12). 2. A cascode output stage having transistors (TR1 to TR4, TR6 to TR9) connected to a cascode whose source-to-source voltage (VDS) changes, wherein the bias voltage from the bias circuit according to claim 1 is the cascode output stage. Transistors (TR1 to TR4, T
An amplifier characterized in that it is supplied to the gates of R6 to TR9). 7. The bias circuit according to claim 1, wherein:
A power down signal (PD) is applied to the source or drain of a required transistor of the plurality of transistors.
7. The amplifier according to claim 6, wherein the amplifier body circuit is clipped to a polarity that does not allow current to flow. 8. The cascode output stage according to claim 6, further comprising a common mode feedback transistor (TR5, TR10),
And a transistor (TRV1, TRV2) corresponding to the cascode circuit of the bias circuit according to claim 1,
An amplifier characterized by adjusting the number of transistor stages. 9. A first differential pair of N channel transistors (TR11, TR12) to which a balanced signal is input, a second differential pair of P channel transistors (TR18, TR19), and said first and second Differential pair of transistors (TR11, TR1
2. The bias voltage from the bias circuit according to claim 1, wherein the drain current changes according to the output of (2, TR18, TR19), and the drain-source voltage (VDS) changes correspondingly. P-channel transistors (TR1, TR2, TR6, TR7) and N-channel transistors (TR3, TR4, TR8, TR9)
And a first and second common mode feedback transistors (TCM1, TCM2, TR1) of a differential pair respectively connected to the P channel side and the N channel side of the cascode output stage.
0, TR5) and the first input common mode feedback transistor (TCM5, TCM6) of the differential pair connected to the common source of the N-channel transistors (TR11, TR12) of the first differential pair, and the second An amplifier having a second pair of common mode feedback transistors (TCM3, TCM4) on the input side of the differential pair connected to the common drain of the P-channel transistors (TR18, TR19) of the differential pair.