JPS61248608A - Differential amplifier - Google Patents

Abstract

PURPOSE:To obtain a differential amplifier with an excellent common mode input voltage rejection ratio characteristic, having an excellent high speed characteristic and a low offset voltage by constituting the titled amplifier with a folded type full differential amplifier circuit comprising a couple of circuits and with a bias circuit so as to apply a positive input and a negative input to a gate of an input MOSFET of the bias circuit. CONSTITUTION:When voltages slightly different are fed respectively to input terminals 78 and 79, an amplified voltage is produced to drains 82, 83. Further, a signal amplified further is produced between output terminals 80, 81 by constant current source transistors (TRs) 67, 68 and cascode TRs 62, 63. When a common mode voltage is applied respectively to input terminals 78, 79, since an input voltage equal to that at the input terminals 78, 79 is fed to an input TR 64 of the bias circuit, a potential at a terminal 84 is equal to a position at drains 82, 83 of MOSFETs 60, 61. Thus, the potential at output terminals 80, 81 is equal to a potential at a terminal 86, an excellent common mode input signal rejection ratio is attained and the offset voltage becomes a very small value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differential amplifier having high-speed operation characteristics and excellent common-mode input rejection ratio and input offset voltage characteristics.

[Summary of the Disclosure] The present invention provides a differential amplifier configured with MOSFETs, including a first folded fully differential amplifier circuit consisting of a pair of circuits in which cascode MOSFETs are arranged symmetrically, and a pair of circuits in which cascode MOSFETs are arranged symmetrically. 2 or 1 input MO in the second folded fully differential amplifier circuit or the fully differential amplifier circuit consisting of the circuit
A bias circuit in which the average value of the positive input and negative input is applied to the gate of the 8FET, and the gate and drain of the cascode MOSFET are connected, and the connection point forms a bias voltage, and the bias voltage formed by the bias circuit. By applying the voltage to the gates of the pair of cascode MOSFETs in the second folded fully differential amplifier circuit, it is possible to suppress the input offset voltage without being affected by manufacturing process variations, and moreover, The present invention discloses a technique that has an excellent input voltage rejection ratio.

Note that this summary is provided solely for the purpose of quickly accessing the technical content of the present invention, and does not have any influence on the technical scope of the present invention or the interpretation of rights.

[Prior Art] In recent years, there has been a demand for differential amplifiers capable of high-speed operation in video signal processing and the like.

The IEEE Journal satisfies this requirement.
alof 5olid 5tate C1rcuit,
IH3 year Vo1.18. No, Ei.

pp. 852-1383 “Old gh-Frequency”
y CMO95w1tched-Capacitor
Filters for Communication
Cascode MOSF for sApplication J
Folded fully differential amplifiers using ET are TAT C, C
It has been proposed by tIOI et al.

In the case of this circuit, there are problems in that there are restrictions in circuit design in determining an appropriate DC operating point and that a sufficient common-mode input rejection ratio cannot be obtained.

Also, IEEE Journal of 5olid
5tate circuit.

! 883, Vo1.18. No, θ, PP, 700
-708 rAcMosSwitched-Capac
Itor Variabie 1jne Equ
AlizerJ discloses a differential amplifier proposed by Toshiro Izuzuki et al., but it is insufficient in terms of high-speed operation.

The folded fully differential amplifier described above will be described in detail using FIG. 4. In Figure 4, 1 to 5
is a constant current source, 8.7 is input NO! JFET, 8.9 is input terminal pair, 10.11 is cascode MOSFET, 12
．． 13 is an output terminal pair, 14.15 is MOSFETIO,
Terminal for bias voltage applied to the gate of 11, 16-1
8 is each bias terminal for constant current sources 3-5.

The output point of the differential amplifier shown in Figure 4! The voltage at terminal 3 cannot take a value near the intermediate value between terminals 15 and 18 unless the current supply capabilities of constant current source 5 and cascode MOSFET II match, and the voltage at The MOSFET that is currently in use will no longer operate in the saturation current region, resulting in a decrease in voltage gain and an increase in input offset voltage.

Furthermore, to solve this problem, even if the bias voltages applied to terminals 14 and 1B, and 15 and 18, and the sizes of cascode MOSFETIO and 11 are optimally selected, slight manufacturing variations in MOSFET characteristics will cause The DC operating point will be significantly different from the design value.

Furthermore, the common-mode input voltage rejection ratio characteristics should be improved. An example of a conventionally used circuit is shown in FIG. Here, the same parts as in FIG. 4 are given the same reference numerals. In FIG. 5, constant current sources 1 to 5, input MOSFET B, 7, input terminal pair 8, 8, cascode MOSFET 10.11, output terminal pair 12, 13, and bias input terminal 14.15 are arranged in the same manner as in FIG. has been done. In this example, MOSFETs 20 to 23 that operate in a resistive region are connected to constant current sources 3 and 3, respectively.
Connect to ~5. That is, these MOSFET20.
Connect the drains and sources of 21, 22, and 23 between each constant current @3.4 and 5 and the common potential Vss,
Each gate of MOSFET 20 and 23 is connected to output terminal 12.
and 13 respectively, and grounding the gates of MOSFETs 21 and 22 to give a negative feedback effect to the voltages at output points 12 and 13.
Attempts to improve common-mode input rejection characteristics.

However, sufficient effects are not necessarily obtained.

Furthermore, when trying to improve these characteristics, sufficient high-speed characteristics cannot be obtained.

[Problems to be Solved by the Invention] Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a method having good high-speed operation characteristics, low offset voltage, and excellent common-mode input voltage rejection ratio characteristics. The purpose of this invention is to provide a dynamic amplifier.

[Means for solving the problem] In order to achieve the above object, the differential amplifier of the present invention includes a folded fully differential amplifier circuit and its cascode MOS.
It consists of the entire second folded fully differential amplifier circuit or only one of its symmetrical circuits to generate the bias voltage of the FET, and the average value of the positive input and negative input is input to the MOSFET.
It consists of a bias circuit applied to ET.

That is, the present invention provides a first folded fully differential amplifier circuit consisting of a pair of circuits in which cascode MOSFETs are arranged symmetrically, and a cascode No. A positive input and a negative input are connected to the gates of two or one input MOSFET in a second folded fully differential amplifier circuit or one circuit in a fully differential amplifier circuit consisting of a pair of circuits in which 3FETs are arranged symmetrically. A bias circuit is applied, and the gate and drain of the cascode MOSFET are connected, and the connection point forms a bias voltage. It is characterized by comprising means for applying voltage to the gates of a pair of cascode MOSFETs therein.

Here, the positive and negative inputs can be applied to the gate of the input MOSFET of the bias circuit via a resistor or resistive device.

[Function] In the bias circuit according to the present invention, when the differential input is zero, the current ratio on the input MO8FET and cascode MOSFET sides is equal to the current ratio on the fully differential amplifier circuit side. In other words, equivalent terminals of the fully differential amplifier circuit and the bias circuit are configured to always show the same voltage, and the input offset voltage becomes extremely small.

Furthermore, since the input MOSFET gate on the bias circuit side is configured so that an intermediate value between the positive input and the negative input is input, even if a common-mode input signal is input, the input MOSFET gate on the differential amplifier circuit side and the bias circuit The electrodeposition ratio flowing through the side equivalent element does not change, resulting in a very small voltage gain in this case and excellent common mode input signal rejection.

Furthermore, in the differential amplifier of the present invention, the cascode MOSFE
Since the bias voltage applied to T varies in accordance with the input voltage level, a much wider input signal voltage range can be obtained than when using a fixed bias.

[Example] The present invention will be described in detail below with reference to the drawings.

An example of the differential amplifier of the present invention is shown in FIG. Here the fourth
The same parts as in the figure are given the same reference numerals.

In FIG. 1, block B1 shows the main part of a fully differential amplifier, and block B2 shows a bias circuit part for supplying bias voltage to MOSFETs 30 and 31 forming a cascode transistor circuit in block B1. 32 and 33 are MOSFEs as input transistors
T, 34 and 35 are input transistors 32 and 33
An input terminal 38 is a MOSFET that forms a cascode transistor circuit together with MOSFETs 30 and 31. 3
7 to 44 are constant current sources, 45.48.47 are constant current sources 311.41, 43, 44; 40.37, 38.4, respectively.
2 shows the bias voltage line that supplies the voltage.

To explain in more detail, the differential amplifier of the present invention includes a folded fully differential amplifier circuit B1 consisting of a pair of circuits with a symmetrical structure looking at the cascode MOSFETs 30 and 31, and each gate of the cascode MOSFETs 30 and 31.
・Bias circuit B2 for applying to 48.411
It consists of This bias circuit B2 is a folded fully differential amplifier circuit consisting of a pair of circuits □ or one of the circuits includes a cascode MO
The gate 50 and drain 51 of the SFET 36 are connected together, and the voltage at the connection point between the gate 50 and the drain 51 is used as the bias voltage applied to the gate 48.49 of the cascode MOSFET 30.31. moreover,
Two or one input MO included in bias circuit B2
A positive input 56 and a negative input 57 are applied to the gate 53 of SFET 52 via resistors or resistive devices 54 and 55 such that the average value of the positive and negative inputs is applied. 58 and 59 are differential output terminals.

In bias circuit B2, when the differential input is zero, the input M
The current ratio on the OSFET 52 and cascode MOSFET 3B sides is equal to the current ratio on the fully differential amplifier circuit Bl side. In other words, equivalent terminals of the fully differential amplifier circuit Bl and the bias circuit B2 are configured to always show the same voltage, and as a result, the input offset voltage becomes extremely small.

That is, in the bias circuit B2 of the present invention, by connecting the gate 50 and drain 51 of the cascode MOSFET 3B, it has the same function as a current mirror circuit for the cascode MOSFET 30 and 31 on the fully differential amplifier circuit Bl side. As a result, the current supply capabilities of the constant current source 41 and the cascode MOSFET 31 in FIG. It turns out.

Furthermore, since the input MOSFET gate 53 on the bias circuit B2 side is configured so that an intermediate value between the positive input 56 and the negative input 57 is input, even if a common-mode input signal is input, the fully differential amplification Circuit Bl side and bias circuit B
The ratio of currents flowing through the equivalent elements on the two sides does not change, and as a result the voltage gain in this case is very small and the common mode input signal rejection ratio is excellent.

Furthermore, in this differential amplifier, the cascode MOSFET
Since the bias voltages applied to 30 and 31 vary in accordance with the input voltage level, a much wider input signal voltage range can be obtained than when using a fixed bias.

FIG. 2 is a circuit diagram showing a specific example of the present invention.

In FIG. 2, No. 5 FETs 80, 81, and 64 are input transistors in a fully differential amplifier circuit and a bias circuit, respectively. No. 9 FETs 82, 63, and 65 are cascode transistors in the fully differential amplifier circuit and bias circuit, respectively.

MOSFET fi8 to 74 are constant voltage* source transistors,
No9FET75 is MOSFETθ8~[18,71,
A transistor for supplying a bias voltage to 72, M
OSFET? 8.77 is a constant current source transistor 69.
This is a transistor pair for supplying bias voltage to 70, 73, and 74. 78 and 713 are input terminal pairs; 80.
81 is a pair of output terminals.

The operation of the embodiment of the present invention shown in FIG. 2 will be described in detail below.

Applying slightly different voltages to input terminals 78 and 79 produces an amplified voltage at each drain 82 and 83 because the sources 85 of input quadrants 0 and 61 are commonly connected. Further, constant current source transistors 87, 68 and cascode transistors 82, 83
As a result, a further amplified signal is generated between output terminals 80 and 81.

When common mode voltages are applied to input terminals 78 and 79, respectively, no voltage difference occurs between drains 82 and 83. Since an input voltage equal to that of the input terminals 78 and 78 can be applied to the input quadrant transistor 4 on the bias circuit side, the potential of the terminal 84 is MO! 1liFET80 and 61
becomes equal to the potential of drains 82 and 83 of . Therefore, the potentials of the output terminals 80 and 81 are equal to the potential of the terminal 86, and the in-phase input signal rejection ratio is excellent, and the offset voltage is also a very small value.

In the figure, 87 is a positive input, 88 is a negative input, 89 and 80 are resistive devices, and 91 and 92 are phase compensation capacitors.

Furthermore, since the bias voltage applied to the gates of the cascode MOSFETs 82 and 83 changes in accordance with the common-mode input signal, the common-mode input voltage range is wide.

FIG. 3 is a circuit diagram showing another embodiment of the present invention. Third
In the figure, No. 9 FETs 100, 101 and 102
are the input transistors in the fully differential amplifier circuit and the bias circuit, respectively.No9FET103, +04 and 105 are the cascode transistors and MOSFETs in the fully differential amplifier circuit and the bias circuit, respectively.
I08~11J123.124 are constant current source transistors, MOSFET117~120 are MOSFET101
Transistors, MOSFETs 121, 1 for supplying bias voltages to 3 to 111°123.124, respectively
22 is a transistor for supplying bias voltage to MOSFETs 112 to 11B. 125, 126 are input terminals, 127, 128, 129 are input transistors 1
00, 101, and 102, 130 and 131 are output terminals, and 132 and 133 are the drain and gate of the cascode transistor 105, respectively. 134 is a positive input, 135 is a negative input, 13B and 137 are resistive devices, and 138 and 139 are phase compensation capacitors.

The circuit in FIG. 3 is different from the circuit in FIG.
This is because OSFETs 117 and 118 are added. These constant current source MOSFETs 123 and 124 have the effect of significantly increasing the load impedance of the output terminals 130 and 131, and therefore serve as an effective means for improving the voltage gain of the amplifier. That is, the second
The only difference in performance between the circuits shown in FIG. 3 and FIG. 3 is the voltage gain, and the characteristics of input voltage offset and common-mode input voltage rejection ratio remain unchanged. Note that when using a conventional bias circuit, the gain bandwidth edge was 80 Meg, but by using the present invention, it was improved to 120 Meg without deteriorating the common-mode input voltage rejection ratio.

Note that similar performance can be obtained even when the n-channel MOSFET and the p-channel MOSFET are complementarily replaced in the circuits of FIGS. 2 and 3.

Furthermore, the present invention can be applied without deteriorating the impedance seen from the signal source side by adding a buffer stage to the signal supply end of a resistive device that adds positive and negative input signals of the bias circuit to create an intermediate value. is clear.

[Effects of the Invention] As is clear from the above, the differential amplifier circuit of the present invention can suppress the input offset voltage without being affected by manufacturing process variations, and has an excellent common-mode input voltage rejection ratio. Therefore, since the size of each transistor can be freely selected independently, the gain and frequency band characteristics can be optimized in relation to the offset voltage and common-mode input voltage rejection ratio characteristics, making it extremely easy to design a differential amplifier circuit. , and the frequency band characteristics and voltage gain characteristics are significantly improved compared to conventional circuits.

Moreover, the input voltage range is also widened, and as a result, it can be used even if the supplied power supply voltage is almost half of the conventional value, which has the advantage of being able to be used effectively for low-voltage equipment.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of the configuration of the folded fully differential amplifier of the present invention, FIG. 2 is a circuit diagram showing a specific example of the folded fully differential amplifier of the present invention, and FIG. 3 is the folded type of the present invention. A circuit diagram showing another specific example of a fully differential amplifier. Figure 4 is a circuit diagram showing the configuration of a conventional folded fully differential amplifier. Figure 5 is a circuit diagram showing a configuration of a conventional folded fully differential amplifier FIG. 32.33.52...Input transistor, 30.31
．． 38... Cascode transistor, 34... Negative input, 35... Positive input, 37-44... Constant current source transistor, 45.48
．． 4? ...Bias voltage line, 48.411.50
...Gate, 51...Drain, 53...Gate, 54.55...Resistive device, 58.59...Output terminal.

Claims (1)

[Claims] 1) A first folded fully differential amplifier circuit consisting of a pair of circuits in which cascode MOSFETs are arranged symmetrically, and a second folded fully differential amplifier circuit consisting of a pair of circuits in which cascode MOSFETs are arranged symmetrically. In one circuit of the differential amplifier circuit or the fully differential amplifier circuit, the average value of the positive input and negative input is applied to the gates of two or one input MOSFET, and the gate and drain of the cascode MOSFET are applied. a bias circuit whose connection point forms a bias voltage; and a pair of cascode MOSFETs in the second folded fully differential amplifier circuit that transmits the bias voltage formed by the bias circuit.
1. A differential amplifier comprising: means for applying voltage to a gate of an ET. 2) The positive input and the negative input are connected to the input MOSFET of the bias circuit via a resistor or a resistive device.
2. The differential amplifier according to claim 1, wherein the voltage is applied to the gate of the differential amplifier.