KR19980054988A - Method of manufacturing thin film transistor - Google Patents

Abstract

A thin film transistor manufacturing method according to the present invention comprises the steps of sequentially forming a gate insulating layer, a semiconductor layer and an etch stopper layer on a substrate having a gate electrode; Forming a photoresist pattern on the etch stopper layer on the gate electrode; Forming an etch stopper layer having a shape in which a side center portion is undercut using the photosensitive film pattern as a mask; Sequentially forming an n ⁺ amorphous silicon layer and a metal wiring layer on the photoresist pattern and the semiconductor layer so that the undercut portion of the etch stopper layer is exposed; Removing the etch stopper layer of the undercut portion exposed by the wet etching method; Etching the metal wiring layer, the n ⁺ amorphous silicon layer, and the semiconductor layer to form a source / drain electrode and a channel so that the surface of the gate insulating layer is partially exposed, and the number of masks required for the etching process is one sheet. This can reduce costs and improve productivity, as well as eliminate defects caused by device manufacturing (eg, silica formation, water droplet defects, misalignment, etc.).

Description

Method of manufacturing thin film transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor used as an active element such as a liquid crystal display device (hereinafter referred to as an LCD device), and more particularly, to an etch stopper layer (protective insulating layer). The present invention relates to a bottom gate type thin film transistor manufacturing method for improving productivity and cost reduction by improving a manufacturing process of a thin film transistor having a thin film transistor.

Recently, with the development of new high-tech video devices such as high definition TVs (hereinafter referred to as HDTVs), there is a demand for flat panel displays. LCD is a representative technology of flat panel display, and it does not have problems such as colorization, low power, and high speed that ELD (electro luminescence display), VFD (vacuum fluorescence display), PDP (plasma display panel) cannot solve. The LCD is divided into two types, passive and active. The active LCD is controlled by an active element such as a thin film transistor to control each pixel one by one, which is far superior to the passive LCD in speed, field of view, and contrast. It is used as the best indicator for HDTV that requires a resolution of 1 million pixels or more. Accordingly, the importance of the thin film transistor is increasing, and the research and development thereof is intensifying.

Currently, research and development on thin film transistors, which are used as electrical switching elements for selective driving of pixel electrodes in LCDs, focus on reducing the manufacturing cost by improving yield and improving productivity, thereby improving transistor structure, amorphous or polycrystalline silicon. The focus is on improving the properties, ohmic contact resistance of electrodes, and preventing disconnection / short circuits. Among these, the technology of amorphous silicon thin film transistor is being studied more because of large area, low cost and mass production.

Amorphous thin film transistors used in the current manufacturing line is largely divided into two types depending on the structure of the gate. One is a bottom gate type, also called an inverse stagger type, and the other is a top gate type, also called a forward stagger type.

Forming a gate electrode first on a substrate is called a bottom gate type and forms a main species. On the other hand, the top gate type first forms the source / drain electrodes of the thin film transistor, and in reality, it is not used much because of the large leakage current and lack of mass productivity.

The bottom gate type is divided into two types. 1 and 2 are cross-sectional views showing the structure of these two types of bottom gate type amorphous silicon thin film transistors. 1 shows an etch back type thin film transistor structure, and FIG. 2 shows an etch stopper type thin film transistor structure.

In the etching back type thin film transistor of FIG. 1, a gate insulating layer (e.g., an SiN _X layer) 14, a semiconductor layer (e.g., an a-Si layer) is formed on a gate electrode 12 formed on the glass substrate 10 ( 16, n ⁺ amorphous silicon (e.g., n ⁺ a-Si layer) 18, and a source / drain electrode 20 are continuously stacked, and the etch stopper type thin film transistor of FIG. 12, a gate insulating layer 14, a semiconductor layer 16, an etch stopper layer (e.g., a SiN _X layer) 17 as an insulating film, an n ⁺ amorphous silicon layer 18, and a source / drain electrode 20 are continuous. It has a laminated structure.

In the case of using the etch stopper type thin film transistor, the etch stopper layer formed for the purpose of preventing damage to the semiconductor layer is first, since the semiconductor layer can be protected from the etching process, so that the thickness of the semiconductor layer can be minimized. It is possible to improve the on / off current value characteristics of the thin film transistor, and secondly, to reduce the value of the parasitic capacitance at the portion where the gate and the source / drain electrodes cross. Third, even when the back light exposure is gradually increased, the effect of the semiconductor layer due to light can be minimized, so that the light current can be reduced, and compared with the case of using the etch back type thin film transistor. It has the advantage of improving the characteristics of the thin film transistor.

The method of manufacturing an etch stopper type thin film transistor having the above characteristics will be briefly described with reference to the cross-sectional view shown in FIG. 2.

As a first step, after forming the gate electrode 12 on the glass substrate 10 by using a mask, the gate insulating layer 14 as an active layer on the entire surface of the substrate 10 including the gate electrode 12. The semiconductor layer 16 and the etch stopper layer 17 are successively deposited. In this case, the etch stopper layer 17 serves to prevent damage to the semiconductor layer 16 from overetching in a subsequent process.

As a second step, a photoresist film is deposited on the etch stopper layer 17, and a predetermined photoresist pattern is formed only on the etch stopper layer 17 on the gate electrode 12 by a photolithography process using a mask. The etch stopper layer 17 is patterned using a mask, and then the photoresist pattern is removed.

As a third step, the entire surface of the substrate is cleaned with an HF solution, an n ⁺ amorphous silicon layer 18 for ohmic contact and a metal wiring layer (e.g., on the semiconductor layer 16 including the patterned etch stopper layer 17). , Al layer) is continuously deposited, and then a photoresist pattern is formed on the metallization layer by a photolithography process using a mask. Subsequently, the metal wiring layer is etched using the photoresist pattern as a mask to form a source / drain electrode 20, and then the photoresist pattern is removed, and n ⁺ amorphous silicon between the channel portions, that is, the source / drain 20, is removed. The layer 18 is removed using reactive ion etching (RIE) to complete the manufacture of one thin film transistor.

However, in the case of manufacturing the thin film transistor using the above process, first, since the etching process using a mask is required three times (e.g., forming a gate electrode, patterning an etch stopper layer, and forming a source / drain electrode) during the process. 3 masks are required to increase the manufacturing cost. Second, during the cleaning process using HF solution, SiN _X constituting the etch stopper layer is partially dissolved in the HF solution. Residues in which SiN _X is dissolved flow into the back to form silica, which causes process defects during the subsequent process. Third, a part of the surface of the surface is exposed to the amorphous silicon layer, which is a semiconductor layer, during the process. It is a thin natural oxide film (e.g., silicon oxide film) formed on the case to deposit the n ⁺ amorphous silicon layer over the natural oxide Due to the poor adhesion to the surface, the surface is excited, resulting in water droplet defects that appear as if water droplets are formed. Fourth, misalignment occurs when the etch stopper layer is patterned. As a result, the reliability of the thin film transistor is reduced.

Therefore, the present invention was devised to improve the above-mentioned disadvantages, and by using the back exposure during the process, the self-aligning thin film transistor can realize the reduction in the number of masks and the resulting cost reduction. The purpose is to provide a manufacturing method.

1 is a cross-sectional view showing a structure of a thin film transistor of an etch back type according to the prior art;

2 is a cross-sectional view showing a structure of an etch stopper type thin film transistor according to the prior art;

Figure 3 (A) to Figure 3 (F) is a process flowchart showing a thin film transistor manufacturing method according to the present invention.

A thin film transistor manufacturing method according to the present invention for achieving the above object comprises the steps of sequentially forming a gate insulating layer, a semiconductor layer and an etch stopper layer on a substrate provided with a gate electrode; Forming a photoresist pattern on the etch stopper layer on the gate electrode; Forming an etch stopper layer having a shape in which a side center portion is undercut using the photosensitive film pattern as a mask; Sequentially forming an n ⁺ amorphous silicon layer and a metal wiring layer on the photoresist pattern and the semiconductor layer so that the undercut portion of the etch stopper layer is exposed; Removing the etch stopper layer of the undercut portion exposed by the wet etching method; Forming a source / drain electrode and a channel by etching the metal wiring layer, the n ⁺ amorphous silicon layer, and the semiconductor layer so that the surface of the gate insulating layer is partially exposed.

As a result of this process, the number of masks can be reduced by one, so that cost reduction can be realized, and a thin film transistor of a self-aligned type can be manufactured by an etching process using a back exposure.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

The present invention focuses on manufacturing a thin film transistor which can eliminate the defects of the device such as silica formation, water droplet defects, and misalignment, and at the same time realize cost reduction by reducing the number of masks. Looking in detail using the process purity shown in A) to Figure 3 (F) as follows. The thin film transistor manufacturing method according to the present invention is largely divided into six process steps, which will be described by dividing step by step. Each process corresponds to FIG. 3 (A)-(F).

As a first step, as shown in FIG. 3A, a metal layer is deposited on a substrate (eg, a glass substrate) 100, and then the metal layer is etched by a photolithography process using a mask to form a gate electrode 102. To form. At this time, examples of the metal constituting the gate electrode 102 include Al, Ta, W, Cr, and the like. Subsequently, SiN _X , which is the gate insulating layer 104, and amorphous silicon, which is the semiconductor layer 106, are sequentially deposited on the entire surface of the substrate 100 on which the gate electrode 102 is formed.

As a second step, as shown in Fig. 3B, an etch stopper layer 108, SiN _X , is deposited on the semiconductor layer 106 to a thickness of 7000 Å or more, and then onto the etch stopper layer 108. The photoresist film is deposited, and back exposure is performed so that the photoresist film remains only on the etch stopper layer 108 on the gate electrode 102 to form the photoresist pattern 110.

As a third step, as shown in Fig. 3C, the etch stopper layer 108 below the photoresist pattern 110 is used as a mask to be etched by dry etching. In this case, the etching process is performed by adjusting the amount of etching so that full etching is performed on both sides of the etch stopper layer 108. As a result, the interface with the photosensitive film pattern 110 cannot be etched, and the center can be concave. Therefore, a severe under-cut occurs in the central portion of the lateral side of the etch stopper layer 108.

As a fourth step, as shown in FIG. 3D, n ⁺ amorphous silicon and Cr, a metal wiring material, are sequentially sputtered from the upper side of the photoresist pattern 110 toward the substrate, thereby forming the photoresist pattern 110 and the photoresist layer. The n ⁺ amorphous silicon layer 112 and the metallization layer 114 of a predetermined thickness are successively deposited on the semiconductor layer 106. At this time, the n ⁺ amorphous silicon layer 112 and the metal wiring layer 114 are not applied to the undercut portion of the side of the etch stopper layer 108, and the surface thereof is exposed, so that the n ⁺ amorphous silicon layer ( 112 and a pattern having a structure in which the metal wiring layer 114 is broken.

In this case, the process of sputtering the n ⁺ amorphous silicon layer 112 and the metallization layer 114 is a deposition process in a fast time in the same chamber so that a natural oxide film is not grown on the semiconductor layer 106 after wet etching. Is carried out.

As a fifth step, wet etching is performed using the HF solution as shown in FIG. As a result, the undercut portion of the etch stopper layer 108 with its exposed surface is melted away by the HF solution. Accordingly, the photoresist pattern 110 and the n ⁺ amorphous silicon layer 112 and the metal wiring layer 114 deposited thereon may also be dropped, and the spaced apart portions may have a self-aligned structure. .

In this case, the etching process is performed using the HF solution, but since the n ⁺ amorphous silicon layer 112 and the metal wiring layer 114 are already formed on the semiconductor layer during the etching process, the etch stopper is used. Residues in which the SiN _X melted layer 108 is not attached to the pattern valleys of the semiconductor layer 106 may be prevented from forming silica, and at the same time, a surface cleaning effect may be obtained.

As a sixth step, as shown in FIG. 3F, a photoresist pattern is formed on a predetermined portion on the metal wiring layer 114, and the metal wiring layer 114 is etched by a photolithography process using the mask as a source / drain. The thin film transistor according to the present invention is completed by forming an electrode and forming a channel by successively etching the n ⁺ amorphous silicon layer 112 and the semiconductor layer 106 under the mask as a mask.

In the case of performing the process as described above, the mask is used only when forming a gate electrode on the substrate 100 and when forming a source / drain electrode in the present invention, whereas three masks are conventionally required. Since the number of masks can be reduced by one compared with the related art, cost reduction and productivity improvement can be realized.

In the present process, after etching the etching stopper layer 108 at the lower portion of the photoresist layer 110 using a mask as a mask in a third step by using a dry etching method, the photoresist layer pattern 110 is removed, and As in step 4, the process may be sequentially performed in order of sputtering n ⁺ amorphous silicon and Cr, which is a metallization material, to obtain the same effects as mentioned above.

As described above, according to the present invention, first, since the etching process using the mask is required twice when manufacturing the thin film transistor, the number of masks can be reduced by one compared with the conventional case, thereby achieving cost reduction and thus productivity. able to talk to an improved, second, to use HF solution during wet etching, but because it is the state in which the etching process when already n ⁺ amorphous silicon layer and a metal wiring layer on the semiconductor layer is formed, to a SiN _X melted residues semiconductor Since it can not be attached to the pattern bone of the layer, it is possible to prevent the formation of silica and at the same time to obtain a cleaning effect. Third, the process of forming an n ⁺ amorphous silicon layer and a metal wiring layer on the amorphous silicon layer, which is a semiconductor layer, is performed. The sputtering method is performed in the same chamber in a short time so that the amorphous silicon layer can be It is possible to suppress the growth of the natural oxide film, thereby preventing water droplet defects caused by poor adhesion with the natural oxide film. Fourth, since the process is performed using the back exposure, the thin film transistor can be formed by the self-aligning method. As a result, element defect factors such as misalignment and the like can be eliminated, thereby improving device characteristics of the thin film transistor.

Claims (8)

Sequentially forming a gate insulating layer, a semiconductor layer, and an etch stopper layer on the substrate provided with the gate electrode; Forming a photoresist pattern on the etch stopper layer on the gate electrode; Etching the etch stopper layer using the photosensitive film pattern as a mask to undercut the central portion of the side surface; Sequentially forming an n ⁺ amorphous silicon layer and a metal wiring layer on the photoresist pattern and the semiconductor layer so that the undercut portion of the etch stopper layer is exposed; Removing the exposed undercut portion of the etch stopper layer by wet etching; Forming a source / drain electrode and a channel by etching the metal wiring layer, the n ⁺ amorphous silicon layer, and the semiconductor layer so that the surface of the gate insulating layer is partially exposed. The method of claim 1, wherein the etch stopper layer is formed to have a thickness of 7000 kPa or more. The method of claim 1, further comprising etching the etch stopper layer such that the center portion of the side surface is undercut by using the photoresist pattern as a mask, and then removing the photoresist pattern. The method of claim 1, wherein the photoresist pattern is formed by back exposure. The method of claim 1, wherein the etching stopper layer is etched by a dry etching method so as to undercut the central portion of the side surface. The method of claim 1, wherein the n ⁺ amorphous silicon layer and the metallization layer are formed by a sputtering method. The method of claim 1, wherein the metal wiring layer is formed of Cr. The method of claim 1, wherein the wet etching is performed by using an HF solution.