KR19980054677A - ATM Cell Generator in ATM Switching System - Google Patents

Abstract

The present invention relates to an apparatus for generating an ATM cell for processing a message transmitted and received to a host system by an ATM method and matching with a taxi (TAXI) bus.

This device of the present invention comprises a dual port memory 228 for registration with the bus; Transmission control memory 220; Transmit packet memory 222; A SAR transmission chip (230) operated by control data set in the transmission control memory to generate an ATM cell by dividing a message received in the transmission packet memory from an upper system; Transmit FIFOs 234 and 236; Taxi transmission chips 240 and 242 for transmitting data of the transmission FIFO at high speed; Taxi reception chips 244 and 246 for reproducing a signal received through a taxi bus and outputting an ATM cell; Receiving FIFO 238; Reception control memory 224; Received packet memory 224; And a SAR receiving chip operated by the control data set in the reception control memory to analyze an ATM cell inputted from the reception FIFO to check an error, reassemble a payload, reproduce a message, and store the message in the reception packet memory. 232) to enable high speed communication.

Description

ATM Cell Generator in ATM Switching System

The present invention relates to an apparatus for generating an ATM cell in an ATM switch, and more particularly, to an apparatus for generating an ATM cell in order to match a taxi (TAXI) bus by processing a message transmitted and received to an upper system by an ATM method.

In general, exchanges include the ability to operate and maintain the exchange system, which is implemented using a processor (OMP) within the exchange system or connected to a workstation (W / S: Workstation) or a personal computer (PC).

In other words, functions related to operation and maintenance in the exchange system are intensively performed by the operation and maintenance processor (OMP), and the connection between the operator's console (or personal computer) and the exchange system is made by RS232C. As described above, since RS232C has a transmission speed of about 9600bps, high-speed data transmission is difficult.

Therefore, it is desirable to use a high-performance computer such as a workstation as a console for operation and maintenance, and to be connected to the switching system by ATM. As such, in order to access an ATM console from an operation and maintenance system in an ATM exchanger, a device for generating an ATM cell while being connected to a switching network side and a taxi (TAXI) method is required.

Accordingly, the present invention has been made in order to meet the above necessity, by dividing the message received from the upper system to form an ATM cell to communicate via the ATM switch and output through a taxi (TAXI) bus, An object of the present invention is to provide an ATM cell generator for assembling an ATM cell received through a taxi (TAXI) bus and delivering it to an upper system.

In order to achieve the above object, the apparatus of the present invention, in the device for connecting to the switch network via a taxi (TAXI) bus to the upper system connected via the S bus, ATM for matching with the bus Dual port memory; A transmission control memory that stores control data for controlling transmission; A transmission packet memory for storing message data for transmission; A segmentation and recombination (SAR) transmitting chip that is operated by control data set in the transmission control memory and divides a message received from the upper system into the transmission packet memory to generate an ATM cell; A first-in, first-out buffer (FIFO) for storing ATM cell data formed by the SAR transmission chip; A taxi (TAXI) transmission chip for transmitting data of the transmission FIFO at high speed; A TAXI receiving chip for reproducing a signal received through a TAXI bus and outputting an ATM cell; A first-in, first-out buffer (FIFO) for storing received data of the TAXI receiving chip; A reception control memory that stores control data for controlling reception; A received packet memory for storing the reassembled message data; A partitioning and recombination operation performed by the control data set in the reception control memory to analyze an ATM cell inputted from the reception FIFO to check an error, reassemble a payload, and reproduce a message, and then store the message in the reception packet memory ( SAR) is characterized by consisting of a receiving chip.

1 is a block diagram showing the overall configuration of an ATM switch to which the present invention is applied;

2 is a detailed block diagram showing an ATM cell generator shown in FIG. 1;

3 is a block diagram illustrating a TAXI transmission chip shown in FIG. 2;

FIG. 4 is a block diagram illustrating a TAXI receiving chip shown in FIG. 2.

* Explanation of symbols for main parts of the drawings

110: ATM local exchange subscriber system 111, 112: subscriber matching module

113: access switching network module 114: call processing processor

120: ATM local exchange trunk system 121,122: trunk matching module

131: interconnection switch network module 132: operation and maintenance processor

133: multiplexing and switch matching device 134: ATM cell generator

135: peripheral device matching unit 136: disk

200: processor 202,204: memory

210,212,214,216,217,218: buffer 220,224: control memory

222,226: packet memory 228: dual port memory

230: SAR transmitting chip 232: SAR receiving chip

234,236: FIFO 240,242,244,246: taxi chip

250: S bus

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a connection of a workstation to a switching system according to the present invention in a general ATM switch, and FIG. 2 is a detailed block diagram of an ATM cell generator (SPCA) shown in FIG.

Broadband Telecommunication Networks are high-speed Telecommunication Networks that accommodate not only voice and low-speed data communications supported by narrowband Telecommunication Networks, but also high-speed data transmission, still picture, telephony, and video conferencing services. The ATM switching system used in the broadband communication network is composed of three switching modules, that is, an access switching module and a UNI / NNI matching module, and provides an ATM local switching subsystem (ALS) that provides subscriber / international service with subscribers or other exchanges. ) And the ATM Central Switching Subsystem (ACS) that connects the ALSs to provide the services of the switching system. At this time, UNI / NNI that can be connected in ATM switching system are UNI of 155Mbps STM-1, DS3, medium and low speed UNI of DS1E, NNI of 155Mbps STM-1 and 622Mbps STM-4, respectively.

As shown in FIG. 1, the ATM switch is largely divided into ATM Local Switching / Subscriber subsystem (ALS / S) and ATM Local Switching / Trunk subsystem (ALS / T). 120, an ATM Central Switching Subsystem (ACS) 130; In addition, the ALS / S 110 may include as many Subscriber Interface Modules (SIMs 111 and 112) as the number of subscribers, and an Access Switching Network Module (ASNM) to accommodate the SIMs 111 and 112, Call Control Control Processor (CCCP) 114 that controls the subsystem, and the ALS / T 120 includes Trunk Interface Modules (TIMs) 121 and 122 and accommodates as many trunks as possible. An Access Switching Network Module (ASNM) 123, a call controlling the subsystem, and a Call Connection Control Processor (CCCP) 124.

In addition, the ACS 130 includes an interconnection switch network module (ISNM) and an operation preservation processor (OMP: 132), and the OMP 132 is a cell multiplexing and demultiplexing block (CMDH: Cell). Mux / Demux H / W Assembly), ATM Cell Generator (SPCA: Sbus interface Processor Communication board Assembly; 134), ATM Main Processor Block (AMPA) 135, and AMPA 135 Disk 136, cartridge tape (CT: 137), and the like.

As shown in FIG. 2, the ATM cell generator (SPCA) 134 may include a CPU 200, a ROM 202, a RAM 204, a buffer 210, 212, 214, 216, 217, 218, 219, and a sara transmission (SARA-S) control memory ( 220, SARA-S packet memory 222, SARA-R control memory 224, SARA-R packet memory 226, SARA-S: 230), Sara reception chip (SARA-R: 232), first-in first-out buffer (FIFO: 234), first-in, first-out buffer (FIFO: 236), taxi transmission chip (240,242), taxi reception chip (244,246) It is in charge of the IPC function, and there is a mutual conversion function between the message and the cell, and is matched with the upper system (AMPA: 135) and S-BUS. In addition, the CMDH 133 transmits and receives a cell at a rate of 100 Mbps using a TAXI method.

Here, sara transmission (SARA-S) refers to a transmitter that performs the functions of the division and recombination layer and the ATM layer in the ATM communication method, and sara reception (SARA-R) refers to the division and recombination layer and the ATM layer of the ATM communication method. Represents a receiver that performs a function.

In other words, the ATM communication method is a layered structure such as a physical layer, an ATM layer, and an ATM adaptation layer (AAL). The ATM adaptation layer (AAL) is a segmentation and reassembly (SAR) sublayer and convergence (CS). Subdivided into sublayers. In this process, the SAR layer divides the message into 48-byte payloads, and the ATM layer adds a 5-byte header to the 48-byte payload to form a 53-byte ATM cell. In the reception process, the CRCs attached to the header are examined at the ATM layer, and the payload cells are recombined at the SAR layer to form a message of arbitrary length.

Referring to FIG. 2, the ROM 202 is accessible only to the CPU 200, has a capacity of about 256K bytes, stores a boot program, and the like, and the RAM 204 is only accessible to the CPU 200 and has 128x32 bits. It consists of 0.5Mbyte capacity using module's SRAM.

The dual port memory 228 is accessible from the CPU and the S bus, and connects the ATM cell generator according to the present invention with an upper system through the S bus.

The SARA-S control memory 220 is composed of two 32K x 8-bit SRAMs having a 15 nS access time and a word port memory having a capacity of 64K bytes to support synchronous access of the SARA-S 230.

The SARA-S packet memory 222 is capable of reading and writing through mediation with the SARA-S 230 in the CPU 200 and storing packet data.

The SARA-R control memory 224 is composed of two 32K x 8-bit SRAMs of 15nS access time and a word port memory of 64K bytes in order to support synchronous access of the SARA-R 232.

The SARA-R packet memory 226 is capable of reading and writing through mediation with the SARA-R 232 in the CPU 200 and storing packet data.

The SARA-S chip 230 divides the message received through the S bus to form an ATM cell having a payload of 48 bytes, and then transmits it to the taxi bus side through the transmission FIFOs 234 and 236, and the SARA-R chip 232. ) Reassembles the ATM cells received through the TAXI receiving chips 244 and 246 and delivers them to the upper system through the SBUS. This SAR function can be implemented with the TNETA 1560 chip.

The TAXI (Transparent Asynchronous Xmiter) bus is matched by a TAXI transmit chip as shown in FIG. 3 and a TAXI receive chip as shown in FIG.

Referring to FIG. 3, a TAXI transmission chip (eg, AMD's Am7968) includes a control signal generator 51, a clock generator 52, an input latch 53, an encoder latch 54, a data encoder 55, And a shifter 56, a medium matching section 57, a series matching section 58, and the like.

In FIG. 3, the input latch 53 receives parallel data from a SAR layer chip and a command from a controller and latches the latch according to the control signal of the control signal generator 51, and the control signal generator 51. The data flow control is performed in a handshake manner with the SAR layer by a strobe signal and an acknowledgment signal. The clock generator 52 generates a predetermined clock in accordance with the data mode selection (DMS) and provides the clock to each device. The encoder latch 54 is configured to receive data (Data) received from the input latch 53 or the like. The command is latched according to the clock CLK, and the data encoder 55 encodes data to be transmitted in a 4B / 5B or 5B / 6B scheme.

The shifter 56 converts the parallel data into serial data and outputs the data according to the transmission clock. The medium matching unit 57 outputs differential transmission signals (Serial Out + and Serial Out-) to match the characteristics of the transmission medium. do.

Meanwhile, as shown in FIG. 4, the TAXI receiving chip (eg, AMD's Am7969) includes a medium matching unit 61, a shifter 62, a decoder latch 63, a data decoder 64, and an output latch 65. And an oscillator 66, a PLL clock regeneration unit 67, a byte synchronization logic 68, and the like.

The ATM cell data of the physical layer received through the transmission medium (optical cable, etc.) is received through the medium matching unit 61 in a serial manner, and is converted into parallel data by the shifter 62. The parallel data of the shifter 62 is latched in accordance with the clock reproduced in the decoder latch 63 and then decoded in the data decoder 64. That is, the data decoder 64 receives the symbol encoded by the 4B / 5B or 5B / 6B scheme in the data encoder 55 and decodes the original data.

The output latch 65 latches the decoded data from the data decoder 64 in accordance with the reproduced clock and then outputs the data to the SAR layer chip or controller in synchronization with the byte clock.

In FIG. 4, the oscillator 66 generates a predetermined clock, and the PLL clock regenerator 67 compares the clock of the oscillator with a clock reproduced from the received bit symbol to generate a reception clock and supplies the clock to each unit. Byte synchronous logic 68 establishes a synchronous unit of bytes in a series of bit units of data so that ATM cell data of units of bytes can be transferred to higher layers.

When using AMD's TAXI chips (transmit AM7968, receive AM7969), it is possible to provide high speed one-to-one serial communication of up to 100Mbps through coaxial or optical fiber.

As described above, the ATM cell generator according to the present invention can improve the communication speed by connecting the message of the upper system connected through the S bus to the switch network connected through the TAXI bus and the ATM method. It has an effect.

Claims (1)

In the device for accessing the switch network via a taxi (TAXI) bus to the upper system connected via the S bus, Dual port memory 228 for registration with the bus; A transmission control memory 220 that stores control data for controlling transmission; A transmission packet memory 222 for storing message data for transmission; A SAR transmission chip (230) operated by control data set in the transmission control memory to generate an ATM cell by dividing a message received in the transmission packet memory from an upper system; Transmission FIFOs 234 and 236 for storing ATM cell data formed by the SAR transmission chip; Taxi transmission chips 240 and 242 for transmitting data of the transmission FIFO at high speed; Taxi reception chips 244 and 246 for reproducing a signal received through a taxi bus and outputting an ATM cell; A reception FIFO 238 for storing reception data of the taxi reception chip; A reception control memory 224 that stores control data for controlling reception; A received packet memory 224 for storing the reassembled message data; And A SAR receiving chip 232 operated by control data set in the reception control memory to analyze an ATM cell inputted from the reception FIFO to check an error, reassemble a payload, replay a message, and store the message in the reception packet memory 232. ATM cell generator in an ATM switch system.