KR100337641B1 - ATM Mux/Demux module between MSC and BSC in IMT-2000 network - Google Patents

Abstract

The present invention relates to an ATM multiplexing / demultiplexing means and a method between an exchange station and a control station of an IMT-2000 network, which is a next-generation mobile communication network. The present invention relates to an ATM multiplexing / demultiplexing module between an exchange and a control station.

The ATM multiplexing / demultiplexing module of the present invention multiplexes a physical layer interface function of an ATM cell transmitted and received from a switching center to a control station, an ATM cell received through a cell bus, and a signaling cell of AAL5 sent from a processor, thereby switching the switching center through the physical layer. Conversely, the circuit has multiplexing function to transmit to the processor or cell bus by latching the VPI / VCI of ATM cell received from the exchange and then comparing it to the VPI / VCI column of CAM (Content Addressable Memory). In addition, the present invention provides an ATM multiplexing / demultiplexing means and a method for efficiently constructing a matching module for accommodating each base station controlled through an ATM cell bus, thereby improving the overall system configuration.

Description

ATM Mux / Demux module between MSC and BSC in IMT-2000 network}

The present invention relates to an ATM multiplexing / demultiplexing means and a method between an exchange station and a control station of an IMT-2000 network, which is a next-generation mobile communication network. In particular, the present invention is connected by an ATM switch and a 155Mbps ATM matching standard and accommodates multiple ATM matching modules. The present invention relates to an ATM multiplexing / demultiplexing module between an exchange and a control station.

With the development of high speed networks, IMT-2000 networks are being developed to provide multimedia services required in mobile communication networks. The IMT-2000 network is mainly composed of a mobile switching center (MSC), a base station controller (BSC) and a base station transceiver system (BTS).

In the next generation mobile communication, IMT-2000, it is essential to increase the efficiency of the entire network configuration for accommodating multiple base stations.

Accordingly, the present invention provides an ATM multiplexing / demultiplexing means and method for efficiently constructing an entire system by efficiently configuring an ATM matching module in an IMT-2000 network, which is a next-generation mobile communication network. Its purpose is to.

ATM multiplexing / demultiplexing means between the switching station and the control station in the next generation mobile communication (IMT-2000) network for achieving the above object is an access for performing the function of transferring the traffic information and control information of voice and data between the base station and the control station A plurality of selector and transcoder subsystems that perform a function of converting a signal received through the access network subsystem into PCM form, or converting and transmitting data traffic into HDLC form; A control and signal subsystem connected to an access network subsystem and performing overall radio resource and link management related to radio resource allocation and radio bearer setup, maintenance, modification and termination, and traffic resource management, and the selector and transcoder sub It accepts an ATM switch connected to the system and a 155 Mbps optical interface. Is characterized in that it comprises an exchange.

The ATM multiplexing / demultiplexing method between the switching center and the control station of the next generation mobile communication (IMT-2000) network achieves the above object. The multiplexing / demultiplexing FPGA transmits an ATM cell received through a cell bus to the FIFO in a round robin manner. After saving, the AAL5 signaling cell sent by the processor multiplexes the path with the stored FIFO and transmits it to the switching center through the physical layer, or latches the VPI / VCI of the ATM cell received from the switching center and compares it with the VPI / VCI column of the CAM. And demultiplexing switching toward the processor and the cell bus.

1 is a block diagram showing the structure of the next generation mobile communication network (IMT-2000) according to the present invention.

2 is a block diagram of an ATM multiplexing / demultiplexing module according to the present invention;

3 is a schematic structural diagram of FPGA, CAM and DPRAM and a processor of the ATM multiplexing / demultiplexing module according to the present invention;

4 is an internal circuit and timing diagram of a multiplexed / demultiplexed FPGA in accordance with the present invention.

5 is a cell bus matching timing diagram of an ATM multiplexing / demultiplexing module in accordance with the present invention.

<Description of Signs of Main Parts of Drawings>

100: exchange station 102: control station

103: base station 104: ATM multiplexing / demultiplexing module

105: ATM matching device 106: Vocoder and selector

107: STS 108: ANS

110: CCS 201 and 301: Processor

202 and 303: CAM 203 and 304: DPRAM

204 and 302: Multiplexing / Demultiplexing FPGA 205: Physical Layer Matching

206: optical matching module

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The next generation mobile communication network (IMT-2000) according to the present invention uses an ATM switch as a switching station, and the control station is connected to the switching station via a 155Mbps optical interface and performs a function of controlling a base station. The ATM matching module is connected to the ATM multiplexing / demultiplexing module.

1 is a block diagram showing the structure of a next generation mobile communication network (IMT-2000) according to the present invention.

Referring to FIG. 1, the IMT-2000 network is largely composed of an exchange station 100, a control station 102, and a base station 103. Switching station 100 is used an ATM switch 101, the control station 102 is connected to the switching station 100 by a 155Mbps optical interface. The control station 102 includes an access network subsystem 108 (hereinafter referred to as an ANS), a selector and a transcoder subsystem (hereinafter referred to as an STS), and a control and signal subsystem. (Call and Signal Subsystem; 110, hereinafter referred to as CSS).

The ANS 108 connects each sub-system within the base station 103 and the control station 102 to provide a communication path for traffic and control data between each sub-system, and to route ATM cells generated in each sub-system. Do this. That is, the ANS 108 performs a function of transferring traffic information and control information of voice and data between the base station 103 and the control station 102.

The plurality of STSs 107 include a selector interface block 111 (hereinafter referred to as SIB), a selector and transcoder block (109, hereinafter referred to as STB), an ATM matching module 105 and a plurality of ATM multiplexing / demultiplexing (Mux / Demux) module 104 is configured.

The STS 107 receives the voice traffic data input from the mobile terminal via the base station 103 through the ANS 108 and converts the voice traffic data into the PCM form, and converts the data traffic into the HDLC form and the ATM matching device 105. And transmits to the ATM multiplexing / demultiplexing module 104. The STS 107 is an SIB (Selector Interface Block) 111 that performs the functions of the physical and ATM layers of the ATM, an AAL layer, a plurality of Selector Transcode Blocks (109) that performs the selection transcoding function, and an ATM Cell. ATM matching device 105 and ATM multiplexing / demultiplexing module 104 for transmitting a.

The SIB 111 performs a function of transmitting and receiving traffic and signal data with the base station 103 and transmitting control signals inside the control station 102, and is input from the base station 103 in the form of AAL-2 as an end point of the ATM link. A voice traffic ATM cell and an AAL-5 type control signal and data ATM cell are received and transmitted to the STB 109, and the reverse process thereof is performed.

The plurality of STBs 109 performs a function related to layer triple mobility management of the CDMA wireless access standard and converts the traffic received from the base station 103 into a PCM form, and then converts the traffic to the ATM matching device 105 and the ATM multiplexing / Transmitting to the demultiplexing module 104 and voice coding PCM type voice data received from the ATM matching device 105 and the ATM multiplexing / demultiplexing module 104, soft handoff control and outer-loop power control. And so on.

Control Signaling Subsystem (CSS) 110 is a subsystem that performs base station processing in the mobile subscriber's call processing function. The overall radio resource and link management and STB related to radio resource allocation and radio bearer setup, maintenance, modification, and termination Traffic resource management such as allocation of selector and transcoder in base station and base station link establishment, and the like.

ATM multiplexing / demultiplexing module 104 is designed to control four ATM matching modules 105. The ATM matching module 105 receives the AAL1 traffic data and the AAL5 signaling traffic data in the form of an ATM cell from the switching center 100 through the ATM multiplexing / demultiplexing module 104, and then converts the AAL1 traffic data into a TDM signal to form a vocoder and It transmits to a selector (Vocoder / Selector) 106 and, conversely, converts TDM data coming from the base station into an ATM cell and transmits the same to the switching center 100 through the ATM multiplexing / demultiplexing module 104.

The ATM multiplexing / demultiplexing module 104 supports the ATM-based exchange and transmission scheme in the control station 102 of the IMT2000 network, and multiplexes and demultiplexes the ATM cells between the switching center 100 and the control station 102. Perform the function of multiplexing.

The base station 103 performs a termination function for matching with the terminal according to a wireless standard, and is connected to the control station 102.

2 is a block diagram of the ATM multiplexing / demultiplexing module 104 shown in FIG.

Referring to FIG. 2, the ATM multiplexing / demultiplexing module 104 includes a processor 201, a content addressable memory (CAM) 202, a DPRAM 203, a mux / demux FPGA for the AAL5 SAR function. 204, a physical layer matching chip 205, an optical matching module 206, and FIFOs 207 to 209 for storing ATM cells.

The processor 201 used Motorola's MPC860SAR processor 201 to simultaneously process the AAL5 SAR function for signaling and the overall board control function with the ATM switch 101 of FIG. 1. Since the MPC860SAR processor 201 can assign a specific port to the UTOPIA bus to disassemble and transmit AAL type 5 ATM cells, the MPC860SAR processor 201 does not need to have a separate processor for the AAL5 SAR function. have.

The processor 201 assembles the cells into 53-byte cells after the ATM multiplexing / demultiplexing module 104 has packet data to be sent to the ATM exchanger 101 for signal processing. The FIFO 207, the FPGA 204, and the physical layers 205 to 206 are transmitted to the ATM switch 101. In contrast, when the ATM switch 101 receives the signaling cell, the signaling cells determined by the CAM 202 and the FPGA 204 are transmitted to the processor 201 through the UTOPIA bus, and the cell at the processor 201. Reassembly

In addition, it is configured to provide asynchronous communication through EIA-232C method through one UART channel for matching to perform basic management function.

When transmitting the cell received by the switching center 100 of FIG. 1 to the ATM matching module 105, the CAM 202 and the DPRAM 203 are used for the addition of 3 bytes of ATM cell routing tags and VCI / VPI conversion. do.

In the ATM multiplexing / demultiplexing module 104, the FPGA 204 first stores the ATM cells received via the cell bus in the FIFO 207 in a round robin manner, and the signaling cells of AAL5 sent by the processor 201 Multiplexed paths with the stored FIFO 207 are transmitted to the switching center 100 through the physical layer (205 ~ 206). Conversely, after latching the VPI / VCI of the ATM cell received from the switching center 100, it performs a demultiplexing function to switch to the processor 201 or to the cell bus in comparison with the VPI / VCI sequence of the CAM 202. .

When demultiplexing, the cell going to the UTOPIA bus of the processor 201 is sent as it is, and the cell going to the cell bus adds a routing tag and converts and transmits the VPI / VCI. The physical layer matching chip is used to match the physical layer 205 of the ATM, and the CPU interface matches the processor 201 with 8-bit data.

The 155 Mbps serial ATM transmit / receive channel allows matching with the UNI port of the ATM switch 101 via the optical matching module 206. The 8-bit ATM transmit and receive data is transmitted through the UTOPIA bus through the FIFO 207 of the physical layer. Match with.

FIG. 3 is a matching structural diagram of the FPGA 302, the CAM 303, the DPRAM 304, and the processor 301 of the ATM multiplexing / demultiplexing module 104 shown in FIG. 2.

Referring to FIG. 3, the ATM multiplexing / demultiplexing module 104 adds three bytes of ATM cell routing tag and VCI / VPI conversion when transmitting the cell received at the switching center 100 to the ATM matching module 105. CAM 303 and DPRAM 304 are used for this purpose.

The CAM 303 compares the 32 bit data stream and informs the FPGA 304 of the content address where the data stream is stored.

Referring to the operation of the CAM 303 and the DPRAM, first, a 4-byte cell head portion is latched in a 53-byte standard ATM cell received from the switching center 100 and compared through the data port of the CAM 303, and the comparison result is obtained. Is matched, the DPRAM address of the connection is passed to the FPGA (302). Passing the DPRAM 304 address, the FPGA 302 accesses the DPRAM, adds the desired 3-byte cell bus routing tag, and converts the 4-byte VPI / VCI and 48-byte payload to 56-byte 1 cell to be converted. Make it and send it to the cell bus.

The major signal of CAM 303, / mv, indicates that there is a valid match (/ mv = 0) in the CAM 303 array or VP table after the comparison cycle is over, and the matching active address aa [11..0] Output The CAM 303 has a software control mode and a hardware control mode according to the control method. The selection of the mode is determined by the control register FR26-27 (hardware control mode = 00, software control mode = 11) of the CAM 303.

In the present invention, the hardware control mode is used because real time is required.

In the content memory inside the CAM 303, a VPI / VCI assigned with a connection from an upper block is set, and the DPRAM 304 also stores a head to be newly changed at the address of the connection.

On the other hand, when transmitting to the switching center 100 in the ATM multiplexing / demultiplexing module 104, the FPGA 302 first stores the ATM cells received through the cell bus in the FIFO in a round robin manner, and the processor 301 AAL5's signaling cell sends multiplexed paths to the stored FIFO and transmits them to the switching center 100 through the physical layer. Conversely, after latching the VPI / VCI of the ATM cell received from the exchange 100 and comparing it to the VPI / VCI column of the CAM 303, the demultiplexing function switches to the processor 301 or to the cell bus. Do it.

When demultiplexing, the cell going to the UTOPIA bus of the processor 301 is sent as it is, and the cell going to the cell bus adds a routing tag and converts and transmits the VPI / VCI.

4 is a circuit and timing diagram of the multiplexed / demultiplexed FPGA 204 shown in FIG.

Referring to FIG. 4, the ATM cell received from the switching center 100 is shifted 14 times in the FPGA, and the VPI / VCI is compared by the CAM 402 during the transition, and when matched, a / cam_mv signal is given to the DPRAM 403. Get the corresponding 3 bytes of routing tag and 4 bytes of cell header (VPI / VCI) to be controlled, and control 405 to export the routing tag and changed header in DPRAM 403 for a specific clock period (13 ~ 19) The payload of the original cell is then exported from the next clock.

Efficient network configuration can be achieved by configuring four ATM adapters to receive ATM cells broadcast from the cell buses of the ATM multiplexing / demultiplexing module 104 through the changed headers.

On the other hand, when the switching center 100 wants to send a signaling signal to the processor 301 of the ATM multiplexing / demultiplexing module 104, it sets a specific bit of the VPI / VCI to the processor without converting a routing tag or VPI / VCI. To send.

5 is a cell bus matching timing diagram of the ATM multiplexing / demultiplexing module 104. Referring to FIG. 5, the Statecnt value is a timing count value running inside the FPGA to receive and transmit a cell according to the count value. Transmit ATM cells (p_rxin [7: 0]) received at the physical layer-matched FIFO to the FPGA for 14 times, and the statecnt is routed to 13-15 using the CAM 402 and DPRAM 403 during the transition. After 3 bytes, the statecnt has changed VPI / VCI from 16 to 19, and once transitioned from the FPGA, statecnt sends the routing tag and changed VPI / VCI to the cell bus for 14 to 20, and from statecnt 21 the payload of the original cell. Send.

The cell bus block is a bus that sends and receives ATM cells to and from the ATM matching module 105. When the ATM multiplexing module 104 sends data to the ATM matching module 105, the cell bus block always performs broadcasting and ATM matching. Module 105 compares and receives the routing heads.

On the other hand, when the cell is transmitted from the ATM matching module 105 to the ATM multiplexing / demultiplexing module 104, a cell bus is designed so that a plurality of ATM matching modules 105 can transmit the receiving cells to the physical layer in a round robin manner. It was.

As described above, in a control station of an IMT-2000 network, which is a next-generation mobile communication network, an ATM multiplexing / demultiplexing module between an switching center and a control station connected to an ATM switch and a 155Mbps ATM matching standard and accommodating several ATM matching boards. The ATM matching module is connected to an ATM multiplexing / demultiplexing module through an ATM cell bus, and efficiently configures an ATM matching module for accommodating a plurality of base stations, thereby increasing system efficiency.

Claims (5)

An access network subsystem that performs a function of transferring traffic information and control information of voice and data between the base station and the control station; A plurality of selector and transcoder subsystems for converting a signal received through the access network subsystem into a PCM form or converting and transmitting data traffic into an HDLC form; A control and signal subsystem connected to the access network subsystem to perform overall radio resource and link management related to radio resource allocation and radio bearer setup, maintenance, modification and termination, and traffic resource management; Means for multiplexing / demultiplexing between the switching station and the control station of a next-generation mobile communication network, wherein the switching station accommodates an ATM switch connected to the selector and transcoder subsystem through a 155 Mbps optical interface. The system of claim 1, wherein the selector and transcoder subsystem A selector interface block for receiving and transmitting a voice traffic ATM cell inputted from the base station in the form of AAL-1 and an AAL-5 type control signal and data ATM cell as an endpoint of an ATM link, or performing the reverse process thereof; A plurality of selector and transcode blocks connected to the selector interface block for converting and transmitting traffic received from the base station into a PCM format or performing voice encoding on PCM-type speech data; And an ATM multiplexing / demultiplexing module connected to the selector and the transcode block to support an ATM-based exchange and transmission scheme, and performing an ATM multiplexing and a demultiplexing function between the switching center and the control station. AMT multiplexing / demultiplexing means between an exchange station and a control station of a next generation mobile communication network. The method of claim 2, wherein the selector and the transcode block is Receives traffic data and signaling traffic data in the form of ATM cell from the ATM multiplexing / demultiplexing module and converts it into a TDM signal, or converts the TDM data received from the base station into an ATM cell and transmits it to the ATM multiplexing / demultiplexing module. ATM matching module, And a vocoder and a selector for receiving the TDM signal received by the ATM matching module. The method of claim 2, wherein the ATM multiplexing / demultiplexing module A processor for simultaneously processing the AAL5 disassembly and assembly function for the ATM exchanger and the signaling and the entire board control function; CAM and DPRAM for adding an ATM cell routing tag and performing VCI / VPI conversion when transmitting a cell received at the switching center to the ATM matching module; A plurality of FIFOs storing ATM cells, ATM cells received through a cell bus are stored in the FIFO in a round robin manner, and a signaling cell of AAL5 sent by the processor is multiplexed with a stored FIFO or latches the VPI / VCI of an ATM cell received from the switching center. A multiplexing / demultiplexing FPGA that performs a demultiplexing function to switch to the processor or cell bus compared to the VPI / VCI column of the CAM; 8-bit data matching the processor and the 155Mbps serial ATM transmission and reception channel comprises a physical layer matching and optical matching module to match the UNI port of the ATM switch between the switching station and the control station of the next-generation mobile communication network HT multiplexing / demultiplexing means. The multiplexing / demultiplexing FPGA stores the ATM cells received through the cell bus in the FIFO in a round robin fashion, and then the AAL5 signaling cells sent by the processor multiplex the paths with the stored FIFOs and transmit them through the physical layer to the exchange. ATI multiplexing between the switching center and the control station of the next generation mobile communication network, characterized in that the latching of the VPI / VCI of the ATM cell received from the switching center is performed and the demultiplexing is switched to the processor and the cell buses in comparison with the VPI / VCI column of the CAM. Demultiplex method.