KR19980054474A - Field effect transistor and manufacturing method of semiconductor device - Google Patents
Field effect transistor and manufacturing method of semiconductor device Download PDFInfo
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- KR19980054474A KR19980054474A KR1019960073637A KR19960073637A KR19980054474A KR 19980054474 A KR19980054474 A KR 19980054474A KR 1019960073637 A KR1019960073637 A KR 1019960073637A KR 19960073637 A KR19960073637 A KR 19960073637A KR 19980054474 A KR19980054474 A KR 19980054474A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000002353 field-effect transistor method Methods 0.000 title 1
- 238000005468 ion implantation Methods 0.000 claims abstract description 30
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 230000005669 field effect Effects 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- -1 phosphor ions Chemical class 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 장치 제조방법.Semiconductor device manufacturing method.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
바디 이펙트를 보상함과 동시에 높은 구동 전류를 갖는 소오스/드레인 영역을 형성하기 위한 전계효과트랜지스터 및 그 제조방법을 제공하고자 함.To provide a field effect transistor and a method of manufacturing the same to compensate for the body effect and to form a source / drain region having a high driving current.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
반도체 기판 상부에 게이트 전극 패턴을 형성한 후, 제 1 도전형의 소오스/드레인영역을 형성하고, 상기 소오스/드레인 영역 하부에 제 2 도전형의 제 1 포켓 이온주입 영역을 형성한 다음, 상기 게이트 전극 패턴의 일부분과 드레인 영역을 덮는 마스크를 사용하여 제 2 도전형의 불순물을 포켓 이온주입하여 상기 제 1 포켓 이온주입 영역 하부에 제 2 포켓 이온 주입 영역을 형성하는 것을 포함해서 이루어진 전계효과트랜지스터 제조방법을 제공하고자 함.After forming a gate electrode pattern on the semiconductor substrate, a source / drain region of a first conductivity type is formed, and a first pocket ion implantation region of a second conductivity type is formed below the source / drain region, and then the gate is formed. Fabrication of a field effect transistor comprising forming a second pocket ion implantation region under the first pocket ion implantation region by pocket ion implantation of impurities of a second conductivity type using a mask covering a portion of the electrode pattern and the drain region To provide a way.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 소자 제조 공정 중 전계효과트랜지스터 및 그 제조 공정에 이용됨.It is used in field effect transistor and manufacturing process of semiconductor device manufacturing process.
Description
본 발명은 반도체 장치의 전계효과트랜지스터 제조방법에 관한 것으로, 특히 싱글(Single) 소오스/드레인 구조를 갖는 반도체 장치의 전계효과트랜지스터 및 그 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a field effect transistor of a semiconductor device, and more particularly to a field effect transistor of a semiconductor device having a single source / drain structure and a method of manufacturing the same.
일반적으로, 반도체 소자가 점차 고집적화되어감에 따라 단채널(short channel) 효과를 억제함과 동시에 얕은 소오스/드레인 접합 및 게이트 전극의 면저항(sheet resistance) 감소가 요구되고 있다.In general, as semiconductor devices become increasingly integrated, short source effects are suppressed, and shallow source / drain junctions and sheet resistances of gate electrodes are required.
도 1 내지 도 3은 종래기술에 따른 반도체 장치의 전계효과트랜지스터의 단면도로, 소오스/드레인 영역 형성 방법에 따른 실용적인 3가지 구조의 전계효과트랜지스터를 도시한 것이다. 도면 부호, 11은 반도체 기판, 12는 게이트 산화막, 13은 게이트 전극, 14는 산화막 스페이서, 15는 저농도 이온주입 영역, 16은 고농도 이온주입 영역 및 17은 포켓 이온주입 영역을 각각 나타낸다. 먼저, 도 1은 LDD(Lightly Doped Drain) 구조의 전계효과트랜지스터로 핫 캐리어 효과(Hot Carrier Effect)에는 매우 효과적이다. 단채널 효과(Short Channel Effect)에는 매우 취약하며 특히, 소오스/드레인간의 직결저항이 너무 커서 전류 구동성(Current Drivability)이 매우 취약하다.1 to 3 are cross-sectional views of a field effect transistor of a semiconductor device according to the prior art, and show three practical field effect transistors according to a source / drain region forming method. Reference numeral 11 denotes a semiconductor substrate, 12 a gate oxide film, 13 a gate electrode, 14 an oxide spacer, 15 a low concentration ion implantation region, 16 a high concentration ion implantation region, and 17 a pocket ion implantation region, respectively. First, FIG. 1 is a field effect transistor having a lightly doped drain (LDD) structure, which is very effective for a hot carrier effect. It is very vulnerable to the short channel effect, and in particular, the direct resistance between the source and drain is so large that the current driveability is very weak.
이어서, 도2는 GO(Gate Overlap) LDD(Lightly Doped Drain) 구조의 전계효과트랜지스터를 도시한 것으로, 단채널 효과에 매우 취약한 특성을 나타내며, 도 3은 포켓 LDD(Lightly Doped Drain) 구조의 전계효과트랜지스터를 도시한 것으로, 기생적인 접합 캐패시턴스가 많은 문제점을 안고 있다.Subsequently, FIG. 2 illustrates a field effect transistor having a GO (Gate Overlap) lightly doped drain (LDD) structure, which exhibits very vulnerable characteristics to short channel effects, and FIG. 3 illustrates a field effect of a pocket LDD structure. As transistors are shown, parasitic junction capacitances present many problems.
따라서, 상기와 같이 매우 짧은 채널(Channel) 길이를 갖음으로써 단채널 효과에 매우 취약한 특성을 갖는 소자의 경우 드레인에 높은 바이어스(Bias)가 인가되었을 때 바디 이펙트(Body Effect)에 의해 드레인 에지(Drain Edge) 부근에서 핀치오프(Pinch-off)가 일어나게 되는 등의 문제점이 있었다.Therefore, in the case of a device having a very short channel length as described above and very vulnerable to short channel effects, when a high bias is applied to the drain, the drain edge is caused by the body effect. There is a problem such as a pinch-off occurs near the edge.
상기와 같은 문제점을 해결하기 위해서 안출된 본 발명은 바디 이펙트를 보상함과 동시에 높은 구동 전류를 갖는 소오스/드레인 영역을 형성하기 위한 반도체 장치의 전계효과트랜지스터 및 그 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a field effect transistor of a semiconductor device for forming a source / drain region having a high driving current while compensating for a body effect, and a method of manufacturing the same. .
도 1 내지 도 3은 종래기술에 따른 반도체 장치의 전계효과트랜지스터 단면도,1 to 3 are cross-sectional views of a field effect transistor of a semiconductor device according to the prior art,
도 4A 내지 도4C는 본 발명의 일실시예에 따른 반도체 장치의 전계효과트랜지스터 제조 공정 단면도.4A to 4C are cross-sectional views of a field effect transistor manufacturing process of a semiconductor device according to one embodiment of the present invention;
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
41 : 반도체 기판42 : 게이트 산화막41 semiconductor substrate 42 gate oxide film
43 : 게이트 전극44 : 고농도 불순물 이온주입 영역43: gate electrode 44: high concentration impurity ion implantation region
45, 46 : 포켓 이온주입 영역47 : 포토레지스트 패턴45, 46: pocket ion implantation region 47: photoresist pattern
상기 목적을 달성하기 위하여 본 발명은 반도체 기판; 소정부위의 반도체 기판에 형성된 게이트 전극; 상기 게이트 전극 양측 반도체 기판에 형성된 제 1 도전형의 고농도 불순물 소오스/드레인; 상기 제 1 도전형의 고농도 불순물 소오스/드레인 하부에 형성된 제 2 도전형 불순물의 제 1 포켓 소오스/드레인; 및 상기 제 1 포켓 소오스 하부에 형성된 제 2 도전형의 제 2 포켓 소오스를 포함하여 구성된 것을 특징으로 한다.The present invention in order to achieve the above object; A gate electrode formed on the semiconductor substrate at a predetermined portion; A high concentration impurity source / drain of a first conductivity type formed in the semiconductor substrate on both sides of the gate electrode; A first pocket source / drain of a second conductivity type impurity formed under the high concentration impurity source / drain of the first conductivity type; And a second pocket source of a second conductivity type formed under the first pocket source.
또한, 본 발명은 반도체 기판 상부에 게이트 절연막, 게이트 전극용 전도막을 차례로 형성한 후 게이트 전극용 마스크를 사용한 식각공정에 의해 게이트 전극을 형성하는 단계; 제 1 도전형의 불순물을 고농도 이온주입하여 소오스/드레인 영역을 형성하는 단계; 상기 소오스/드레인 영역 하부에 제 2 도전형의 불순물을 포켓 이온주입하여 제 1 포켓 이온주입 영역을 형성하는 단계; 및 상기 게이트 전극의 일부분과 드레인 영역을 덮는 마스크를 사용하여 제 2 도전형의 불순물을 포켓 이온주입하여 상기 제 1 포켓 이온주입 영역 하부에 제 2 포켓 이온주입 영역을 형성하는 단계를 포함하는 것을 특징으로 한다.In addition, the present invention comprises the steps of forming a gate insulating film, a gate electrode conductive film on the semiconductor substrate in turn and then forming a gate electrode by an etching process using a mask for the gate electrode; Forming a source / drain region by implanting impurities of the first conductivity type in a high concentration; Pocket ion implantation of a second conductivity type impurity under the source / drain region to form a first pocket ion implantation region; And pocket ion implanting impurities of a second conductivity type using a mask covering a portion of the gate electrode and a drain region to form a second pocket ion implantation region under the first pocket ion implantation region. It is done.
본 발명은 게이트 전극 하부의 채널 영역의 포켓 이온주입에 있어서 소오스/드레인간의 불순물 농도에 있어서 기울기를 주는 방법으로, 소오스 에지(Edge)로부터 드레인 에지(Edge)로의 카운터 및 포켓 이온주입의 불순물 농도를 줄임으로써 바디 이펙트를 보상하기 위한 것이다.The present invention is a method of giving a slope in the impurity concentration between the source and drain in the pocket ion implantation of the channel region under the gate electrode, the impurity concentration of the counter and pocket ion implantation from the source edge to the drain edge (Edge) To compensate for the body effect by reducing.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 4A 내지 도 4C는 본 발명의 일실시예에 따른 반도체 장치의 전계효과트랜지스터 제조 공정 단면도로, N형 전계효과트랜지스터 제조 공정을 도시한 것이다.4A to 4C are cross-sectional views of a field effect transistor manufacturing process of a semiconductor device according to an embodiment of the present invention, which illustrates an N-type field effect transistor manufacturing process.
먼저, 도 4A는 P-웰(도시되지 않음)이 기형성된 반도체 기판(41)상에 게이트 산화막(42) 및 게이트 전극용 폴리실리콘막을 차례로 형성하고, 게이트 전극 마스크를 사용한 식각공정에 의해 게이트 전극(43)을 형성한 다음, N형 불순물인 포스포러스(Phosphorous) 이온을 고농도 이온주입하여 고농도 불순물 이온주입 영역(44)을 형성한 것을 도시한 것이다.First, FIG. 4A shows a gate oxide film 42 and a polysilicon film for a gate electrode sequentially formed on a semiconductor substrate 41 on which a P-well (not shown) is formed, and then a gate electrode by an etching process using a gate electrode mask. (43) is formed, followed by implantation of high concentration impurity ion implantation region 44 by phosphorus (Phosphorous) ions which are N-type impurities.
이어서, 도 4B는 상기 고농도 불순물 이온주입 영역(44) 형성을 위한 이온주입 에너지보다 더 높은 이온주입 에너지로 BF2이온을 이온주입하여 상기 고농도 불순물 이온주입 영역(44) 하부에 제 1 포켓 이온주입 영역(45)을 형성한 후, 열처리(Anneal)하고, 게이트 전극(43)의 일부분과 드레인 영역을 덮는 포토레지스트 패턴(47)을 형성한 것을 도시한 것이다.4B shows a first pocket ion implantation under the high concentration impurity ion implantation region 44 by implanting BF 2 ions at a higher ion implantation energy than the ion implantation energy for formation of the high concentration impurity ion implantation region 44. After forming the region 45, annealing is performed to form a photoresist pattern 47 covering a portion of the gate electrode 43 and a drain region.
마지막으로, 도 4C는 상기 포토레지스트 패턴(47)을 이온주입 마스크로 소오스 영역에 P형 불순물인 보론(Boron)을 고농도 이온주입하여 제 2 포켓 이온주입 영역(46)을 형성한 다음, 상기 포토레지스트 패턴(47)을 제거하고 열처리(Anneal)한 것을 도시한 것이다.Finally, FIG. 4C shows that the second pocket ion implantation region 46 is formed by implanting boron, which is a P-type impurity, into the source region using the photoresist pattern 47 as an ion implantation mask. The resist pattern 47 is removed and heat-treated (Anneal).
상기와 같은 일련의 공정은 P형 전계효과트랜지스터에 적용할 수 있다.Such a series of processes can be applied to P-type field effect transistors.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의한 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the spirit of the present invention. It will be evident to those who have knowledge of.
상기와 같이 이루어지는 본 발명은 소오스/드레인 영역간 불순물의 기울기를 갖는 싱글 소오스/드레인 구조를 형성함으로써, 소오스 영역에서의 높은 불순물 집중으로인해 소오스 영역에서의 공핍 영역이 커지는 것을 방지하게 되어 드레인 영역에서의 전장이 펀치 쓰로우 전압의 감소없이 저하된다.The present invention as described above forms a single source / drain structure having an inclination of impurities between the source and drain regions, thereby preventing the depletion region in the source region from growing due to the high concentration of impurities in the source region. The overall length is lowered without reducing the punch through voltage.
이로 인해 소오스/드레인간의 직렬저항을 최소화할 수 있어 전류 구동성을 크게 향상시킬 수있으며, 낮은 소오스/드레인 접합 캐패시턴스를 구현할 수 있고, 단채널 효과 및 핫 캐리어 효과를 효과적으로 억제할 수 있다.As a result, the series resistance between the source and drain can be minimized, which greatly improves the current driveability, realizes low source / drain junction capacitance, and effectively suppresses short channel effects and hot carrier effects.
Claims (5)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960073637A KR100248807B1 (en) | 1996-12-27 | 1996-12-27 | Field effect transistor and method for manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960073637A KR100248807B1 (en) | 1996-12-27 | 1996-12-27 | Field effect transistor and method for manufacturing the same |
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| Publication Number | Publication Date |
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| KR19980054474A true KR19980054474A (en) | 1998-09-25 |
| KR100248807B1 KR100248807B1 (en) | 2000-03-15 |
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