KR19990004935A - Method for manufacturing field effect transistor of semiconductor device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Semiconductor device manufacturing method.

2. The technical problem to be solved by the invention

To provide a field effect transistor manufacturing method for compensating substrate effects and forming a diffusion layer region having a high driving current.

3. Summary of Solution to Invention

After the gate electrode pattern is formed on the first conductive semiconductor substrate, a diffusion layer of the second conductivity type is formed, and a pocket ion implanted region which is highly doped with the first conductivity type is formed under the first conductive semiconductor substrate to form a short channel effect or a hot carrier. To overcome problems such as effects.

4. Important uses of the invention

Used in the field effect transistor manufacturing process of semiconductor device manufacturing process.

Description

Method for manufacturing field effect transistor of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor (FET) in a semiconductor device. The present invention relates to a method of manufacturing a field effect transistor (FET) in which a gate is formed of a PN junction, and a MOS stacked in the order of an oxide film / semiconductor. The present invention relates to a MOS field effect transistor having a single structure, particularly a MOS field effect transistor having a single source / drain structure.

In the 1960's, the characteristics and structure of the MOS transistor developed by Bell Labs in the United States shows that a gate oxide and a metal layer are stacked and patterned on a silicon substrate to form a gate electrode. A transistor having a MOS structure was manufactured by forming a diffusion layer of a source and a drain using the gate electrode as a diffusion barrier.

Such MOS transistors have various problems due to their physical characteristics, not theories. Among them, the short channel effect and the hot carrier effect have a great influence on the deterioration of device characteristics. Carriers can get more heat than they can get by ambient temperature due to interactions in the field. These carriers are called hot carriers. Primarily, hot carriers are obtained by obtaining enough heat that the free carrier across the high edge region of the drain edge can exceed the potential barrier (3.1 eV) of silicon and oxide, which is trapped in the gate oxide to affect device characteristics. give. The hot carrier effect due to such hot carriers causes more serious problems for short channel devices. In general, as semiconductor devices become increasingly integrated, short channel effects of MOS field effect transistors are suppressed, and shallow source / drain junctions and sheet resistance of gate electrodes are required to be reduced.

1A to 1C are cross-sectional views of a MOS field effect transistor of a semiconductor device according to the prior art, which is further improved, showing three practical MOS field effect transistors according to a method of forming a source / drain region.

In general, reference numeral 11 denotes a silicon substrate, 12 a gate oxide film, 13 a gate electrode, 14 an oxide spacer, 15 a low concentration ion implantation region, 16 a high concentration ion implantation region, and 17 a pocket ion implantation region, respectively.

First, FIG. 1A illustrates a field effect transistor having a general lightly doped drain (LDD) structure, which is very effective for a hot carrier effect, but very weak for a short channel effect. In particular, the series resistance between the source and the drain is so large that the current driveability is very weak.

Subsequently, FIG. 1B illustrates a field effect transistor having a GO (Gate Overlap) Lightly Doped Drain (LDD) structure, and exhibits very weak characteristics for short channel effects.

Next, FIG. 1C illustrates a field effect transistor having a pocket lightly doped drain (LDD) structure, which has many problems with parasitic junction capacitance.

Therefore, the conventional transistor as described above has a very short channel length, and thus, in the case of a device having a characteristic that is very vulnerable to a short channel effect, a high bias is applied to the substrate effect when a high bias is applied to the drain. As a result, a pinch-off occurs near the drain edge, and thus, it is necessary to develop a new MOS field effect transistor that can solve the problem.

SUMMARY OF THE INVENTION The present invention devised to solve the above-mentioned problems provides a method of manufacturing a field effect transistor of a semiconductor device for forming a diffusion layer having a high driving current while compensating for substrate effects in a semiconductor device manufacturing process. The purpose is.

1A to 1C are cross-sectional views of a field effect transistor of a semiconductor device according to the prior art;

2A to 2D are cross-sectional views of a field effect transistor fabrication process of a semiconductor device according to one embodiment of the present invention;

* Explanation of symbols for main parts of the drawings

21: silicon substrate

22: gate oxide film

23: gate electrode

24, 24a: first and second photoresist pattern

25 source / drain diffusion layer

26: first pocket ion implantation region

27: second pocket ion implantation region

In order to achieve the above object, a method of manufacturing a semiconductor device includes: forming a gate insulating film and a conductive film on an upper surface of a first conductive semiconductor substrate, and then forming the gate electrode by an etching process using a mask for a gate electrode; Implanting impurities with the gate electrode as a diffusion barrier to form a diffusion layer doped with a second conductivity type in both directions of the gate electrode; And implanting impurities of a first conductivity type into a lower portion of the diffusion layer doped with the second conductivity type, and varying impurities injected into the diffusion layer in the first direction and the diffusion layer in the second direction in both directions of the gate electrode. And forming second pocket ion implantation regions, respectively.

The present invention provides a gradient in the impurity concentration between the source and the drain in the pocket ion implantation of the channel region under the gate electrode, and the impurities of the counter and the pocket ion implantation from the source edge to the drain edge, the concentration of impurities By compensating for the substrate effect.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A to 2D are cross-sectional views of a field effect transistor manufacturing process of a semiconductor device according to an embodiment of the present invention, which illustrates a field effect transistor manufacturing process having N channels.

First, as shown in FIG. 2A, a polysilicon film 23 is sequentially formed of a gate oxide film 22 and a conductive film on the silicon substrate 21 doped with a P-type. The gate electrode 23 is formed by sequentially etching the polysilicon film 23 and the gate oxide film 22 in an etching process using a gate electrode forming mask. Impurity ions are implanted using the gate electrode 23 as an impurity diffusion barrier, and, for example, phosphorus (Phosphorous) is ion-implanted with high concentration on the entire surface of the N-type impurity to form the n + diffusion layer 25.

Next, as shown in Fig. 2B, the first photoresist film 24 formed to cover the diffusion layer on the first side of the diffusion layers 25 formed on both sides of the gate electrode 23 is used as an impurity diffusion barrier. Is implanted with ion implantation energy higher than the ion implantation energy for forming the n + diffusion layer 24, and thus the second pocket ion implantation in which the substrate is doped in the same semiconductor form as the diffusion layer 25 on the second side The area 27 is formed.

Next, as shown in Fig. 2C, the second photoresist 24a film formed so as to cover the diffusion layer on the second side of the diffusion layers 25 formed on both sides of the gate electrode 23 is used as an impurity diffusion barrier. _2, the ion implantation, but the n + diffusion layer 24, ion implantation energy higher implanted ion implantation with energy by the first doped semiconductor type, such as a substrate to the lower diffusion layer 25 of the first side of the first pocket than for the formation An ion implantation region 26 is formed.

Finally, as shown in Fig. 2D, the second photoresist 24a is removed and a thermal process is performed. Here, since boron used as the ion implantation material of the second pocket ion implantation region 27 has a larger diffusion ratio than BF ₂ used as the ion implantation material of the first pocket ion implantation region 26, the pocket ion implantation region deeper from the surface. Can form

The above series of processes can also be applied to P-type field effect transistors.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The present invention made as described above forms a pocket ion implantation region doped with impurities of the same type as the substrate under the source / drain regions doped with impurities, thereby preventing the depletion region toward the substrate from increasing and draining the drain. The electric field in the area reduces the decrease in the punch through voltage.

In addition, the series resistance between the source and the drain can be minimized, which greatly improves the current driveability, realizes low source / drain junction capacitance, and can effectively control the short channel effect and the hot carrier effect.

Claims (7)

Forming a gate insulating film and a conductive film on the first conductive semiconductor substrate in order, and then forming the gate electrode by an etching process using a mask for the gate electrode; Implanting impurities with the gate electrode as a diffusion barrier to form a diffusion layer doped with a second conductivity type in both directions of the gate electrode; And Ion implanting impurities of the first conductivity type under the doped diffusion layer doped with the second conductivity type, and different impurities are injected into the diffusion layer in the first direction and the second direction in both directions of the gate electrode Respectively forming second pocket ion implantation regions; Field effect transistor manufacturing method of a semiconductor device comprising a. The method of claim 1, And a second conductivity type impurity for forming the diffusion layer is formed of phosphorus. The method of claim 1, The diffusion layer formed in the first direction in both directions of the gate electrode is a drain region, the manufacturing method of the field effect transistor of the semiconductor device. The method of claim 1, The diffusion layer formed in the second direction in both directions of the gate electrode is a source region, the field effect transistor manufacturing method of a semiconductor device. The method of claim 3, The impurity implanted in the first pocket ion implantation region is a field effect transistor manufacturing method of a semiconductor device is formed in a gas atmosphere containing BF ₂ . The method of claim 4, wherein The impurity implanted in the second pocket ion implantation region includes boron, the field effect transistor manufacturing method of a semiconductor device. The method of claim 4, wherein And the second pocket ion implantation region is formed deeper from the surface than the first pocket ion implantation region.