KR19980053388A - Cell plate voltage fluctuation method and its circuit - Google Patents

Abstract

The present invention relates to a cell plate voltage fluctuation method and a circuit thereof for generating a high voltage difference across a cell capacitor, thereby reducing the relative test time and increasing the verification rate of the cell plate oxide layer. The first step of detecting and determining whether the level of the elevated voltage is out of an arbitrary threshold range, and if it is determined that the level of the elevated voltage is out of an arbitrary threshold range, the cell determined as a predetermined voltage And providing a cell plate voltage fluctuation method and a circuit according to the second step of converting the plate voltage into an external voltage or a ground voltage. The cell plate voltage is converted into an external voltage VCC or a ground voltage VSS. To switch up to the maximum burn-in external voltage level across the cell capacitor, Given a stress by detecting the process the defective state of the chips at an early stage is an operation to reduce the test time.

Description

Cell plate voltage fluctuation method and its circuit

1 is a diagram illustrating a related configuration of a memory cell according to a conventional method for holding a plate of the memory cell;

2 is an exemplary configuration diagram of a memory having a cell plate voltage variation circuit according to the present invention.

3 is a diagram illustrating a configuration of the switching circuit of FIG.

The present invention relates to a cell plate voltage fluctuation method and a circuit for generating a high voltage difference across a cell capacitor to reduce the relative test time and increase the verification rate of the cell plate oxide layer.

In general, the half voltage of the driving voltage (VCC) is used as the cell plate voltage in the self-burn-in experiment for early detection of a process defect of a highly integrated DRAM. Is shown.

1 is a diagram illustrating a related configuration of a memory cell according to a conventional method for holding a plate of a DRAM memory cell.

Looking at the configuration, the NMOS transistor (MN) having a gate terminal connected to the word line (WL), the bit line (BL) connected to the drain terminal, and one end is connected to the source terminal of the NMOS transistor (MN) A plurality of cells CA, CB, ... constituted by the capacitor C are provided.

In addition, the sensing amplifier 10 is connected to the bit line BL and amplifies and outputs a voltage applied to the bit line BL, and a capacitor constituting the cells CA, CB, ... The voltage generator 20 is configured to apply a cell plate voltage having a predetermined magnitude to the other end of the C).

Referring to the necessity of the plate voltage of the cell in the conventional DRAM memory structure configured as described above, in the DRAM structure having one transistor and one capacitor for storing data restored through the transistor inside the memory cell. The half-level voltage of the driving voltage is applied to the cell plate, which is a reference voltage node of the cell capacitor.

Accordingly, the stress applied to the cell capacitor oxide layer in the normal DRAM operation may be reduced, and the influence on noise may be reduced as compared with using the ground power source VSS or the driving voltage VCC as a reference voltage.

However, during burn-in test for early elimination of process defects rather than normal DRAM operation, the VCP level rises with a certain slope along with the external applied voltage rise, so that the stress caused by the electric field applied to the oxide layer of the cell capacitor is normal during operation. There is a problem that it is not possible to form the extreme condition necessary for burn-in test because there is no difference.

An object of the present invention for solving the above problems is the ground potential (VSS) or the driving voltage (VCC) according to the internally generated data pattern of the cell plate voltage set to the half voltage of the driving voltage during the self burn-in experiment The present invention provides a cell plate voltage fluctuation method and a circuit for reducing the relative test time and increasing the verification ratio of the cell plate oxide layer by generating a high voltage difference across the cell capacitor.

A feature according to the present invention for achieving the above object is a method for providing an extreme condition according to a burn-in test in a semiconductor memory device in which the cell plate voltage is determined to be a predetermined voltage, and detecting whether an external voltage is rising or not. A first step of determining whether the level of the elevated voltage is out of an arbitrary threshold range; and if it is determined that the level of the elevated voltage is out of an arbitrary threshold range, the cell plate voltage determined as a predetermined voltage is determined. Including a second process of switching to an external voltage or a ground voltage.

According to another aspect of the present invention for achieving the above object, a plurality of NMOS transistors having a gate terminal connected to a word line and a bit line connected to a drain terminal and a capacitor having one end connected to a source terminal of the NMOS transistor Memory cells, a sensing amplifier connected to the bit line to amplify and output a voltage applied to the bit line, and a cell plate voltage of a predetermined level applied to the other end of the capacitor to maintain safe operation of the memory. A circuit for providing an extreme condition in accordance with a burn-in check in a semiconductor memory device having a voltage generator, the circuit comprising: a self-burn-in detector for detecting a self-burn-in test and generating a flag signal; In the voltage generator according to the state of the flag signal generated in the detector It includes a switching unit for transferring the generated voltage to the plate of the cell or the ground potential or driving voltage to the plate of the cell in accordance with the internally generated data pattern.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a diagram illustrating a related configuration of a cell plate voltage circuit according to the present invention.

Looking at the configuration, the NMOS transistor having a gate terminal connected to the word line (WL), the bit line (BL) connected to the drain terminal, and a capacitor (C) having one end connected to the source terminal of the NMOS transistor A plurality of cells CA, CB, ... are provided.

In addition, a sensing amplifier 10 connected to the bit line BL and configured to amplify and output the voltage connected to the bit line BL, and a capacitor constituting the cells CA, CB, ... The voltage generator 20 is configured to apply a cell plate voltage having a predetermined magnitude to the other end of the C).

Such a structure is the same as the conventional structure, and in the present invention, the self-burn-in detector 40 and a self-burn-in detector 40 generating a flag signal by detecting the self-burn-in test are generated in the present invention. Switching to transfer the voltage generated from the voltage generator 20 to the plate of the cell according to the state of the flag signal or to transfer the ground potential VSS or the driving voltage VCC to the plate of the cell according to an internally generated data pattern. The part 30 is provided.

The configuration of the switching unit 30 as described above is composed of the first inverter I1 and the first inverter I1 that receives the inverted signal and outputs the inverted signal as shown in FIG. A second inverter I2 that receives an output signal and inverts and outputs the output signal; a third inverter I3 that receives the output signal of the second inverter I2 and inverts and outputs the data; OR gate OR for receiving the output signal of the third inverter I3 and performing an OR operation and outputting the calculated value, OR operation for receiving the data pattern and the output signal of the second inverter I2 Value and the output signal of the first inverter (I1) input to the gate terminal and the output signal from the voltage generation unit 20 to the drain terminal to perform the on / off operation according to the state The first NMOS transistor NA, A PMOS transistor having a sub-power VCC input to a source terminal and operating on / off according to an output signal of the OR gate OR input to a gate terminal, and having a drain terminal connected to a source terminal of the first NMOS transistor; MP) and the voltage applied to the drain terminal of the PMOS transistor MP are input to the drain terminal and operate on / off according to the output signal of the AND gate AND input to the gate terminal, and the source terminal is connected to ground. 2nd NMOS transistor MN.

Looking at the preferred operation of the cell plate voltage fluctuation circuit according to the present invention configured as described above are as follows.

First, in the normal DRAM operation, the output of the voltage generator 20 that generates a voltage level corresponding to the half voltage of the external voltage VCC as the conventional method is used as the reference voltage of the cell plate.

At this time, since the flag signal output from the burn-in detector 40 is in the L state, the first NMOS transistor NA is turned on, and the PMOS transistor PN and the second NMOS transistor NB are turned off. Doing.

Subsequently, when the external voltage VCC rises above a predetermined threshold level for the burn-in test operation, the burn-in detector 40 converts the output flag signal to H, thereby outputting the first inverter I1. The signal is switched to L.

Thus, the first NMOS transistor NA is turned off. As a result, the output path of the voltage generator 20 transmitted to the cell plate is closed.

At this time, the case of the pattern according to the burn-in check is determined internally. Assuming that the data pattern generated in this state is L state, the output of the third inverter I3 is in the L state, and the data pattern is in the L state. ) Output signal OR also maintains the L state.

The output signal of the AND gate AND also maintains the L state because the output pattern of the second inverter I2 is in the H state, but the data pattern is in the L state.

Accordingly, the PMOS transistor PN is turned on and the second NMOS transistor NB is turned off. The voltage applied to the cell plate is applied to the external voltage VCC.

On the other hand, when the data pattern is in the H state, the PMOS transistor PN is turned on and the second NMOS transistor NB is turned on in the opposite case to the above-described operation. VSS) voltage is applied.

By providing a cell plate voltage fluctuation method and a circuit which operate as described above, the cell plate voltage is converted into an external voltage (VCC) or a ground voltage (VSS) to reach the maximum burn-in external voltage level across the cell capacitor. The stress caused by the electric field causes early detection of defective chips in the process, thereby reducing the test time.

Therefore, the problem of defects that can be formed in the oxide layer of the cell capacitor is stressed by the electric field formation caused by the voltage difference up to the maximum external burn-in voltage level, which causes the cell plate voltage level to fluctuate during burn-in tapes. The situation has been made possible for extreme conditions, and time effects can be expected.

This effect is considered to be even greater in highly integrated cell processes of 256M DRAM and above.

Claims (3)

A method for providing an extreme condition following burn-in inspection in a semiconductor memory device in which a cell plate voltage is determined to be a predetermined voltage, Detecting whether the external voltage is increased and determining whether the level of the increased voltage is outside an arbitrary threshold range; And a second step of converting the cell plate voltage determined as a predetermined voltage into an external voltage or a ground voltage when it is determined that the level of the voltage raised in the first step is out of a predetermined threshold range. Fluctuation method. A plurality of memory cells comprising an NMOS transistor having a gate terminal connected to a word line and a bit line connected to a drain terminal, and a capacitor having one end connected to a source terminal of the NMOS transistor, and a bit line connected to the bit line And a sensing amplifier for amplifying and outputting a voltage applied to the circuit, and a voltage generator for applying a predetermined level of cell plate voltage to the other end of the capacitor to maintain safe operation of the memory. In a circuit for providing an extreme situation according to A self burn-in detector for detecting the self burn-in test and generating a flag signal; The voltage generated by the voltage generator is transferred to the plate of the cell according to the state of the flag signal generated by the self burn-in detector, or the ground potential or the driving voltage is transferred to the plate of the cell according to the internally generated data pattern. Cell plate voltage fluctuation circuit comprising a switching unit. The method of claim 2, The switching unit includes a first inverter that receives the flag signal and inverts and outputs it; A second inverter which receives the output signal of the first inverter and inverts the output signal; A third inverter that receives the output signal of the second inverter and inverts the output signal; An OR gate for receiving an internal data pattern and an output signal of the third inverter and performing an OR operation to output the calculated value; An AND gate receiving the data pattern and the output signal of the second inverter and performing an AND operation to output the calculated value; A first NMOS transistor configured to receive a voltage output from the voltage generator and a drain terminal, and to turn on / off an output signal of the first inverter input to a gate terminal according to a state; A PMOS transistor receiving an external power source from a source terminal and operating on / off according to an output signal of the OR gate input to a gate terminal and having a drain terminal connected to a source terminal of the first NMOS transistor; And And a second NMOS transistor having a voltage applied to the drain terminal of the PMOS transistor being input to the drain terminal, operating on / off according to an output signal of the AND gate input to the gate terminal, and having a source terminal connected to ground. Cell plate voltage fluctuation circuit.