KR19980048597A - Antistatic Circuit of Semiconductor Device - Google Patents

Abstract

An object of the present invention is to provide an antistatic circuit of a semiconductor device capable of preventing the data stored in the cell region of the semiconductor device from being destroyed.

The configuration of the present invention is an antistatic circuit of a semiconductor device including an antistatic unit configured to receive a predetermined voltage from an input pad and operate when an input voltage value is a voltage value corresponding to static electricity to discharge static electricity. And a voltage drop means for dropping the voltage value when an abnormal voltage is applied from the input pad, between the and the antistatic circuit portion.

Description

Antistatic Circuit of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an antistatic circuit of a semiconductor device, and more particularly, to a semiconductor device which prevents data stored in a cell region from being destroyed by electrons generated when an abnormal voltage is applied to an input pad of an antistatic circuit. It relates to an antistatic circuit.

In general, electrostatic discharge (Electro Static Discharge) is one of the factors that determine the reliability of the semiconductor chip, and occurs when handling the semiconductor chip or when mounted in the system, damage the chip. Therefore, in order to protect the semiconductor device from static electricity in the peripheral region of the semiconductor device, an antistatic circuit is provided.

A conventional antistatic circuit embedded in a semiconductor chip is shown in FIG.

Referring to FIG. 1, an antistatic circuit unit 11 is connected to an input pad 10, and an input buffer unit 12 is connected to an output terminal of the antistatic circuit unit 11.

Here, the electrostatic circuit unit 11 includes two first and second N-MOS transistors Q1 and Q2 connected in series to the respective power lines Vcc and Vss and primarily remove static electricity. Here, the gate electrodes of the first and second N-MOS transistors Q1 and Q2 are connected to each other, Vcc is applied to the drain of the first N-MOS transistor Q1, and the source of the second N-MOS transistor Q2 is applied. Vss is applied. At this time, the source of the first N-MOS transistor Q1 and the drain of the second N-MOS transistor Q2 are a common junction region (hereinafter referred to as node 1), and a resistor R and an input pad 10 are connected to this node 1. do. A field transistor 12 that secondaryly removes static electricity is connected to the resistor R. The field transistor 12 has a gate and a source grounded, and a drain thereof is connected to the input buffer unit 13.

In the antistatic circuit unit 20 as described above, when static electricity of Vcc or more is applied through the input pad 20, the first N-MOS transistor Q1 is turned on to remove static electricity through the Vcc line, thereby inputting static electricity. Is prevented from flowing into the input buffer 30.

In addition, when static electricity of −Vss or less is applied to the antistatic circuit unit 20 through the input pad 20, the second NMOS transistor Q2 is turned on to remove the static electricity.

A process cross section of such an antistatic circuit is shown in FIG. 2.

Referring to FIG. 2, reference numeral 1 denotes a semiconductor substrate, 2 denotes a field oxide film, 3 denotes an N well region, and 4 denotes a junction region corresponding to node 1, that is, the first NMOS transistor Q1. In the case of the source region, 5 denotes a drain region of the first N-MOS transistor Q1, and 6 denotes a cell region where data is stored.

The field oxide film 2 is formed in a predetermined region of the semiconductor substrate 1 where the P wells (not shown) are directed by a well-known LOCOS method, and in the drain predetermined region of the first N-MOS transistor Q1. The impurities of the type are ion implanted to form the N well 3. At this time, the N well 3 is formed to effectively discharge the static electricity when static electricity of Vcc voltage or more is introduced therein. Thereafter, predetermined predetermined impurities are ion implanted into the cell area to form the data storage area 6. Thereafter, a high concentration of N-type impurities are ion implanted into the semiconductor substrate 1 to form the source 4 and drain 5 regions of the first N-MOS transistor Q1. Here, the source 4 region of the first N-MOS transistor Q1 is also a drain region of the second MOS transistor Q2, and an input pad is connected to this portion 4, and the first N-MOS transistor Q1 is provided. The Vcc voltage is applied to the drain region 5 of the.

However, in the conventional semiconductor device, since the system needs to simultaneously drive a memory cell that is accelerated, an undershoot voltage, which is an abnormal input voltage as shown in FIG. 3, may be applied to the input pad. Here, the undershoot voltage is determined by the junction forward voltage (V _F : about −0.7 V) and the substrate voltage (V _BB : about −1.5 V) applied to the P well region of the substrate. That is, the enhanced voltage value of the junction forward voltage value and the substrate voltage value is applied to the minimum voltage value of the voltage applied through the pad, and the undershoot voltage is about -2 to -3.5V. . (In FIG. 3, A represents the maximum value of the undershoot voltage, and B represents the undershoot voltage.)

As described above, when the value of | V _F + V _BB | is input through the input pad, the source region of the first MOS transistor Q1 or the drain region of the second MOS transistor Q2 to which the input pad is connected is in a forward state. A large amount of electrons are injected into the P well in the semiconductor substrate. At this time, some of the injected electrons are coupled to the holes of the P well in the semiconductor substrate, and the remaining part flows into the cell region, thereby destroying the data storage region in the cell region (see FIG. 2).

Accordingly, the present invention is to solve the above-mentioned conventional problems, and to provide an antistatic circuit of a semiconductor device capable of preventing destruction of stored data in a cell region when an abnormal voltage is applied through an input pad. For the purpose of

1 is a diagram showing an antistatic circuit of a general semiconductor element embedded in a semiconductor chip.

2 is a process sectional view of an antistatic circuit of a general semiconductor device.

3 is a voltage timing diagram applied through the input pad of FIG.

4 is a diagram showing an antistatic circuit of a semiconductor device according to the present invention.

* Description of the symbols for the main parts of the drawings *

21: Input pad 22: Voltage drop section

23: static electricity prevention circuit section 24: input buffer section

In order to achieve the above object of the present invention, the present invention, the semiconductor device including a static electricity prevention unit for receiving a predetermined voltage from the input pad, the operation when the input voltage value is a voltage value corresponding to the static electricity, to discharge the static electricity An antistatic circuit of, characterized in that a voltage drop means for lowering the voltage value when an abnormal voltage is applied from the input pad is provided between the input pad and the antistatic circuit portion.

According to the present invention, even when an abnormal voltage is applied, the introduction of electrons into the cell region is prevented by the voltage drop means.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a schematic diagram illustrating an antistatic circuit of a semiconductor device according to the present invention, in which reference numeral 21 denotes an input pad, 22 denotes a voltage drop means, 23 denotes an antistatic circuit portion, and 24 denotes an antistatic circuit. Indicates an input buffer section.

Referring to FIG. 4, the antistatic circuit of the semiconductor device of the present invention includes an input pad 21 to which an input voltage is applied, and a voltage drop unit 22 to drop a voltage input from the input pad 21 by a predetermined value. Is provided. The voltage drop part 22 is connected to an antistatic circuit part 23 for discharging static electricity. The input buffer 24 is connected to the antistatic circuit portion 23.

At this time, the voltage drop unit 22 is a resistor having a predetermined value.

The antistatic circuit unit 23 includes two first and second NMOS transistors Q1 and Q2 connected in series to respective power lines Vcc and Vcc and primarily to remove static electricity. Here, the gate electrodes of the first and second N-MOS transistors Q1 and Q2 are connected, the power supply voltage Vcc is applied to the drain of the first N-MOS transistor Q1, and the second N-MOS transistor Q2 The source voltage Vss is applied to the source. The input pad 10 and the resistor R2 are connected to the source of the first N-MOS transistor Q1 and the drain region of the second N-MOS transistor Q2, and the resistor R2 secondaryly removes static electricity. The field transistor Q3 is connected. The field transistor Q3 has a gate and a source grounded, and a drain thereof is connected to the input buffer unit 13.

The antistatic circuit of the semiconductor device of the present invention having such a configuration is a value that is lowered by a predetermined voltage value by the voltage drop unit 22 when an abnormal voltage is applied through the input pad, and is input to the input pad 21. _Becomes | V _F + V _BB | Therefore, the junction region contacted with the input pad 22 is in the reverse state, and a large amount of electrons are not generated.

In this embodiment, although the structure of the antistatic circuit part is composed of two NMOS transistors, a resistor and a field transistor, other types of antistatic circuit parts can be used to achieve the same effect as the present invention.

In the present invention, a resistor is used as the voltage drop means, but any element can drop any other voltage.

As described in detail above, according to the present invention, when an abnormal voltage is applied, the voltage applied from the input pad is reduced by a predetermined value by the voltage drop means, thereby preventing the data stored in the cell region from being destroyed.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (2)

An antistatic circuit of a semiconductor device comprising an antistatic portion configured to receive a predetermined voltage from an input pad and operate when an input voltage value is a voltage value corresponding to static electricity to discharge static electricity. And a voltage drop means for lowering the voltage value when an abnormal voltage is applied from the input pad, between the input pad and the antistatic circuit portion. 2. The antistatic circuit of claim 1, wherein the voltage drop means is a resistor.