KR100192579B1 - Esd protection circuit of ic - Google Patents

Abstract

[Technical field to which the invention described in the claims belong]

An electrostatic discharge protection circuit of an integrated circuit.

[Technical Challenges to Invent]

The present invention provides a circuit for protecting an electrostatic discharge of an integrated circuit in a semiconductor device using two levels of operating voltage.

[Summary of the solution of the invention]

Use enhyeong Mohs transistor in the semiconductor device in the circuit to protect the internal integrated circuit from electrostatic discharge, then the first over a first and a 2P ^+-well and the substrate P ^_-well to form a guard ring region, and the third, First through fifth n ⁺ diffusion regions forming drains and sources of fourth and second N-type MOS transistors, and metal lines drawn from the input pads connected to the internal integrated circuit to the second and fourth n ⁺ diffusion regions And a metal line drawn from the first power supply terminal Vdd connected to the drains of the third and fourth N-type MOS transistors to the third n ⁺ diffusion region, and over the first to fifth n ⁺ diffusion regions. First to fourth polysilicon layers connected to each other and connected to a second power supply terminal Vss to form gate electrodes of the first, third, fourth, and second N-type MOS transistors, and the first n ⁺ diffusion. Region, First and Second Polysilicon The third and the fourth connection point is connected to the polysilicon features a composed of a metal line coupled to a second power supply terminal (Vss).

[Important Uses of the Invention]

Description

Electrostatic discharge protection circuit of integrated circuit

1 is a schematic configuration diagram of a conventional electrostatic discharge protection circuit.

2 is a schematic configuration diagram of an electrostatic discharge protection circuit according to an embodiment of the present invention.

3 is an exemplary implementation of an electrostatic discharge protection circuit according to an embodiment of the present invention.

4 is a plan view of the electrostatic discharge protection circuit according to an embodiment of the present invention.

5 is a cross-sectional view taken along the fold line X-X 'of FIG.

* Explanation of symbols for main parts of the drawings

D1, D2: Diodes Q1 ~ Q4: NMOS Transistors

42: input pad 10: internal integrated circuit

11: inverter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge (ESD) protection circuit in a semiconductor device, and more particularly to a circuit for protecting an electrostatic discharge of an internal integrated circuit in a semiconductor device using two levels of operating voltage.

In a highly integrated semiconductor device such as a memory, it is necessary to prevent the devices inside the chip from being destroyed by the stress voltage applied by the ESD phenomenon induced from the outside. In the case of a minute semiconductor device, even a small change in the sensitive external voltage is affected. Therefore, when such a stress voltage is applied from the outside, it must flow through a specific path. In the test process after the memory chip is completed, the ESD protection characteristic of the chip is checked by applying a stress voltage of 2500-3000V to an arbitrary pin. The problem of the device caused by the ESD phenomenon and its solutions are described in IEEE TRANSACTION ON ELECTRON DEVICES, Internal Chip ESD Phenomena the Protection Circuit, pp. 2133-2139, vol. 35, no. 12, DEC, 1989. In addition, reference may be made to Korean Patent Application No. 91-1128, which was previously filed by the present applicant, in order to be applicable to a wider range of ESD protection. In Patent Application No. 91-1128, an ESD mechanism is realized between a pin and a ground voltage, a pin and a power supply voltage, and a power supply voltage and a ground voltage.

As logic processes are shifting to 0.5 micrometers or less, the problem of processing 5V (volt) signals is serious. It is impossible to supply more than 3.3V to the power supply voltage of less than 0.5㎛ class, and when supplying more than 3.3V, the channel length is reduced and the thickness of the gate oxide is also reduced. . Therefore, maintaining that voltage continuously will result in reduced product life time.

However, in the current system, since 3V and 5V are mixed, even if a device having a class of less than 05㎛ is developed, it must be able to effectively process the 5V signal. There are two ways a 0.5 µm class device can handle 5V signals: 5V tolerang IO (Input Output) and 3V / 5V mixed IO. The latter 3V / 5V mixed IO can use both 3V and 5V as an input signal and an output signal, but in the former 5V tolerant IO, only the input signal is accepted as a 5V signal and 5V cannot be driven as an output. This is because the 0.5-m class apparatus cannot apply 5 V to the supply voltage Vdd. Nevertheless, 3V and 5V can be mixed because only the IO part is specially considered.

FIG. 1 is a schematic configuration diagram of a conventional electrostatic discharge protection circuit. In order to input the integrated circuit 10-data with respect to the ESD stress voltage coming from the data input pin, that is, the input pad 42, a well-known configuration is shown at the front end. Diode 11 is connected to the front end to protect the inverter 11 connected. As a result, a static current flows through the diode D1 to protect the integrated circuit 10 from electrostatic discharge.

However, according to this circuit configuration, when 5V is required to the integrated circuit 10, when 5V is applied to the input pad 42, when the power supply voltage Vdd is 3V, the diode D1 conducts, so that 5V cannot be applied. There is a problem.

Accordingly, an object of the present invention is to provide a circuit for protecting an electrostatic discharge of an internal integrated circuit in a semi-automatic apparatus using two levels of operating voltage.

Another object of the present invention is to provide a circuit for protecting electrostatic discharge when implementing 5V tolerant input and output in a semiconductor device using two levels of operating voltage.

The present invention for achieving the above object is a circuit for protecting an internal integrated circuit from electrostatic discharge by using an N-type transistor in a semiconductor device, the first and second P ⁺ wells to form a guard ring region, the substrate P ^- then the first, third, fourth, second en first to forming the drain and source of the Mohs transistor claim 5n ⁺ with the diffusion region, from an input pad connected to the internal integrated circuit the second and on the A metal line drawn to a 4n ⁺ diffusion region, a metal line drawn to the 3n ⁺ diffusion region from a first power terminal Vdd connected to drains of the third and fourth N-type transistors, and the first line First to second connected to the 5th ⁺ diffusion regions, one per two regions, and connected to a second power supply terminal Vss to form gate electrodes of the first, third, fourth, and second NMOS transistors. A 4 polysilicon layer and the 1n ⁺ diffused spirit On the contrary, it is characterized in that it is composed of a metal line connected to the connection point of the first and second polysilicon and the third and fourth polysilicon and connected to the second power supply terminal (Vss).

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In describing the present invention, if it is determined that detailed descriptions of related known functions or configurations may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2 is a schematic configuration diagram of an electrostatic discharge protection circuit according to an embodiment of the present invention, in which an n-MOS transistor Q3 is connected to a supply voltage Vdd. In this way, when a high level of surge voltage is applied to the input pad, the NMOS transistor Q3 connected to the supply voltage Vdd is turned on by the punch throuhg phenomenon between the source and drain, so that the current can be drawn out to the supply voltage Vdd. Will be.

3 shows an example of the actual implementation of the electrostatic discharge protection circuit according to an embodiment of the present invention, in which the node points are paralleled in the same manner as the connection form of the transistor Q3 and the diode D1 with the node point A shown in FIG. The transistor Q4 and the diode are connected with B as the center. However, the diode D1 and the added diode are implemented as NMOS transistors Q1 and Q2.

4 is a plan view of FIG. 3, and FIG. 5 is a cross-sectional view taken along the line X-X 'of FIG. First, the substrate P ^- well 45 is formed. P ⁺ wells are then formed as guarding regions. The metal line 43 is drawn from the input pad 42 to n ⁺ diffusion regions 32 to 36 and the metal line 51 is drawn from the power supply terminal Vdd to contact the drain and the source of the transistors Q1 to Q4. Polysilicon 38 to 41 form gate electrode regions of the transistors Q1 to Q4. In addition, the ground line metal line 44 is connected to the connection point of n ⁺ diffusion region 32 and two polysilicon 38, 39, and is connected to the connection point of n ⁺ diffusion region 36 and two polysilicon 40, 41. That is, the ground voltage Vss is applied to the gate 32 and the source (node point A) of the transistor Q1 and the gate 36 and the source (node point B) of the transistor Q2.

In the above structure, when a high level surge voltage is applied through the input pad 42, the drain depletion region expands when the n ⁺ diffusion region 34, i.e., the reverse bias voltage applied to the drains of the two transistors Q3 and Q4 increases. The electric field of the drain penetrates n ⁺ diffusion regions 33 and 35, that is, the source regions of the two transistors Q3 and Q4. Reference numeral BP in FIG. 5 denotes such a bulk punch through path.

As described above, the present invention has an advantage of preventing ESD when the 5V tolerant IO is implemented.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (1)

A circuit for protecting an integrated circuit from electrostatic discharge in a semiconductor device using two levels of operating voltages, the first and second P ⁺ wells 31 forming a guard ring region and the substrate P ^- well 100. First to fifth n ⁺ diffusion regions 32 to 36 forming a drain and a source of the first, third, fourth, and second N-type transistors Q1, Q3, Q4, and Q2 in order; A metal line 43 drawn from the input pad 42 connected to the internal integrated circuit to the second and fourth n ⁺ diffusion regions 33 and 35, and the third and fourth N-type transistors Q3, The metal line 51 drawn from the first power supply terminal Vdd connected to the drain of Q4) to the 3n ⁺ diffusion region 34 and on the first to 5n ⁺ diffusion regions 32 to 36. One to one connected per area and connected to the second power supply terminal Vss to form gate electrodes of the first, third, fourth, and second NMOS transistors Q1, Q3, Q4, and Q2. My The polysilicon layers 38 to 41 and the junction points of the 1n ⁺ diffusion regions 32, the first and second polysilicon 38, 39 and the third and fourth polysilicon 40, 41 And a metal line (44) connected to the second power supply terminal (Vss).