KR19980047253A - Copper wiring film formation method - Google Patents
Copper wiring film formation method Download PDFInfo
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- KR19980047253A KR19980047253A KR1019960065729A KR19960065729A KR19980047253A KR 19980047253 A KR19980047253 A KR 19980047253A KR 1019960065729 A KR1019960065729 A KR 1019960065729A KR 19960065729 A KR19960065729 A KR 19960065729A KR 19980047253 A KR19980047253 A KR 19980047253A
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- forming
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- copper wiring
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- 239000010949 copper Substances 0.000 title claims abstract description 54
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 53
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 41
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000005530 etching Methods 0.000 claims abstract description 35
- 239000010410 layer Substances 0.000 claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 239000000126 substance Substances 0.000 claims abstract description 10
- 238000000053 physical method Methods 0.000 claims abstract description 9
- 239000002344 surface layer Substances 0.000 claims abstract description 5
- 239000010408 film Substances 0.000 claims description 43
- 239000004065 semiconductor Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 239000010409 thin film Substances 0.000 claims description 11
- 239000007789 gas Substances 0.000 claims description 8
- 239000003795 chemical substances by application Substances 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 229920000642 polymer Polymers 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000007865 diluting Methods 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- 229910021591 Copper(I) chloride Inorganic materials 0.000 abstract description 13
- OXBLHERUFWYNTN-UHFFFAOYSA-M copper(I) chloride Chemical compound [Cu]Cl OXBLHERUFWYNTN-UHFFFAOYSA-M 0.000 abstract description 13
- 239000007795 chemical reaction product Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006884 silylation reaction Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/265—Selective reaction with inorganic or organometallic reagents after image-wise exposure, e.g. silylation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Inorganic Chemistry (AREA)
- Organic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
100℃ 이하의 저온에서 반응 생성물인 CuClx가 퇴적되고, 100℃ 이상의 온도에서는 감광막이 손상되는 문제가 발생되므로 사실상 구리의 식각이 불가능 하였던 종래 기술의 문제점을 해결하기 위한 본 발명은 구리 식각 마스크로 사용하는 감광막의 표면층을 화학적 물리적 방법으로 처리하여 감광막의 하부층은 당초 감광막의 특성을 유지시키고, 표면의 얇은 층을 식각용 마스크 특성이 우수하도록 변화시킴으로써 이중 층의 식각 마스크를 형성시키고, 이중 층을 구리 식각용 마스크로 사용하여 구리를 식각함으로써 구리 배선막을 용이하게 형성할 수 있도록 한 구리 배선막 형성 방법이 개시된다.The reaction product CuCl x is deposited at a low temperature of 100 ° C. or lower, and the photoresist film is damaged at a temperature of 100 ° C. or higher. Therefore, the present invention is directed to a copper etching mask. By treating the surface layer of the photoresist film to be used by chemical and physical methods, the lower layer of the photoresist film maintains the characteristics of the original photoresist film, and forms a double layer etching mask by changing the thin layer of the surface to have excellent etching characteristics. Disclosed is a method for forming a copper wiring film which can be easily formed by etching copper using as a mask for copper etching.
Description
본 발명은 반도체 장치 제조 방법에 관한 것으로, 특히 반도체 기판에 증착된 구리 박막을 식각하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for etching a copper thin film deposited on a semiconductor substrate.
반도체 소자의 배선 금속재로 알루미늄이 주로 사용되고 있으나, 최근 구리 금속을 차세대 배선 금속재로 도입하기 위한 연구가 활발히 추진되고 있다. 왜냐하면 구리는 알루미늄에 비하여 비저항이 60% 정도로 낮고, 일레트로 마이그레이션(electro-migration) 및 스트레스 마이그레이션(stress-migration) 내성이 우수하기 때문이다.Although aluminum is mainly used as a wiring metal material of semiconductor devices, researches for introducing copper metal as a next generation wiring metal material have been actively promoted. This is because copper has a specific resistance of about 60% lower than that of aluminum, and is excellent in electro-migration and stress-migration resistance.
종래의 구리 식각 기술은 Cl2를 기본으로 한 식각 반응 가스가 이용되어 고밀도 플라즈마 식각기로 구리를 식각하고 있다. 반응기 내에서 구리는 Cl기와 반응하여 CuClx를 용이하게 형성시킨다. 원활한 구리 식각을 위해서는 반응 생성물인 CuClx의 제거도 용이하여야 하나, CuClx의 기상 압력(vapor pressure)이 너무 낮기 때문에 통상적으로 사용하는 식각 공정 온도에서 CuClx의 제거가 거의 이루어지지 않는 문제가 해결되지 않고 있다.Conventional copper etching technology uses an etching reaction gas based on Cl 2 to etch copper using a high density plasma etcher. Copper reacts with the Cl group in the reactor to easily form CuCl x . CuCl x, which is a reaction product, should be easily removed for smooth copper etching. However, since Cuvapor x has a low vapor pressure, the removal of CuCl x is hardly achieved at the etching process temperature. It is not.
반도체 식각 공정에서는 일반적으로 감광막을 식각용 마스크로 사용하여 식각하고 있으며, 통상적인 식각 공정 한계 온도는 감광막의 열적 내성을 고려하여 100℃ 내외로 하고 있다. 구리는 Cl기와의 반응성이 크기 때문에 100℃ 이하의 저온에서도 CI 기와 반응하여 식각 생성물, CuClx를 용이하게 생성시킨다. 그러나, 식각 생성물인 CuClx는 기상 압력이 너무 낮기 때문에 식각 반응으로 생성된 CuClx는 제거되지 않고 반도체 기판 위에 계속 퇴적된다. CuClx의 퇴적이 어느 정도 두께만큼 이루어지면 CI기와 구리와의 접촉 통로가 차단되므로 구리 식각이 더 이상 진행할 수 없게 되는 것이다. 이때 식각 온도를 100℃ 이상으로 상승시키면 온도가 증가함에 따라 CuClx의 기상 압력이 상승되므로 고온일수록 CuClx를 보다 용이하게 제거할 수 있으나, 온도가 150℃ 이상으로 증가하면 식각 마스크로 사용되는 감광막이 손상되는 새로운 문제가 발생된다. 즉, 감광막은 150℃ 이상의 고온에서 손상되며, 이로 인하여 구리 식각 마스크 역할을 할 수 없게 되는 중대한 문제가 발생된다.In the semiconductor etching process, a photosensitive film is generally used as an etching mask for etching, and a typical etching process limit temperature is about 100 ° C. in consideration of thermal resistance of the photosensitive film. Since copper has high reactivity with the Cl group, it reacts with the CI group even at a low temperature of 100 ° C. or lower to easily produce an etching product, CuCl x . However, the etching product is CuCl CuCl x x produced by the etching reaction due to the vapor pressure too low is not removed and continued deposition on a semiconductor substrate. If CuCl x is deposited to some extent, the contact path between the CI and copper is blocked, and thus the copper etching can no longer proceed. At this time, if the etching temperature is increased above 100 ° C, the gas phase pressure of CuCl x increases as the temperature increases, so CuCl x may be more easily removed at a higher temperature, but when the temperature increases above 150 ° C, the photoresist used as an etching mask is used. There is a new problem of being damaged. That is, the photoresist film is damaged at a high temperature of 150 ° C. or higher, thereby causing a serious problem that it cannot serve as a copper etching mask.
따라서, 본 발명에서는 표면 변형층의 온도, 빛, 플라즈마 등에 대한 내성을 우수하게 함으로써 CuClx의 기상 압력이 충분히 커지는 온도 영역까지 식각용 마스크가 손상없이 유지될 수 있도록 하는 구리 배선막 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a method for forming a copper interconnection film which enables the etching mask to be maintained without damage to a temperature region where the gas phase pressure of CuCl x is sufficiently increased by excellent resistance to temperature, light, plasma, and the like of the surface modification layer. Its purpose is to.
상술한 목적을 달성하기 위한 본 발명은 소정의 반도체 제조 공정이 완료된 전체 구조 상부에 구리 금속막을 증착하는 단계와, 상기 구리 금속막 상부에 감광막을 도포한 후 소프트 베이킹을 실시하는 단계와, 상기 소프트 베이킹을 실시한 후 노광 장치를 이용하여 감광막의 선택된 영역을 노광시키는 단계와, 상기 감광 공정에 의해 감광막의 선택된 영역에 형성된 노광 영역과 비노광 영역 표면 층에 프리 실리레이션 베이킹 공정을 수행하는 단계와, 상기 감광막의 노광 영역 상부 표면에 변형층을 형성하는 단계와, 상기 감광막의 비노광 영역을 제거하는 단계와, 상기 비노광 영역을 제거하여 노출된 구리 박막을 식각하는 단계와, 상기 식각된 구리 박막 측면에 폴리머를 형성시키는 단계와, 상기 변형층과 노광된 감광막을 제거하고 구리 배선 금속막을 노출시키는 단계로 이루어진 것을 특징으로 한다.The present invention for achieving the above object is a step of depositing a copper metal film on the entire structure of a predetermined semiconductor manufacturing process, the step of applying a photosensitive film on the copper metal film and then performing a soft baking, the soft Exposing a selected region of the photoresist film using an exposure apparatus after the baking, performing a presiliation baking process on the exposed and non-exposed region surface layers formed in the selected region of the photoresist by the photosensitive process; Forming a strained layer on an upper surface of an exposed region of the photoresist layer, removing a non-exposed region of the photosensitive layer, etching the exposed copper thin film by removing the non-exposed region, and etching the exposed copper thin film Forming a polymer on the side, removing the strained layer and the exposed photoresist, and Exposing the film.
도 1A 내지 도 1C는 종래의 구리 배선막 형성 방법을 순서적으로 도시한 단면도.1A to 1C are cross-sectional views sequentially showing a conventional method for forming a copper wiring film.
도 2A 내지 도 2E는 본 발명에 따른 구리 배선막 형성 방법을 순서적으로 도시한 단면도.2A to 2E are cross-sectional views sequentially illustrating a method for forming a copper wiring film according to the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1 : 반도체 기판(silicon substrate)1: semiconductor substrate
2 : 구리 박막(Cu layer)2: Cu thin film
3 : 감광막(photo resist)3: photo resist
4 : 플라즈마 마스크(plasma mask)4: plasma mask
5 : 노광 영역(exposure area)5: exposure area
6 : 비노광 영역(non exposure area)6: non exposure area
7 : 폴리머층(polymer layer)7: polymer layer
8 : 변형층 또는 실리레이션 에이전트 확산층(sylilation agent diffusion layer)8: Strain layer or sylilation agent diffusion layer
본 발명을 첨부된 도면을 참조로 하여 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.
화학적 물리적 방법을 이용한 감광막의 표면 처리 과정을 DESIER(Diffusion Enhanced Silylastion Resist) 공정을 이용하여 설명하기로 한다.The surface treatment process of the photoresist film using chemical and physical methods will be described using a DESIER (Diffusion Enhanced Silylastion Resist) process.
도 1A 내지 도 1C는 종래의 구리 배선막 형성 방법을 순서적으로 도시한 단면도이다. 도 1A는 반도체 기판(1) 상부에 구리 박막(2)을 증착하고, 구리 박막(2) 상부에 감광막(3)을 도포한 후, 노광 장치를 이용하여 감광막(3)의 선택된 영역을 노광시킨 단면도이다.1A to 1C are cross-sectional views sequentially showing a conventional method for forming a copper wiring film. FIG. 1A shows that a copper thin film 2 is deposited on a semiconductor substrate 1, a photoresist film 3 is applied on a copper thin film 2, and a selected region of the photoresist film 3 is exposed using an exposure apparatus. It is a cross section.
도 1B는 노광 공정에 의해 감광막에 노광 영역(5)과 비노광 영역(6)이 형성된 단면도이다.1B is a cross-sectional view in which the exposure region 5 and the non-exposed region 6 are formed in the photosensitive film by an exposure process.
도 1C는 비노광 영역을 제거한 후 Cl2가스를 주종으로 하는 식각 가스를 플라즈마 식각기에 주입하여 비노광 영역이 제거된 부분의 구리 박막을 식각한 단면도이다. 이 경우, 전술한 바와 같이 100℃ 이하의 저온에서 반응 생성물인 CuClx가 퇴적되고, 100℃ 이상의 온도에서는 감광막이 손상되는 문제가 발생되므로 사실상 구리의 식각이 불가능하였다.FIG. 1C is a cross-sectional view of a copper thin film of a portion in which a non-exposed region is removed by injecting an etching gas mainly containing Cl 2 gas into a plasma etchant after removing the non-exposed regions. In this case, as described above, CuCl x as a reaction product is deposited at a low temperature of 100 ° C. or lower, and the photoresist film is damaged at a temperature of 100 ° C. or higher.
도 2A내지 도 2E는 본 발명에 따른 구리 배선 금속 식각 방법을 순서적으로 도시한 단면도로서, 본 발명은 DESIER 공정을 이용하여 구리 금속막을 식각한다. 도 2A에 도시된 바와 같이 반도체 소자가 심어진 반도체 기판(1) 상부에 구리 금속막(2)을 증착한다. 구리 금속막(2) 상부에 플라즈마 마스크(plasma mask)(4)를 도포한 후, 소프트 베이킹을 실시한다. 소프트 베이킹을 실시한 후 노광 장치를 이용하여 플라즈마 마스크(4)의 선택된 영역을 노광시키는 단면도이다. 이때, 플라즈마 마스크 하부 층에 의한 반사율을 감소시키거나, 요철로 인한 플라즈마 마스크 패턴의 손상을 감소시키기 위해서는 색소(dye)가 함유된 플라즈마 마스크를 사용할 수 있다.2A to 2E are cross-sectional views sequentially illustrating a copper wiring metal etching method according to the present invention. The present invention etches the copper metal film using a DESIER process. As illustrated in FIG. 2A, a copper metal film 2 is deposited on the semiconductor substrate 1 on which the semiconductor device is implanted. After applying a plasma mask 4 on the copper metal film 2, soft baking is performed. After performing soft baking, it is sectional drawing which exposes the selected area | region of the plasma mask 4 using an exposure apparatus. In this case, in order to reduce the reflectance caused by the lower layer of the plasma mask or to reduce damage of the plasma mask pattern due to irregularities, a plasma mask containing dye may be used.
도 2B는 감광 공정에 의해 플라즈마 마스크의 선택된 영역에 형성된 노광 영역(5)과 비노광 영역(6) 표면 층에서의 실리레이션(silylation) 선택비를 향상시키기 위한 목적으로 프리 실리레이션 베이킹(pre-silylation baking) 공정을 수행한 단면도이다.FIG. 2B is a pre-silicon baking (pre-) method for the purpose of improving the sililation selectivity in the exposed layer 5 and the non-exposed region 6 surface layer formed in the selected region of the plasma mask by a photosensitive process. It is sectional drawing which performed the silylation baking process.
도 2C에 도시된 바와 같이 화학적 물리적 방법을 사용하여 노광 영역 플라즈마 마스크의 상부 표면에 고온 내성이 우수한 변형층(8)을 형성한다. 플라즈마 식각 장비를 이용하여 실리레이션 되지 않는 비노광 영역의 플라즈마 마스크를 건식 해상(dry develop)으로 제거한다. 감광막 표면층에 변형층을 형성시키는 화학적 물리적 방법은 화학적 방법과 물리적 방법을 각각 실행하거나 동시에 실행할 수 있으며, 감광막 표면에 실리레이션 에이전트 등을 확산시키는 방법, 불순물 이온을 주입시키는 방법, 플라즈마로 처리시키는 방법, 빛 및 레이저 등을 방사(radiation)시키는 방법 등이 포함된다. 실리레이션 에이전트 확산층 형성 단계에서 공기 또는 질소 등의 가스를 실리레이션 에이전트와 희석시킴으로써 반도체 기판에서의 공정 균일성 향상 및 공정의 특성을 향상시킬 수 있다. 실리레이션 에이전트 확산층을 형성시킴으로써 구리 박막 식각시 요구되는 열 내성, 빛 내성, 플라즈마 내성, 기계적 내성, 화학적 내성, 물리적 내성 등에 대한 특성을 향상시킬 수 있다. 또한, 건식 해상 단계에서 O2에 He를 첨가함으로써 선택비를 향상시킬 수 있다.As shown in FIG. 2C, a strained layer 8 having excellent high temperature resistance is formed on the upper surface of the exposure area plasma mask using a chemical physical method. Plasma etching equipment is used to remove the plasma mask in the non-exposed region, which is not silicated, by dry develop. The chemical and physical methods for forming the strained layer on the photoresist surface layer may be performed simultaneously or simultaneously with the chemical method and the physical method. , Radiation and the like of radiation and the like. By diluting a gas such as air or nitrogen with the silicide agent in the silicide agent diffusion layer forming step, process uniformity and process characteristics on the semiconductor substrate may be improved. By forming the silicide agent diffusion layer, properties of heat resistance, light resistance, plasma resistance, mechanical resistance, chemical resistance, physical resistance, and the like required for etching the copper thin film may be improved. In addition, the selectivity can be improved by adding He to O 2 in the dry resolution step.
도 2D는 Cl2가스를 주종으로 하는 구리 식각 가스를 이용하여 비노광 영역의 구리 박막을 식각한 단면도이다. 도시된 바와 같이 변형층(8)을 식각 마스크로 사용하여 구리를 식각하는 것으로 고온에서도 마스크층의 손상없이 유지되므로 구리 식각이 가능하게 된다. 이때 구리가 식각된 측면에 폴리머(7)를 형성하는 기법을 이용하여 측벽 식각 방지 및 식각 기울기를 향상시킬 수 있다.FIG. 2D is a cross-sectional view of a copper thin film in an unexposed region using a copper etching gas mainly containing Cl 2 gas. As shown in the drawing, the copper is etched using the strained layer 8 as an etch mask, and thus copper etching is possible because the mask layer is maintained without damage to the mask layer even at a high temperature. In this case, by using a technique of forming a polymer (7) on the copper-etched side can be improved sidewall etching prevention and etching slope.
도 2E는 식각용 마스크 상부의 변형층(8)과 하부의 플라즈마 마스크(5)를 완전히 제거하고 구리 배선 금속막 (2) 패턴이 형성된 단면도이다. 이 공정 이후는 일반적인 반도체 제조 공정에 따라 제조하면 된다.FIG. 2E is a cross-sectional view in which the strained layer 8 on the etch mask and the plasma mask 5 on the bottom are completely removed and the copper wiring metal film 2 pattern is formed. What is necessary is just to manufacture after this process in accordance with a general semiconductor manufacturing process.
상술한 바와 같이 본 발명에 의하면 일반 감광막에 비하여 온도, 빛, 플라즈마 등에 대한 내성이 강한 변형층을 구리 식각용 마스크로 사용함으로써 구리 식각의 반응 생성물인 CuClx를 용이하게 제거할 수 있는 온도까지 식각 마스크 층을 손상없이 유지시킬 수 있도록 하여 구리 배선막 식각 공정을 용이하게 할 수 있으며, 감광막 표면에 얇은 변형층을 만듦으로써 극히 얇은 마스크를 이용한 식각이 가능하므로 고해상력의 초미세 패턴을 용이하게 형성할 수 있으며, 감광막 표면에 얇은 변형층을 만드는 것으로 건식 현상이 가능하게 되므로 습식 현상을 이용하는 일반 감광막에 비해 고해상력의 초미세 패턴을 용이하게 형성할 수 있는 훌륭한 효과가 있다.As described above, according to the present invention, by using a strained layer that is more resistant to temperature, light, plasma, and the like than the general photosensitive film as a mask for copper etching, etching is performed to a temperature at which CuCl x , which is a reaction product of copper etching, can be easily removed. By maintaining the mask layer without damage, it is easy to etch the copper wiring film, and by forming a thin strained layer on the surface of the photoresist, it is possible to etch using an extremely thin mask to easily form a high resolution ultra fine pattern Since the dry phenomenon is possible by making a thin strained layer on the surface of the photoresist film, there is an excellent effect of easily forming an ultrafine pattern of high resolution compared to a general photoresist using a wet phenomenon.
Claims (11)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960065729A KR100223015B1 (en) | 1996-12-14 | 1996-12-14 | Method for forming copper wiring film |
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| KR1019960065729A KR100223015B1 (en) | 1996-12-14 | 1996-12-14 | Method for forming copper wiring film |
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| KR19980047253A true KR19980047253A (en) | 1998-09-15 |
| KR100223015B1 KR100223015B1 (en) | 1999-10-01 |
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