KR19980046381A - Inter-signal signal preprocessor chip - Google Patents

Abstract

The present invention relates to a chip for signal transmission / reception processing between a high speed signal processor and a slave signal processor in an STM-64 synchronous optical transmission system. The purpose is to reduce the number of cables and reduce the number of cables by increasing the signal connection speed between STM-1, STM-4, STM-16 slave signal processing units and STM-64 high speed signal processing units in the STM-64 optical transmission system. To mitigate interference between the liver. Its characteristic is that it has a transmission function processing section and a receiving function processing section which are necessary for the preprocessing as an internal structure as a means for increasing the signal connection speed between self.

Description

Inter-signal signal preprocessor chip

The present invention relates to a chip for signal transmission / reception processing between a high speed signal processor and a slave signal processor in an STM-64 synchronous optical transmission system.

In general, since ITU-T standardizes the STM-N synchronous transmission scheme, STM-1, STM-4, and STM-16 optical transmission systems have been developed in Korea, and STM-64 optical transmission systems are currently being developed. In the existing system, since the signal capacity is not large, the high-speed signal processing unit and the subordinate signal processing unit transmit and receive data, clock, and FS signals at a speed of 100 Mbps or less, and do not use a separate chip for this purpose. In general, in a 10Gbps synchronous optical transmission system that processes STM-64 signals, all three signals, STM-1, STM-4, and STM-16, are accepted as dependent signals and multiplexed into STM-64 signals and transmitted. 1 is a signal connection diagram between a high speed signal processor and a slave signal processor in an STM-64 system. In the actual system implementation, a unit for processing the above three dependent signals and a high-speed signal processing unit for receiving the STM-64 electric signal and converting the light into an optical signal are mounted in a separate shelf. Therefore, the high speed signal processor and the slave signal processor are connected via a cable. In addition to the input and output data, the signal connected through the cable transmits a clock signal and an FS signal indicating the start of a frame. When the speed of the signal connected in such a system is 78Mbps, the number of signal connection cables is about 128 in one direction. Considering the signal connection in both directions, and considering the number of clock signals and FS signals, the number of connection cables between the slave signal processing unit and the high speed signal processing unit is about 300, which increases the system size and the interference between signals. There was a problem that the operation of the system is also unstable.

The present invention devised to solve the above problems increases the signal connection speed between the unit for processing STM-1, STM-4, STM-16 dependent signals and the unit for processing STM-64 high speed signals in the STM-64 optical transmission system. The purpose is to reduce the number of connecting cables and to mitigate interference between cables.

A feature of the present invention for achieving the above object is to have a transmission function processing unit and a receiving function processing unit necessary for the preprocessing as internal means for increasing the signal connection speed between the self.

That is, the connection speed is increased to a 622Mbps STM-4 signal, only data is connected, the clock is extracted by receiving the 622Mbps signal, and the FS signal is reframed and reproduced in the 622Mbps signal. On the other hand, for self-signal connection, the transmitter must generate and insert a frame scrambled signal to reproduce the FS signal and the scrambling of the clock extraction signal, and the receiver reproduces the FS signal through clock extraction and reframe. After that, a process of descrambling the signal is necessary. In addition, B1 byte processing for evaluating an error in signal connection is also required. In the present invention, a preprocessor for processing the above-mentioned functions is implemented, and the self-interconnection signal access preprocessor shown in FIG. 1 receives 12 52Mbps signals corresponding to 622Mbps capacity from the slave signal processing unit and processes eight of the above-mentioned functions. Outputs a 78Mbps signal. The eight 78Mbps signals are externally multiplexed into a 622Mbps signal via an 8: 1 multiplexer, which is a commercial product, and then transmitted to a high-speed signal processor. At the time of reception, the received 622Mbps signal is first transformed into eight 78Mbps signals through a commercial 1: 8 demultiplexer, and the clock is simultaneously extracted. The eight 78Mbps outputs of the 1: 8 demultiplexer are fed to the pre-self signaling preprocessor, which are then processed into twelve 52Mbps signals and sent to the slave signal processor. As shown in Fig. 2, the self-signal connection preprocessor handles the 622Mbps capacity for two channels and selectively handles the transmission / reception function by external control.

1 is a signal connection diagram between a high speed signal processor and a slave signal processor in an STM-64 system;

2 is a block diagram of a signal connection preprocessor between self,

3 is a detailed configuration diagram of a transmission function processing unit;

4 is a detailed configuration diagram of a reception function processing unit.

The configuration of the pre-self signal connection preprocessor of the present invention is as shown in FIG. The preprocessor shown in Fig. 2 processes 622Mbps capacity for two channels, respectively. Transmit function processor (10,30) and receive function processor (20,40) on one chip, and control the external selection signal to transmit and receive processing with one chip without increasing the number of chip I / O It was configured to be used. In addition, the processor includes a processor signal matching unit 70 so that the K1 / K2 overhead signal on the STM-4 frame and the operation of the processor can be processed in software.

The detailed configuration of the transmission function processing unit shown in FIG. 2 is the same as that of FIG. 3. 3 includes a phase aligner 12, a serial / parallel converter 13, an SOH inserter 14, a scrambler 16, a B1 calculator 15, a timing generator 17, and a processor signal matcher 70. ) Twelve 52 Mbps input data and 52 MHz clock and FS signals are connected to the input of phase aligner 12. The phase aligner 12 receives a system clock and a system FS from the outside and synchronizes input data with the system clock. Therefore, the phase aligner 12 outputs twelve 52 Mbps signals in synchronization with the system clock. The twelve 52 Mbps output signals of the phase aligner 12 are connected to the inputs of the serial / parallel converter 13. The serial / parallel converter 13 converts 12 52 Mbps signals corresponding to 622 Mbps into 8 78 Mbps signals. The eight 78 Mbps outputs of the serial / parallel converter 13 are input to the SOH inserter 14. The SOH inserter 14 receives the K1 / K2 byte value from the processor signal matching unit 70 and multiplexes it to the K1 / K2 byte position on the STM-4 frame. The SOH inserter 14 receives the timing signal from the timing generator 17 and inserts A1 / A2 bytes of the STM-4 frame, and receives the output of the B1 calculator 15 at the B1 byte position on the STM-4 frame. In the SOH inserter 14, eight 78 Mbps output signals with A1 / A2, B1 and K1 / K2 bytes inserted are connected to the input of the scrambler 16 and scrambled. The eight 78 Mbps output signals of the scrambler 16 are output to the output data of the inter-self signaling preprocessor and connected to the input of the B1 calculator 15 for B1 calculation. The B1 calculator 15 calculates a B1 byte value from the input data and sends it to the SOH inserter 14. The timing generator 17 supplies a timing control signal for the serial / parallel converter 13, the SOH inserter 14, the scrambler 16, and the B1 calculator 15 based on the system clock and the system FS signal. Then generate and send the output FS signal to the outside.

The detailed configuration of the reception function processor shown in FIG. 2 is the same as that of FIG. 4. The configuration of FIG. 4 includes a leaframer 28, a descrambler 26, a B1 calculator 25, a SOH extractor 24, a bottle / serial converter 23, a phase aligner 22, a timing generator 27 and The processor signal matching unit 70 is formed. Eight 78 Mbps input data and an input clock are connected to the input of the leaframer 28. The leaf reamer 28 detects A1 / A2 bytes from the input data and generates and outputs a reference FS signal indicating the position of the first A1 byte of the output data through a reframe process. The output FS signal of the leaframer 28 is connected to the input of the timing generator 27 to perform the function of initializing the timing generator 27. The eight 78 Mbps output signals of the leaframers 28 are commonly connected to the inputs of the descrambler 26 and the B1 calculator 25. The descrambler 26 performs a function of restoring the original signal by descrambling the scrambled input signal. The output of the descrambler 26 is connected to the inputs of the SOH extractor 24 and the B1 calculator 25. The B1 calculator 25 receives the eight 78 Mbps output signals of the leaframer 28, calculates the B1 bytes, and compares the B1 byte values extracted from the eight 78 Mbps signals input from the descrambler 26 to detect the B1 error. . The SOH extractor 24 extracts K1 / K2 bytes and sends the value to the processor signal matching unit 70. The eight 78 Mbps output signals of the processed SOH extractor 24 for overhead are connected to the input of the parallel / serial converter 23. The parallel / serial converter 23 converts eight 78 Mbps input signals into twelve 52 Mbps signals and outputs them. Twelve 52 Mbps output signals that are parallel / serial converted are connected to the input of the phase aligner 22. The phase aligner 22 receives a system clock and a system FS from the timing generator 27 as inputs and synchronizes input data with the system clock. Thus, the phase aligner outputs twelve 52 Mbps signals in synchronization with the system clock. The timing generator 27 controls timing necessary for the descrambler 26, the B1 calculator 25, the SOH extractor 24, and the bottle / serial converter 23 based on the output FS signal and the input clock of the leaf reamer 28. It performs a function of supplying a signal and receives a separate system clock and system FS signal from the outside to supply a timing control signal necessary for the phase aligner 22. The output clock and output FS signal are generated from the timing generator 27.

As described above, the present invention is applied to the STM-64 system, and thus the capacity of the system is gradually increased. Thus, the system can efficiently connect signal between the slave signal and the high-speed signal, and the preprocessor is used to process the signal. There is an effect that it is possible to reduce the size and to facilitate the construction of the optical transmission system by applying this method when implementing a larger capacity system. According to the present invention, in the STM-64 synchronous optical transmission system having a signal transmission speed of 10 Gbps, a method for reducing the number of connection cables between the high speed signal processor and the slave signal processor and a means for performing the necessary signal processing are provided. There is another effect in reducing the size of the system and enabling a more reliable system.

Claims (3)

An inter-self signal connection preprocessor chip as a means for increasing the inter-self signal connection speed, having a transmission function processing unit and a receiving function processing unit necessary for preprocessing. The method of claim 1, The transmission function processing unit, A phase aligner 12 which receives a system clock and a system FS from an external source, synchronizes input data with the system clock, and outputs 12 52 Mbps signals in synchronization with the system clock; A serial / parallel converter (13) converting the twelve 52 Mbps signals into eight 78 Mbps signals; It receives eight 78 Mbps outputs of the serial / parallel converter 13, receives K1 / K2 byte values from the processor signal matching unit 70, multiplexes them to K1 / K2 byte positions on the STM-4 frame, and generates the timing generator 17. A SOH inserter that receives the timing signal from the STM-4 frame and inserts A1 / A2 bytes and receives the output of the B1 calculator 15 into the B1 byte position on the STM-4 frame to output eight 78 Mbps signals. 14); Receiving the output signal of the B1 calculator 15 and receiving and scrambling the eight 78 Mbps signals of the SOH inserter 14 to output eight 78 Mbps signals as output data and to output to the input of the B1 calculator 15 Scrambler 16; And a B1 calculator 15 for calculating and outputting a B1 byte value from the input data, the serial / parallel converter 13, the SOH inserter 14, and the scrambler 16 based on a system clock and a system FS signal. And a timing generator (17) for supplying the timing control signal necessary for the B1 calculator (15), generating an output FS signal, and outputting it externally. The method of claim 1, The reception function processing unit, A leaframer 28 that receives eight 78Mbps input data and an input clock, detects A1 / A2 bytes from the input data, and generates and outputs a reference FS signal indicating the position of the first A1 byte of the output data through a reframe process. ; A descrambler 26 which receives the eight 78 Mbps output signals of the leaf reamer 28 and descrambles the scrambled input signal to restore the original signal; B1 calculator for detecting the B1 error by receiving the eight 78 Mbps output signals of the leaf reamer 28, calculating the B1 bytes, and then comparing the B1 byte values extracted from the eight 78 Mbps signals input from the descrambler 26 ( 25); An SOH extractor 24 receiving the output signal of the descrambler 26 and extracting K1 / K2 bytes and outputting the value to the processor signal matching unit 70; A bottle / serial converter (23) for receiving eight 78 Mbps output signals of the SOH extractor (24) which has been processed for overhead, and converting them into 12 52 Mbps signals and outputting them in parallel / serial conversion; A phase aligner 22 that receives the parallel / serial converted 12 52 Mbps output signals and receives a system clock and a system FS as inputs, and synchronizes input data with the system clock to output 12 52 Mbps signals in synchronization with the system clock; ; And initializing itself by receiving the output FS signal of the leaf reamer 28 and timing necessary for the descrambler 26, the B1 calculator 25, the SOH extractor 24, and the bottle / serial converter 23. Before the self-connection signal connection characterized in that it comprises a timing generator 27 for supplying a control signal and receiving a separate system clock and system FS signal from the outside to supply the necessary timing control signal to the phase aligner 22. Processor chip.