KR100713358B1 - Apparatus and method for sharing tributary unit shelf - Google Patents

Abstract

The present invention allows the slave units to use a common shelf, and can recognize and use them by software control even when an arbitrary card / any slot of the shelf is applied. The TInU accommodates all ISLU / HU functions and interfaces with the high speed unit to solve the back plane complexity and system structural problems.

Dependency Self, Common

Description

Dependent self-sharing device and method {APPARATUS AND METHOD FOR SHARING TRIBUTARY UNIT SHELF}             

1A to 1C are diagrams illustrating self-configuration of a slave unit (TSS-1 / TSS-4 / TSS-16) according to the prior art in a transmission system including various types of slave units (155 Mbps / 622 Mbps / 2.5 Gbps).

2 is a configuration diagram of a slave unit (TSS-1 / TSS-4 / TSS-16) according to the prior art in a transmission system including slave units of various types (155 Mbps / 622 Mbps / 2.5 Gbps).

3 is a system configuration diagram according to an embodiment of the present invention;

4 is a high-speed unit (HSS) and dependent unit (TSS) self-configuration diagram according to an embodiment of the present invention,

5 is a diagram illustrating a main signal processing method from a slave unit (TSS) to a high speed unit (HSS);

FIG. 6 is a diagram illustrating the logic of each part of FIG. 5.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous digital hierarchy (hereinafter referred to as " SDH ") transmission system, and more particularly to a transmission system composed of several types (155 Mbps / 622 Mbps / 2.5 Gbps) of subordinates. 155 Mbps / 622 Mbps / 2.5 Gbps) to the method of sharing the Self (Shelf).

For example, the prior art in a 10 Gbps transmission system composed of several types (155 Mbps / 622 Mbps / 2.5 Gbps) of slave units (Tributary's Signal Shelf) TSS-1 / TSS-4 / As shown in the TSS-16 self configuration, it is composed of three dedicated slave selfies, a 155 Mbps dedicated self (2), a 622 Mbps dedicated self (4), and a 2.5 Gbps transmit self (6). It has the flexibility of its subordinates within. In this case, the problem can be considered in the following three aspects. The first is from the point of view of the space, the second is from the complexity of the backplane configuration, and the third is from the aspect of system architecture.

1) Aspect of charge space

The 10Gbps transmission system consists of two parts of high speed self, one optical amplification self and a slave part. If the capacity required for each unit of 155Mbps, 622Mbps, 2.5Gbps is required by the system for each slave configuration, each unit is needed one by one, and all three slave units are needed one by one. In other words, it takes up a lot of unnecessary blanks in each shelf. In the case of 155Mbps, 2.5Gbps capacity processing (16 channels) is possible, whereas if only one channel is used, the remaining 15 channels are wasted and 622Mbps is used. While 5Gbps capacity processing (8 channels) is possible, if only one channel is used, the remaining seven channels are wasted. In the case of 2.5Gbps, 10Gbps capacity processing (4 channels) is possible, but if only 1 channel is used, 3 channels are wasted. This is the reason why a 10Gbps system is composed of two racks instead of one rack, which takes up a lot of space in the telephone office where equipment is being installed, resulting in economic losses, maintenance and management. Subsequent maintenance costs also contribute to economic losses, which take up a lot, and also increase the cost of materials, causing a loss of competitiveness.

2) Complexity when constructing back plane

FIG. 2 shows a system structure of a slave unit (TSS-1 / TSS-4 / TSS-16) which processes a unit of 155 Mbps (TSS-1), 622 Mbps (TSS-4), and 2.5 Gbps (TSS-16). FIG. 3 shows a Tributary Interface STM-n interface unit (TInU) (n = 1/4/16) ↔ ISLU in each of the TSS-1 (10), the TSS-2 (20), and the TSS-16 (30). Displays the amount of data actually processed on the interface with / HU (Interface Shelf Low-speed Unit / High-speed Unit). In the case of TSS-1 (10), if the number of 52Mbps data processing is 3 x 16 x 2 = 96, including the clock line (16 x 2 = 32), the total number of 128 data lines and clock lines is processed. do. In the case of the TSS-4 20, when the number of 52 Mbps data processing includes 12 x 8 x 2 = 128 clock lines (8 x 2 = 16), a total of 144 data and clock lines are processed. In the case of the TSS-16 (30), when the number of 52 Mbps data processing includes 48 x 4 x 2 = 384 clock lines (16 x 2 = 32), a total of 416 data and clock lines are processed.

As described above, in the case of TSS-1 (10), 128 data and clock lines for processing pure data, and in the case of TSS-4 (20), 144 data and clock lines for processing pure data, TSS- For 16 (30), a complex configuration where 416 data and clock lines to process pure data must be processed in each TSS-1 / TSS-4 / TSS-16 (10) (20) (30) back plan This can cause significant problems for reproducibility problems.

3) System structural aspect

As shown in FIG. 2, the TInU (n = 1/4/16) signals are interfaced to the high speed unit through a 622Mbps cable via the ISLU / HU. In ISLU included in TSS-1 (10), FPA (Frame & Phase Alignment) processing function, K1 / K2 processing function, 622Mbps multiplexing / demultiplexing (MUX / DMUX) function, clock conversion function, etc. ISHU included in TSS-4 (20) and TSS-16 (30) provides K1 / K2 processing function, 622Mbps multiplexing / demultiplexing function, and clock conversion function. , SOHP (Section Over Head Processor) processing function. The main signal processing in the slave part is interfaced with the high speed part through two stages of TInU (n = 1/4/16) and ISLU / HU. If possible, the main signal processing is performed in several stages or when the clock system is not an integer multiple. This can have a big impact on product reliability.

As described above, as seen from the viewpoint of the charge space, the complexity of the back plane configuration, and the viewpoint of the system structure, the prior art affects the economy, the reproducibility, and the reliability of the product. It has a problem that can cause it.

Accordingly, an object of the present invention is to provide an apparatus and method for sharing a slave part of this type (155 Mbps / 622 Mbps / 2.5 Gbps) in a transmission system composed of several types (155 Mbps / 622 Mbps / 2.5 Gbps). It is.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the same elements in the figures are represented by the same numerals wherever possible. In addition, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

In the present invention, the problem of the charge space among the problems of the prior art is that the slave units use a common shelf, and software control is possible even when the random card / Any slot of the shelf is applied. This can be recognized and used by. This minimizes the amount of blanking that can occur. And the remaining problems of the prior art, the back plane (complex) and structural problems of the system is solved by the interface to the high-speed unit to accommodate all the ISLU / HU function in the TInU.                     

3 is a diagram illustrating a system configuration according to an exemplary embodiment of the present invention, which is a self-incorporating high-speed signal shelf (HSS) self 40 for processing a high-speed signal and a self-incorporating signal for processing a dependent signal. It is divided into tributary's signal shelf (TSS) shelves 60. According to an embodiment of the present invention, as shown in the system structure of FIG. 3, an arbitrary card / arbitrary slot may be arbitrarily mounted to one common slave unit 60 such that the TI1U / TI4U / TI16U units 62, 64, and 66 may be mounted. (Any card / Any slot) is adopted. The interface with the ADCU 46 of the high speed unit 40 is configured to mount 8 channels of 155 Mbps in the TI1U (155 Mbps) unit 62 of the slave unit 60 based on the 622 Mbps data and the TI4U (622 Mbps) unit (64). ) Is configured to mount 622Mbps of 2 channels. In addition, TI16U (2.5Gbps) unit 66 was configured to mount one channel. The reason for the above configuration is that when the TI1U (155 Mbps) is processed to one channel at 155 Mbps, when interfaced with the high speed unit 40, the number of interface cables to the high speed unit 40 increases, and the input of the high speed unit 40 is 622 Mbps. Because it is. In case of TI1U (155Mbps) 8 channel capacity, the total self-processing capacity is 10Gbps capacity, and 1Self is maximized when using TI1U (155Mbps) as the 10Gbps total capacity.

The purpose of accommodating two channels of the TI4U (622Mbps) unit 64 of the slave unit 60 is to accommodate 10 Gbps of total capacity in one self. It is preferable that the widths of the TI1U / TI4U units 62 and 64 are the same in the slave unit 60, for example, about 25 mm is appropriate. In the slave unit 60, the TI16U (2.5 Gbps) unit 66 can accommodate 10 Gbps full capacity in one cell, so that only one channel can be accommodated. It is desirable to make the width twice the width of the TI1U / TI4U units 62 and 64. The slave unit 60 excludes the main data processing function of the ISLU / HU and integrates it into the interface shelf unit (ISU) 68. The ISU 68 receives the reference clock from the System Timing Generator Unit (STGU) 48 of the high speed unit 40 and supplies the system to the units 62, 64, and 66 of the TInU (n = 1/4/6). It supplies a clock and interfaces between order wire (O / W) data from TInU (62, 64, 66) and order wire interface unit (OWU) 54, which is an O / W processing unit of high speed unit 40. I also have The Tributary DCC Controller Unit (TDCU) 70 of the slave unit 60 processes the Data Communication Channel (DCC) from the TInUs 62, 64, and 66 in the same manner as the prior art. In the prior art, the TPU is used to control and monitor each TInU, ISLU, and ISHU. However, in the embodiment of the present invention, the MPU (Main-signal Processor Unit) 50 of the high speed unit 40 is connected to all of the slave units 60. It is structured to process units. This allows the MPU 50 to reduce message loss between all units of the slave unit 60 and the MPU 50 of the high speed unit 40.

4 is a system shape of the high speed part (HSS) 40 and (b) of FIG. 4 is a shape of the subordinate part (TSS) 60. As shown in FIG. System shape. In the system configuration of the slave unit 60 shown in (b) of FIG. 4, an interface shelf unit (ISU), which is a slave unit for self-interface interface, and a TDCU, which is a unit that processes data for slave communication, are basic functions in the self. The TInU is a fixed unit that handles any one of the TI1 unit 62, the TI4U unit 64, and the TI16U unit 66. In such a shape, even if all 16 pieces are used as a working unit, there is no problem. To do this, the data that needs to be processed by the software is quite complicated, but it can be sufficiently implemented in the future considering that the main role of the system is software, not hardware.

The present invention maintains the 622Mbps interface between the high speed portion (HSS) 40 and the slave portion (TSS) 60 as shown in the system structure of FIG. A signal processing process using the interface and a data processing method in TInU (n = 1/4/6) in the slave unit (TSS) 60 will be described with reference to FIGS. 5 and 6.

FIG. 5 is a diagram illustrating a method of processing main data from a slave unit (TSS) 60 to a high-speed unit (HSS) 40 according to an embodiment of the present invention, and FIG. 6 is a block diagram of the logic units of FIG. 5. It is also.

In the process of processing the main data from the slave unit (TSS) 60 shown in FIG. 5 to the high-speed unit (HSS) 40, signals from TInU ↔ ADCU (Add-Drop Controller Unit) ↔ HSU (High Speed interface unit) Are shown in the working line W and the protection line P, and divided into an uplink signal and a downlink signal, respectively.

In FIG. 5, notes (1) to (6) are shown for explanation of the logic parts of TInU ↔ ADCU ↔ HSU, and in FIG. 6, partial logic is shown as notes (1) to (6). The configuration is shown and the description of the operation of the partial logic is as follows.

Note (1): After processing SOHP function in TInU as an uplink signal, interface with ADCU of HSS 40 through DRV (DRiVer) and supply it to the working and standby unit of ADCU. .

Note (2): Working and standby unit of HSU via DRV at TSI (Time Slot Interface) of ADCU of HSS 40 received from TInU of slave unit (TSS) 60 as an uplink signal Supply to (Protection Unit).

Note (3): The signal received from the ADCU of the high speed unit (HSS) 40 is used as the uplink signal by using the working signal and the protection signal through the SEL as the final uplink signal.

Note 4: The signal provided by the ADCU of the high speed unit (HSS) 40 is a downlink signal, and the working signal and the protection signal are SEL (SELector) in the TInU of the slave unit (TSS) 60. It is used as the final downlink signal through.

Note (5): The signal provided by the HSU of the high speed part (HSS) 40 as a downlink signal is passed through the SEL and the operation signal and the protection signal in front of the ADCU and the TSI. 60) to provide a signal.

 Note 6: The downlink signal provides an operation signal and a protection signal from the HSU of the high speed unit (HSS) 40 to the ADCU via the DRV.

The present invention described above can reduce the charge space, reduce the maintenance cost following maintenance and management, reduce the economic loss as well as the material cost, strengthen the competitiveness, and design a complex structure of the back plane with a simple structure to reproduce problems In addition, it reduces material costs, reduces main data processing to three stages, and increases the reliability of the product by unifying the clock system. This is summarized as follows.                     

1) occupy space

In the prior art, when one TI1U / TI4U / TI16U is used as a slave unit (TSS), the minimum self-configuration is composed of three types so that the entire high-speed unit (HSS) and the optical amplifier shelf (OAS) can be configured. The system was formed of two racks. However, in the present invention, the above condition can be configured as one self by using an Any card / Any slot method using the common TTS as the common part as described above. When 155 Mbps is used as the total capacity of 10 Gbps, the conventional technology is composed of 4 cells, but in the present invention, the self-configured 10 Gbps system can be configured from 2 racks to 1 rack. As a result, maintenance costs following maintenance and management can be reduced, economic loss and material costs can be reduced, thereby enhancing competitiveness.

2) Complexity in constructing back plane

Conventionally, by processing the slave unit (TSS) signal with TInU ↔ ISLU / HU, the signal for working and protection line was processed at a TTL level of 52 Mbps. For this reason, the number of layers of the TSS back plne is very complicated, about 14 to 16, and thus the reproducibility of the normal operation is somewhat reduced due to the impedance mismatch generated during mass production. However, in the present invention, since the slave unit (TSS) signal is directly processed by the TInU to interface with the high speed unit (HSS), the configuration of the slave unit (TSS) back plane is simplified to about 6 to 8 layers. Many important aspects of back plane fabrication will disappear, and the problem of abnormal behavior will disappear.                     

3) System structural aspect

Conventionally, 78 Mbps data is used for the high speed part (HSS) and 52 Mbps data is used for the slave part (TSS) to convert 78 Mhz → 52 Mhz from ISLU / HU of the slave part (TSS). Dispense → 2 multiply → 52Mhz system clock was generated and used. Due to the slip phenomenon between the high speed unit (HSS) and the slave unit (TSS) generated in the above process has a little unstable system clock (System clock) system in the present invention, but the high speed unit (HSS) that completely excludes 52Mhz in the present invention ) And slaves (TSS) using a single 78Mhz system clock to increase reliability. In addition, in the notes 1 to 6 of FIG. 6, the signals of the slave part in the main parts 2 and 5 receive both the working signal and the protection signal in the TSI of the high speed part. The structure that can accommodate both DRI (Dual Ring Interworking), DNI (Dual Node Interconnection) in the network.

In the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the equivalent of claims and claims.

As described above, the present invention can make the slave unit of this type (155 Mbps / 622 Mbps / 2.5 Gbps) common in a transmission system composed of several kinds (155 Mbps / 622 Mbps / 2.5 Gbps).

Claims (2)

In a transmission system having a plurality of dependent signals, A high speed unit that multiplexes the dependent signals, converts and converts the optical signals into optical signals, and mounts a high speed unit to interface with an operator; A slave unit which commonizes the slave unit units for processing the plurality of slave signals into one; The dependent self; A plurality of slave units which process the plurality of slave signals; An ISU which receives a reference clock from the high speed unit, supplies a system clock to each of the subordinate units, and interfaces between the request data of the subordinate units and the request data processing unit of the high speed unit; The slave unit self-sharing apparatus according to claim 1, wherein the main processor of the high-speed unit itself processes data of each unit of the slave unit. In the slave self-sharing method in a transmission system having a plurality of dependent signals, Comprising a high speed unit for mounting a high speed unit for converting and transmitting an optical signal by converting the dependent signals into an optical signal, and a slave unit for commonizing the slave unit processing the plurality of slave signals into one Letting the process Allow a plurality of slave units of the slave unit to process the plurality of slave signals, the ISU of the slave unit receives a reference clock from the high speed unit and supplies a system clock to each of the slave units; Interfacing the request data of the slave unit and the request data processing unit of the high speed unit; The slave unit self-sharing method of claim 1, wherein the main processor of the high-speed unit self processes data of each unit of the slave unit self.

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