KR19980045613A - Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, wherein the channel impurity concentration under the floating gate stage and the channel stop impurity concentration under the field oxide film separating the element and the device are formed to be equal to each other. Therefore, the program isolation speed and the erase operation speed as well as device isolation characteristics can be enhanced.

Description

Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device for improving device isolation characteristics and a program erase operation speed, and a manufacturing method thereof.

In general, a nonvolatile semiconductor memory device injects electrons into a floating gate defined as a floating node by an electrical signal to write data or emit electrons from a floating gate to erase data. The unit cell is operated by applying a high voltage generated in a circuit pumped from an external 5V or 3.3V power supply to each node of the cell.

1 is a cross-sectional view of a stacked gate according to an embodiment of the prior art. Referring to FIG. 1, a program operation of injecting electrons into the floating gate 6 of a flash volatile semiconductor memory device of a quinoa type is about 6 V applied to a drain gate 3 and about a control gate 8 that controls the floating gate 6. A voltage of about 10V is applied. At this time, the common source line 9 and the bulk voltage are grounded. The high voltage applied to the drain 3 and the control gate 8 causes the operating mode of the memory cell to become saturated, and drains from the source region 3. Among the electrons flowing to the third side, hot electrons having high energy in the depletion region 4 near the drain 10 are injected into the floating gate 6 to be programmed, thereby increasing the threshold voltage of the memory cell. Since the program operation efficiency can be maximized by the generation of hot electrons by the strong electron field near drain 10, the high channel concentration near the drain 3 of the transistor induces a strong electric field, causing many hot electrons to be generated. The threshold voltage of the programmed memory cell can be ensured. In addition, the erasing operation for erasing data of the memory cell is performed by removing electrons from the floating gate 6 in bulk or sector units. A high voltage of about 12V is applied to the common source line 9 and the control gate 8 is about 0V. Thus, electrons in the floating gate 6 are emitted to the source region 3 by the electric field through the tunneling oxide 5 in which the source region 3 and the floating gate 6 overlap. When applying such a high voltage to the source junction, the drain junction should be a floating node to prevent punch-through. The method of erasing the data of the memory cell by applying the high voltage to the source junction is not only severe generation of band-to-band tunneling current due to thin tunneling oxide in the region where the source junction and floating gate 6 overlap, but also occurs during operation. Most of the electrons in the electron-hole pairs are sourced, but the holes are trapped in the oxide film 5, thereby lowering or damaging the potential barrier, which may cause reliability problems. To overcome this drawback, a low voltage of about 5V is applied to the source region 9 and a negative bias of about -10V is applied to the control gate 8 to erase the data of the memory cell. Since it is applied, there is an advantage to reduce the capacity generated in the internal pumping circuit, and because the band-to-band tunneling current is also reduced, damage to the tunneling oxide during the erase operation is reduced. Since the erase operation by the above two methods is performed through the tunneling oxide film in the region where the high concentration of the source junction and the floating gate 6 overlap, the source impurity concentration in the region where the source and the gate overlap is low in the overlapped region. Depletion layer 2 caused by an electric field may occur to reduce the erase efficiency.

An object of the present invention for solving the above problems is to provide a nonvolatile semiconductor memory device and a method of manufacturing the same that can improve the operation efficiency of writing and erasing.

Another object of the present invention is to provide a nonvolatile semiconductor memory device having improved insulating properties between devices and a method of manufacturing the same.

1 is a view showing a cross-sectional structure of a stacked gate according to an embodiment of the prior art,

2 is a view showing a cross-sectional structure of a stacked gate according to an embodiment of the present invention,

3 to 6 are cross-sectional structures illustrating a stacked nonvolatile unit cell according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In addition, specific details such as specific components are shown in the following description, which will be provided to help a more general understanding of the present invention, and it will be apparent to those skilled in the art that the present invention can be implemented without these specific details. . In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2 is a cross-sectional view illustrating a stacked gate according to an embodiment of the present invention, and FIGS. 3 to 6 are cross-sectional structures illustrating a stacked nonvolatile unit cell according to an embodiment of the present invention. It will be described with reference to the drawings at the same time. Conventional memory cell manufacturing is characterized by growing a thick field oxide layer after implanting channelstop impurities of the same type as the substrate for separation between the device and the device, and using a method of improving the program characteristics of the memory cell. The problem is that the complexity of the process, such as ion implantation at a large tilted angle of about 45 ° and a separate photomask process is added to produce a source region and other drain junction, but the present invention is stacked After the gate is self-aligned and dry etched, the source and drain junctions can be made identical through a single photomask process. To this end, by implanting impurities of the same type as the substrate with high energy to form high impurity regions not only in the channel region under the gate but also in the channel stop region under the field oxide layer, the memory cells can be programmed and erased efficiently as well. It has the advantage of improving device isolation between cells at the same time. FIG. 3 shows a thin tunneling oxide film 5a of about 90 Hz on a semiconductor substrate of a first conductivity type, and a first polysilicon 6a doped with a fockle for floating gate 6 is laminated, and then the oxide / nitride / oxide film 3 As a process diagram after laminating an interlayer insulating film 7a having a layer structure and laminating doped polysilicon and tungsten silicide 8a, the polyside gate is used as a control gate 8 for controlling the floating gate. FIG. 4 is a process diagram after dry etching the control gate 8, the interlayer insulating layer 7, and the floating gate 6 by self alignment using a photomask process. 5 is a photomask process in which the peripheral circuit area is covered with photoresist after the self-aligned dry etching process, and the memory cell array area is a photomask process which completely removes the photoresist. As the process chart after ion implantation, the impurities to be ion-implanted are characterized in that boron ions are commonly used and the amount of implanted is about 5E13 / cm 2. This is because the electric field is strengthened due to the increase in the concentration of the junction in contact with the drain to be formed in the subsequent process, which maximizes the hot carrier generation during the program operation of the memory cell, and improves the program speed, and at the same time depletes the source junction during the erase operation. Suppress FIG. 6 is a process of forming a drain and a source region of a memory cell, and ion implantation at a high concentration of about 6E15 / cm 2 maximizes an electric field at a source and a drain junction. Thereafter, at a low temperature, a relatively thin oxide film of about 150 kV is grown to form a gate burdick. Subsequently, an interlayer insulating film 7 of HTO / BPSG is stacked, and a contact hole is opened to connect metal wiring. The method of manufacturing a memory cell has been briefly described, and the implementation of the present invention not only realizes high program speed and erase operation speed, but also contributes to improvement of insulation characteristics between memory cells.

According to the present invention as described above, in order to prevent degradation of the erasing efficiency, a high impurity region is formed near the source junction, similarly to the drain junction, to suppress the occurrence of the depletion region. Impurity formation in the channel region in contact with the drain region and the source region, as well as channel stop impurity formation under the thick field oxide film, may be performed in the same process step without a separate photomask process. In addition, since the memory cells are highly integrated and the channel width is decreased, the impurity concentration of the channel is high, thereby preventing the punch-through phenomenon caused by the drain electric field, thereby achieving scale down of the memory cell. In addition, since the impurity implantation process is performed with high energy, the same type of impurity as the substrate is implanted in the field oxide layer area between active and active, and thus, the insulating property between devices can be improved.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by those equivalent to the scope of the claims.

Claims (6)

A nonvolatile semiconductor memory device comprising a floating gate stage for storing data and a control gate for controlling and biasing the floating gate stage; And a channel stop impurity concentration under the field oxide layer separating the element and the device from the channel impurity concentration under the floating gate stage. The method of claim 1; And the channel impurity and channel stop impurity have the same conductivity type as the substrate. The method of claim 1; And the channel impurity and channel stop impurity are formed after the control gate is formed. A method of manufacturing a nonvolatile semiconductor memory device, comprising: a unit memory cell having a floating gate for storing data and a control gate capable of controlling and biasing the data; Forming a silicon substrate of the first conductivity type or an impurity well region of the same conductivity type as the substrate; Forming a device isolation insulating film on the silicon surface to separate active and inactive regions; Depositing a tunneling oxide film in the active region; Forming a floating gate by laminating polycrystalline silicon of a first conductor on the tunneling oxide film; Forming an interlayer insulating film on the floating gate and forming a control gate made of polysilicon and tungsten silicide of the second conductor, Forming a stack-type gate by selectively etching the second conductor, the interlayer insulating film, and the first conductor by self-alignment; Removing the photoresist of the memory cell array region using a photo mask process and simultaneously implanting impurities of the same conductivity type as the substrate to simultaneously form a high concentration of impurity regions under the channel region and the field oxide layer; Implanting arsenic ions to form a high concentration of source and drain regions; A method of manufacturing a nonvolatile semiconductor memory device, comprising the step of forming a gate burdock by performing a high temperature heat treatment. The method of claim 4; The energy of the ion implantation under the channel and field oxide layer region is between about 150 KeV and 300 KeV. The method of claim 4; And a thickness of the tunneling oxide film is about 100 GPa or less.